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Cypress AN1196 manual

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Table of contents for the manual

  • Page 1

    November 21, 2002 Document No. 001-431 17 Rev . ** 1 EZ-USB FX2™ PCB Design Recommendations Introduction This application n ote presents recommendati ons for design- ing with the Cypress Semiconductor EZ-USB FX2™ compo- nent. T echniques for high-speed desi gn should be applied to circuits using the EZ-USB FX2. Du e to the packaging and high pe[...]

  • Page 2

    November 21, 2002 Document No. 001-431 17 Rev . ** 2 AN1 196 Figure 2. FX2 Eye Diagram of High-speed Signali ng In the diagram, notice how no signal traces overlap the cen- tral, six-sided, shade d area. Also, no trace overlaps the extremes of permissible volt age as shown in the shaded lin es at the very top and very bottom of the figure. Overlap [...]

  • Page 3

    November 21, 2002 Document No. 001-431 17 Rev . ** 3 AN1 196 Maint ain PCB T race Impedance Designing the PCB traces for particular ch aracteristic imped- ance is very important to signal quality . The USB specification requires controlled impedance a mong all elements in the USB data path. The differential impedance of each USB data pair should be[...]

  • Page 4

    November 21, 2002 Document No. 001-431 17 Rev . ** 4 AN1 196 This figure shows the die lectric material thickness (“Prepreg”) between layers 1 and 2 and the thickness between layers 3 and 4. The dimensio ns between these layers are a key ele- ment in the design to se t the proper characteristic impedance for the USB data traces. This is the “[...]

  • Page 5

    November 21, 2002 Document No. 001-431 17 Rev . ** 5 AN1 196 The design of the land area fo r the expose d paddle is critical to proper thermal transfer . A copper fill is to be designed into the PCB and under the QFN in order to assist thermal trans- fer . Fig ure 5 is the diagram of the PCB land area for the EZ- USB FX2. Figure 5. Diagram of the [...]

  • Page 6

    November 21, 2002 Document No. 001-431 17 Rev . ** 6 AN1 196 EZ-USB FX2 Assembly Recommenda- tions The solder stencil over the expos ed p addle is required to per- mit at least 50% solder application coverage. Figure 8 is a graph from Amkor research showing how solder void mu ch less than 50% has little influe nce on thermal transfer . The package [...]

  • Page 7

    AN1 196 Cypress Semico nd uctor 198 Champi on Cou rt San Jose, CA 9513 4-1709 Phone: 408- 943-2600 Fax: 408-94 3-4730 http://www.cypr ess.com © Cypress S emiconductor Corpora tion, 2002-2007. The information containe d herein is subjec t to change with out notice. Cypres s Semiconductor Corporation a ssumes no resp onsibility for t he use of an y [...]