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Cypress AN6077 manual

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Table of contents for the manual

  • Page 1

    February 19, 2008 Document No. 001-15342 Rev . ** 1 with FX2LP Implementing an 8-Bit Asynchronous Interface Application Note Abstract This application note discusses how to configure the General Programmable Interface (GPIF) and slave FIFOs of the EZ-USB FX2LP™ to implement an 8-bit asynchronous interface. The GPIF is a prog ramma ble 8 or 1 6-bi[...]

  • Page 2

    February 19, 2008 Document No. 001-15342 Rev . ** 2 AN6077 GPIF Master Pin Descriptions The GPIF pin names, descriptions, an d their uses are dis- cussed in this section. RDYn Input s RDY[5:0] are ‘ready’ inputs that can be sampled and allow a transaction to wait (inserting wa it states), continue, or repeat until the signal is at the appr opri[...]

  • Page 3

    February 19, 2008 Document No. 001-15342 Rev . ** 3 AN6077 Figure 2 shows the GPIF De signer view of the FIFO Read waveform. FIFOWR When creating the F IFOWR waveform the following timin g parameters must be met. tWR pwl - SL WR Pulse Wid th LO W = 50 ns (minimum) tWR pwh - SL WR Pulse Width HIGH = 50 ns (minimum) tSFD - SL WR to FIFO DA T A Setup [...]

  • Page 4

    February 19, 2008 Document No. 001-15342 Rev . ** 4 AN6077 Figure 4. FIFO Read Waveform in gpif.c Figure 5. FIFO Write W avefo rm in gpif.c 8051 Firmware Programming (Master) This section describes how to config ure the 8051 to support the interface on the master side (registe r se ttings and others) and discusses the firmware implemented to perfor[...]

  • Page 5

    February 19, 2008 Document No. 001-15342 Rev . ** 5 AN6077 The firmware uses the AUTO mode for both IN and OUT transfers. Th is means that the maximum size (512 bytes) packets are committed automat ical ly from the pe ripheral domain to the USB domai n for OUT transfers. For IN trans- fers, they are committed from USB to the peripheral doma in. The[...]

  • Page 6

    February 19, 2008 Document No. 001-15342 Rev . ** 6 AN6077 IOA = 0x80; xFIFOTC_OUT = ( ( EP2FIFOBCH << 8 ) + EP2FIFOBCL ); // setup GPIF transaction count SYNCDELAY; EP2GPIFTCH = EP2FIFOBCH; SYNCDELAY; EP2GPIFTCL = EP2FIFOBCL; // trigger FIFO write transaction(s) SYNCDELAY; GPIFTRIG = GPIFTRIGWR | GP IF_EP2; // once master (GPIF) drains OUT p[...]

  • Page 7

    February 19, 2008 Document No. 001-15342 Rev . ** 7 AN6077 if( EP68FIFOFLGS & 0x01 ) { // EP6FF=1, when fifo "full" } else { // EP6FF=0, when fifo "not full", fo r example, buffer available // setup GPIF transaction count SYNCDELAY; EP6GPIFTCH = 0x02; SYNCDELAY; EP6GPIFTCL = 0x00; // trigger FIFO read transaction(s), using S[...]

  • Page 8

    February 19, 2008 Document No. 001-15342 Rev . ** 8 AN6077 Code Listing for Master Side #pragma NOIV // D o not generate interrupt vectors #include "fx2.h" #include "fx2regs.h" #include "fx2sdly.h" // S YNCDELAY macro extern BOOL GotSUD; // R eceived setup data flag extern BOOL Sleep; extern BOOL Rwuen; extern BOOL Sel[...]

  • Page 9

    February 19, 2008 Document No. 001-15342 Rev . ** 9 AN6077 // EP4 and EP8 are not used in thi s implementation SYNCDELAY; // EP4CFG = 0x20; // c lear valid bit SYNCDELAY; // EP8CFG = 0x60; // c lear valid bit SYNCDELAY; // FIFORESET = 0x80; // a ctivate NAK-ALL to avoid race co nditions SYNCDELAY; // FIFORESET = 0x82; // r eset, FIFO 2 SYNCDELAY; /[...]

  • Page 10

    February 19, 2008 Document No. 001-15342 Rev . ** 10 AN6077 } #define GPIFTRIGWR 0 #define GPIFTRIGRD 4 #define GPIF_EP2 0 #define GPIF_EP4 1 #define GPIF_EP6 2 #define GPIF_EP8 3 void TD_Poll( void ) { // Called repeatedly while the dev ice is idle static WORD xFIFOTC_OUT = 0x0000; static WORD xFIFOTC_IN = 0x0000; // Registers which require a sync[...]

  • Page 11

    February 19, 2008 Document No. 001-15342 Rev . ** 1 1 AN6077 // setup GPIF transaction count SYNCDELAY; EP2GPIFTCH = EP2FIFOBCH; SYNCDELAY; EP2GPIFTCL = EP2FIFOBCL; // trigger FIFO write tran saction(s), using SFR SYNCDELAY; GPIFTRIG = GPIFTRIGWR | GP IF_EP2; // once master (GPIF) drai ns OUT packet, it (re)arms to us b domain // this path is alway[...]

  • Page 12

    February 19, 2008 Document No. 001-15342 Rev . ** 12 AN6077 // RDY0=1, when peripheral i s "not empty" // drive FIFOADDR lines OEA = 0xC0; IOA = 0x00; if( EP68FIFOFLGS & 0x01 ) { // EP6FF=1, when fifo "ful l" } else { // EP6FF=0, when fifo "not full", for example, buffer avai lable // setup GPIF transaction count S[...]

  • Page 13

    February 19, 2008 Document No. 001-15342 Rev . ** 13 AN6077 } BOOL TD_Suspend( void ) { // Called before the device goes i nto suspend mode return( TRUE ); } BOOL TD_Resume( void ) { // Called after the device resumes return( TRUE ); } //---------------------------------- -------------------------------- ----------- // Device Request hooks // The f[...]

  • Page 14

    February 19, 2008 Document No. 001-15342 Rev . ** 14 AN6077 { // Called when a Set Interface com mand is received EP0BUF[ 0 ] = AlternateSetting; EP0BCH = 0; EP0BCL = 1; return( TRUE ); // Handled by user code } BOOL DR_GetStatus( void ) { return( TRUE ); } BOOL DR_ClearFeature( void ) { return( TRUE ); } BOOL DR_SetFeature( void ) { return( TRUE )[...]

  • Page 15

    February 19, 2008 Document No. 001-15342 Rev . ** 15 AN6077 EZUSB_IRQ_CLEAR( ); USBIRQ = bmURES; // Clear U RES IRQ } void ISR_Susp( void ) interrupt 0 { Sleep = TRUE; EZUSB_IRQ_CLEAR( ); USBIRQ = bmSUSP; } void ISR_Highspeed( void ) interrupt 0 { if ( EZUSB_HIGHSPEED( ) ) { pConfigDscr = pHighSpeedConfig Dscr; pOtherConfigDscr = pFullSpeedC onfigD[...]

  • Page 16

    February 19, 2008 Document No. 001-15342 Rev . ** 16 AN6077 } void ISR_Ep1pingnak( void ) interrup t 0 { } void ISR_Ep2pingnak( void ) interrup t 0 { } void ISR_Ep4pingnak( void ) interrup t 0 { } void ISR_Ep6pingnak( void ) interrup t 0 { } void ISR_Ep8pingnak( void ) interrup t 0 { } void ISR_Errorlimit( void ) interrup t 0 { } void ISR_Ep2piderr[...]

  • Page 17

    February 19, 2008 Document No. 001-15342 Rev . ** 17 AN6077 } void ISR_Ep8fflag( void ) interrupt 0 { } void ISR_GpifComplete( void ) interr upt 0 { } void ISR_GpifWaveform( void ) interr upt 0 { // FIFORd WF detected peripheral prematurely empty (less than max . pkt. size) GPIFABORT = 0xFF; // a bort to handle shortpkt INPKTEND = 0x06; SYNCDELAY; [...]

  • Page 18

    February 19, 2008 Document No. 001-15342 Rev . ** 18 AN6077 // PINFLAGSxx EPxFIFOIRQ // EPxFIFOIE GPIFIRQ // GPIFIE GPIFADRH:L // UDMACRCH:L EPxGPIFTRIG // GPIFTRIG SYNCDELAY; FIFORESET = 0x80; // a ctivate NAK-ALL to avoid race co nditions SYNCDELAY; // s ee TRM section 15.14 FIFORESET = 0x82; // r eset, FIFO 2 SYNCDELAY; // FIFORESET = 0x84; // r[...]

  • Page 19

    February 19, 2008 Document No. 001-15342 Rev . ** 19 AN6077 EP2FIFOCFG = 0x10; // A UTOOUT=1, WORDWIDE=0 SYNCDELAY; EP6FIFOCFG = 0x0C; // A UTOIN=1, ZEROLENIN=1, WORDWIDE=0 SYNCDELAY; } void TD_Poll( void ) { // Called repeatedly while the dev ice is idle // nothing to do;slave fifo's are in AUTO mode } BOOL TD_Suspend( void ) { // Called befo[...]

  • Page 20

    February 19, 2008 Document No. 001-15342 Rev . ** 20 AN6077 EP0BUF[ 0 ] = Configuration; EP0BCH = 0; EP0BCL = 1; return(TRUE); // Handled by user code } BOOL DR_SetInterface( void ) { // Called when a Set Interface com mand is received AlternateSetting = SETUPDAT[ 2 ]; return( TRUE ); // Handled by user code } BOOL DR_GetInterface( void ) { // Call[...]

  • Page 21

    February 19, 2008 Document No. 001-15342 Rev . ** 21 AN6077 USBIRQ = bmSOF; // Clear S OF IRQ } void ISR_Ures( void ) interrupt 0 { if ( EZUSB_HIGHSPEED( ) ) { pConfigDscr = pHighSpeedConfig Dscr; pOtherConfigDscr = pFullSpeedC onfigDscr; } else { pConfigDscr = pFullSpeedConfig Dscr; pOtherConfigDscr = pHighSpeedC onfigDscr; } EZUSB_IRQ_CLEAR( ); U[...]

  • Page 22

    February 19, 2008 Document No. 001-15342 Rev . ** 22 AN6077 } void ISR_Ep4inout( void ) interrupt 0 { } void ISR_Ep6inout( void ) interrupt 0 { } void ISR_Ep8inout( void ) interrupt 0 { } void ISR_Ibn( void ) interrupt 0 { } void ISR_Ep0pingnak( void ) interrup t 0 { } void ISR_Ep1pingnak( void ) interrup t 0 { } void ISR_Ep2pingnak( void ) interru[...]

  • Page 23

    AN6077 Cypress Semico nd uctor 198 Champi on Cou rt San Jose, CA 9513 4-1709 Phone: 408- 943-2600 Fax: 408-94 3-4730 http://www.cypr ess.com © Cypress S emiconducto r Corpora tion, 200 6-2008. The informati on contained herein is subject to chang e without notice. Cy press Semiconducto r Corporation a ssumes no resp onsibility for t he use of an y[...]