Texas Instruments TMS320DM36x инструкция обслуживания

TMS320DM36x DMSoC Analog to Digital Converter (ADC) Interface User's Guide Literature Number: SPRUFI7 March 2009[...]

2 SPRUFI7 – March 2009 Submit Documentation Feedback[...]

Contents Preface ........................................................................................................................................ 5 1 Features .............................................................................................................................. 8 1.1 Block Diagram ....................................[...]

www.ti.com List of Figures 1 ADC IF Block Diagram ...................................................................................................... 8 2 ADC Control (ADCTL) Register .......................................................................................... 12 3 Comparator Target Channel (CMPTGT) Register ........................[...]

Preface SPRUFI7 – March 2009 Read This First About This Manual This document describes the analog-to-digital converter (ADC) interface peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the follow[...]

Related Documentation From Texas Instruments www.ti.com SPRUFH2 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Asynchronous Receiver/Transmitter (UART) Users Guide This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The UART peripheral per[...]

www.ti.com Related Documentation From Texas Instruments SPRUFI2 — TMS320DM36x Digital Media System-on-Chip (DMSoC) DDR2/Mobile DDR (DDR2/mDDR) Memory Controller Users Guide This document describes the DDR2/mDDR memory controller in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The DDR2/mDDR memory controller is used to interface with JESD[...]

1 Features 1.1 Block Diagram 32-bitPeripheralbus ADC T imingandchannel controller Comparator CMPUDA T A InterrupttoCPU CMPTGT CMPLDA T A Interrupt controller 10-bit Analog-to-digital converter 6to1 Analoginput selector ADC_CH0 ADC_CH1 ADC_CH2 ADC_CH3 ADC_CH4 ADC_CH5 ADCTL AD1DA T AD2DA T AD4DA T AD3DA T AD5DA T AD0DA T SE[...]

1.2 Industry Compliance Statement 2 Peripheral Architecture 2.1 Clock Control 2.2 Signal Descriptions 2.3 Functional Operation 2.3.1 One-Shot Mode Operation www.ti.com Peripheral Architecture The ADC interface does not conform to any recognized industry standards. The ADC interface is driven by the auxiliary clock of the PLL controller. The frequen[...]

2.3.2 Free-Run Mode Operation 2.4 Reset Considerations 2.4.1 Software Reset Considerations 2.4.2 Hardware Reset Considerations 2.5 Interrupt Support 2.5.1 Interrupt Events and Requests 2.5.2 Interrupt Multiplexing Peripheral Architecture www.ti.com In free-run mode operation, the ADC interface performs A/D conversion continuously without stopping. [...]

2.6 EDMA Event Support 2.7 Power Management 2.8 Emulation Considerations 3 Registers www.ti.com Registers The ADC interface module does not generate an EDMA event. The ADC interface can be placed in reduced-power modes to conserve power during periods of low activity. Power management of the ADC Interface is controlled by the power and sleep contro[...]

3.1 ADCTL Registers www.ti.com The ADC control register (ADCTL) is shown in Figure 2 and described in Table 2 . Figure 2. ADC Control (ADCTL) Register 31 24 Reserved R-0 23 16 Reserved R-0 15 8 Reserved R-0 76543210 BUSY CMPFLG CMPIEN CMPMD SCNFLG SCNIEN SCNMD START R-0 R/C-0 R/W-0 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read on[...]

3.2 CMPTGT 3.3 CMPLDAT www.ti.com Registers The comparator target channel (CMPTGT) register is shown in Figure 3 and described in Table 3 . Figure 3. Comparator Target Channel (CMPTGT) Register 31 6 5 0 Reserved CMPTGT R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 3. Comparator Target Channel (CMPTGT) Field Descri[...]

3.4 CMPUDAT 3.5 SETDIV 3.6 CHSEL Registers www.ti.com The comparison A/D Upper data (CMPUDAT) register is shown in Figure 5 and described in Table 5 . Figure 5. Comparison A/D Upper Data (CMPUDAT) Register 31 10 9 0 Reserved CMPUDAT R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 5. Comparison A/D Upper Data (CMPUDA[...]

3.7 AD0DAT 3.8 AD1DAT www.ti.com Registers Table 7. CHSEL setting for Channel selection CHSEL Selected Channel 000001b Channel 0 000010b Channel 1 000100b Channel 2 001000b Channel 3 010000b Channel 4 100000b Channel 5 Figure 7. Analog Input Channel Select (CHSEL) Register 31 6 5 0 Reserved CHSEL R-0 R/W-0x3F LEGEND: R/W = Read/Write; R = Read only[...]

3.9 AD2DAT 3.10 AD3DAT 3.11 AD4DAT Registers www.ti.com Table 10. A/D Conversion Data 1 (AD1DAT) Field Descriptions Bit Field Value Description 31-10 Reserved Any writes to these bit(s) must always have a value of 0. 9-0 AD1DAT A/D conversion data for channel 1 The A/D conversion data 2 (AD2DAT) register is shown in Figure 10 and described in Table[...]

3.12 AD5DAT 3.13 EMUCTRL www.ti.com Registers Table 13. A/D Conversion Data 4 (AD4DAT) Field Descriptions Bit Field Value Description 31-10 Reserved Any writes to these bit(s) must always have a value of 0. 9-0 AD4DAT A/D conversion data for channel 4 The A/D conversion data 5 (AD5DAT) register is shown in and described in . Figure 13. A/D Conversi[...]

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