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NEC VR4133 manual

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Table of contents for the manual

  • Page 1

    Customer Notification V R 4133 TM 64-bit Microprocessor Operating Precautions µPD30133F3-266-GA3-A Document No. TPS-HE-B-6009-4 Date Published: June 2004  NEC Electronics (Europe) GmbH[...]

  • Page 2

    DISCLA IMER The related documents in this cu stomer notification may include pr eliminary versions. How ever, preliminary versions may not have been marked as such. The information in this customer notification is curr ent as of its date of public ation. The information is subject to change without notice. For actual design-in, refer to the late st[...]

  • Page 3

    Table of Contents (A) Table of Oper ating Pr ecautions ............................................................................................. 4 (B) Description of Op erating Pr ecautions ................................................................................... 5 (C) Valid Sp ecificat ion ............................................[...]

  • Page 4

    Operating Precautions for V R 4133 TM (A) Table of Operating Precautions µPD30133 Rev. 1.1 1.2 1.3 1.4 1.5 No. Outline Rank Note I,K E P X L 1 Simultaneous locking of cache lines with the same index      2 Reception of non IEEE802.3 conformant packages      3 Register content in Ether0/1 blocks      4 R[...]

  • Page 5

    Operating Precautions for V R 4133 TM (B) Description of Operating Precautions No. 1 Simultaneous locking of cache lines with the same index (Specification change notice) Details Simultaneous locking of two cache lines with t he same index (i.e. in both cache ways) is prohibited. No. 2 Reception of non IEEE802.3 conformant packages (Specification c[...]

  • Page 6

    Operating Precautions for V R 4133 TM No. 5 Write access to external I/O area (Direction of usage) Details A write cycle to external I/O or Flash area after • a CPU read/write access to a BCU-managed registers Note • or a CPU I/O read after a bus hold • or a DMA I/O read after a bus hold • or a Flash memory read may drive the wrong write da[...]

  • Page 7

    Operating Precautions for V R 4133 TM No. 7 Disconnect at the end of PCI burst cycle (Specification change notice) Details The last transfer of a PCI burst cycle is regarded as a disconnect cycle by VR4133, if STOP# and TRDY# are both asserted during the last-but-one dat a cycle, as shown in the following figure: D0 ,D1,D2 are burst data; D3 is las[...]

  • Page 8

    Operating Precautions for V R 4133 TM No. 9 Ethernet: excessive data transfer into memory (Direction of usage) Details If two or more packets are received continuously , excessive data may be written at the end of a packet. The length of excessive data depends on the value of the DRBS0/1 bits of register RCV_CFGR0/1 (0x0f00 1618 / 0x0f00 1918) and [...]

  • Page 9

    Operating Precautions for V R 4133 TM No. 11 Usage PCI and Ether/CEU/BCU/CSI (using DMA mode) simultaneously (Direction of usage) Details Using PCI and Ether / CEU / BCU / CSI (u sing DMA mode) simultaneously may occur a hang- up, if following 3 conditions are all satisfied: (1) CPU reads PCI bus or PCIU register (0x0f000cxx / 0x0f000dxx). (2) Exte[...]

  • Page 10

    Operating Precautions for V R 4133 TM (C) Valid Specification Item Date published Document No. Document Title 1 April 2004 U16551EJ2V0DS00 V R 4133 Preliminary Data Sheet 2 February 2004 U16620EJ3V0UM00 V R 4133 User Manual 10 Customer Notification[...]

  • Page 11

    Operating Precautions for V R 4133 TM Customer Notification 11 (D) Revision History Item Date published Document No. Comment 1 October 2003 TPS-HE-B-6009-1 1 st release 2 January 2004 TPS-HE-B-6009-2 Added item 8 to 12 3 May 2004 TPS-HE-B-6009-3 Modified item 10 4 June 2004 TPS-HE-B-6009-4 Added item 13 and 14[...]