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Cypress CY7C1356C manual

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Table of contents for the manual

  • Page 1

    9-Mbit (256K x 36/512K x 18) Pi p elined SRAM with NoBL™ Architecture CY7C1354C CY7C1356C Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05538 Rev . *G Revised September 14, 2006 Features • Pin-comp atible an d functionally eq uiv a le nt to ZBT ™ • Supports 250-MHz [...]

  • Page 2

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 2 of 28 A0, A1, A C MODE BW a BW b WE CE1 CE2 CE3 OE READ LOGIC DQs DQP a DQP b D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BURST LOGIC A0[...]

  • Page 3

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 3 of 28 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQa DQa V DDQ V SS DQa DQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQd DQd DQd V SS V DDQ A A CE 1 CE 2 BWa CE 3 V DD V SS CLK WE CEN OE NC(1[...]

  • Page 4

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 4 of 28 Pin Configurations (continued) 234 5 6 7 1 A B C D E F G H J K L M N P R T U DQ a V DDQ NC/576 M NC/1G DQ c DQ d DQ c DQ d AA A A NC/18M V DDQ CE 2 A V DDQ V DDQ V DDQ V DDQ NC/144 M NC A DQ c DQ c DQ d DQ d TMS V DD A NC/72M DQP d A A ADV/LD AC E 3 NC V DD AA N C V SS V SS NC DQP b DQ [...]

  • Page 5

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 5 of 28 Pin Configurations (continued) 23 4 567 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d NC/36M NC/72M V DDQ BW d BW a CLK WE V SS V SS V SS V SS V DDQ V SS V DD V SS V SS V SS NC V[...]

  • Page 6

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 6 of 28 Pin Definitions Pin Name I/O T ype Pin Description A0, A1 A Input- Synchronous Address Inp ut s used to select on e of the addre ss locations . Sampled at the rising edge of the CLK. BW a ,BW b , BW c ,BW d , Input- Synchronous Byte Write Select Inpu t s, active LOW . Qualified with WE [...]

  • Page 7

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 7 of 28 Functional Overview The CY7C1354C and C Y7C1356C are synchronous-pipeli ned Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transi tions. All synchronous input s pass through input registers co ntrolled by the rising ed ge of the clock. The clock signal[...]

  • Page 8

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 8 of 28 Because the CY7C1354C and CY7C1356C are common I/O devices, data should not be driv en into the device while the outputs are active. The Output Enable (OE ) can be deasserted HIGH before presenting data to the DQ and DQP (DQ a,b,c, d /DQP a,b,c,d for C Y7C1354C and DQ a,b /D QP a,b for [...]

  • Page 9

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 9 of 28 NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-S tate WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-S tate IGNORE CLOCK EDGE (S t all) Current X L X X X X H L-H - SLEEP MODE None X H X X X X X X T ri-S tate Partial Write Cycle Description [2, 3, 4, 9] Function (CY7C1[...]

  • Page 10

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 10 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1354C/CY7C1356C incorpora tes a serial boundary scan test access port (T AP) in th e BGA package only . The TQFP package does not offer this functionality . This part operates in accordance with IEEE S t andard 1 149.1-1900, but doesn?[...]

  • Page 11

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 1 1 of 28 TDI and TDO ba lls as show n in the T ap Co ntroller Bl ock Diagram. Upon power-up, the instruction register is loaded with the IDCODE in struction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in th e pre v i o us section. Wh[...]

  • Page 12

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 12 of 28 PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection o f another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is[...]

  • Page 13

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 13 of 28 3.3V T AP AC T est Conditions Input pulse levels .................. .............. .............. .. V SS to 3.3V Input rise and fall times ......... ........ ........... ... ........... ... ...... 1 ns Input timing referenc e levels .................... ........... ............1.5V Ou[...]

  • Page 14

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 14 of 28 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (1 19-b all BGA package) 69 69 Boundary Scan Order (165-ball FBGA package) 69 69 Identification Codes Instruct ion Code Descri ption EXTEST 000 Captures the Input/Out[...]

  • Page 15

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 15 of 28 Boundary Scan Exit Order (256K × 36) Bit # 1 19-ball ID 165-ball ID 1K 4 B 6 2H 4 B 7 3M 4 A 7 4F 4 B 8 5B 4 A 8 6G 4 A 9 7C 3 B 1 0 8B 3 A 1 0 9D 6 C 1 1 10 H7 E10 11 G 6 F 1 0 12 E6 G10 13 D7 D10 14 E7 D1 1 15 F6 E1 1 16 G7 F1 1 17 H6 G1 1 18 T7 H1 1 19 K7 J10 20 L6 K10 21 N6 L10 22[...]

  • Page 16

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 16 of 28 Boundary Scan Exit Order (512K × 18) Bit # 1 1 9-ball ID 165-ball ID 1K 4 B 6 2H 4 B 7 3M 4 A 7 4F 4 B 8 5B 4 A 8 6G 4 A 9 7C 3 B 1 0 8B 3 A 1 0 9T 2 A 1 1 10 Not Bonded (Preset to 0) Not Bonded (Preset to 0) 1 1 Not Bonded (Preset to 0) Not Bonded (Preset to 0) 12 Not Bonded (Preset [...]

  • Page 17

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 17 of 28 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied ........... ............................ ...... –55°C to +125°C Su[...]

  • Page 18

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 18 of 28 Cap acit ance [16] Parameter Des criptio n T est Conditions 100 TQ FP Max. 1 19 BGA Max. 165 FBGA Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 55 5 p F C CLK Clock Input Capacitance 5 5 5 pF C I/O Input/Output Capacit ance 5 7 7 pF Thermal Resist [...]

  • Page 19

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 19 of 28 Switching Characteristics Over the Operating Range [18, 19] Parameter Description –250 –200 –166 Unit Min. Max. Min. Max. Min. Max. t Power [17] V CC (typical) to the First Access Read or Write 1 1 1 ms Clock t CYC Clock Cycle T ime 4.0 5 6 ns F MAX Maximum Operating Frequency 25[...]

  • Page 20

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 20 of 28 Switching W aveforms Read/Write T iming [23, 24, 25] Notes: 23. For this waveform ZZ is tied low . 24. When CE is LOW, CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW . When CE is H IGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 25. Order of the Burst sequence is determined by the st atu[...]

  • Page 21

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 21 of 28 NOP ,ST ALL and DESELECT Cycles [23, 24, 26] Note: 26. The IGNORE CLOCK EDGE or ST ALL cycle (Clock 3) illustrated CEN being used to create a pause. A wr ite is not perform ed during this cycle. Switching W aveforms (continued) READ Q(A3) 456789 1 0 CLK CE WE CEN BW X ADV/LD ADDRESS A3[...]

  • Page 22

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 22 of 28 27. Device must be deselected when entering ZZ mode. See cycle descr ipt ion table for all possible signal co nditions to deselect the device. 28. I/Os are in High-Z when exiting ZZ sleep mode. ZZ Mode Timing [27, 28] Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL I[...]

  • Page 23

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 23 of 28 Ordering Information Not all of the spe ed, package and temperature ran ges are available. Please contact your local sales r epresentative or visit www .cypress.com for actual pro duct s offered. Speed (MHz) Ordering Code Package Diagram Part and Packa ge T ype Operating Range 166 CY7C[...]

  • Page 24

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 24 of 28 250 CY7C1354C-250AXC 51-8 5050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1356C-250AXC CY7C1354C-250BGC 51-851 15 1 19-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1356C-250BGC CY7C1354C-250BGXC 51-851 15 1 19-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Fre[...]

  • Page 25

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 25 of 28 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMAT[...]

  • Page 26

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 26 of 28 Package Diagrams (continued) 1.27 20.32 2 16 5 4 37 L E A B D C H G F K J U P N M T R 12.00 19.50 30° TYP. 2.40 MAX. A1 CORNER 0.70 REF. U T R P N M L K J H G F E D C A B 21 43 65 7 Ø1.00(3X) REF. 7.62 22.00±0.20 14.00±0.20 1.27 0.60±0.10 C 0.15 C B A 0.15(4X) Ø0.05 M C Ø0.75±0[...]

  • Page 27

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 27 of 28 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod u[...]

  • Page 28

    CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 28 of 28 Document History Page Document Title: CY7C1354C/CY7C1356C 9-Mbit (256K x 36/5 12K x 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05538 REV . ECN No. Issue Date Orig. of Change Description of Cha ng e ** 242032 See ECN RKF New dat a sheet *A 278130 Se e ECN RKF Chang[...]