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Cypress CY7C1019CV33 manual

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Table of contents for the manual

  • Page 1

    128K x 8 S t atic RAM CY7C1019CV33 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05130 Rev . *F Revised August 3, 2006 Features • Pin and function compatible with CY7C1019BV33 •H i g h s p e e d —t AA = 10 ns • CMOS for optimum speed/po we r • Dat a retention at 2[...]

  • Page 2

    CY7C1019CV33 Document #: 38-05130 Rev . *F Page 2 of 10 Pin Configuration [1] Selection Guide -10 -12 -15 Unit Maximum Access T ime 10 12 15 ns Maximum Operat ing Current 80 75 70 mA Maximum S tandby Cu rrent 5 5 5 mA Note: 1. NC pins are not connected on the die. WE V CC A 9 A 16 NC A 4 A 2 A 1 CE NC I/O 0 I/O 1 A 5 A 0 NC NC NC I/O 2 I/O 3 V SS A[...]

  • Page 3

    CY7C1019CV33 Document #: 38-05130 Rev . *F Page 3 of 10 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T e mperature with Power Applied ........... ............................ ...... –55°C to +125°C Supply V [...]

  • Page 4

    CY7C1019CV33 Document #: 38-05130 Rev . *F Page 4 of 10 AC T est Loads and W aveforms [4] Switching Characteristics Over the Operating Range [5] Parameter Description -10 -12 -15 Unit Min. Max. Min. Max. Min. Max. Read Cycle t RC Read Cycle T ime 10 12 15 ns t AA Address to Data V alid 10 12 15 ns t OHA Data Hold from Address Change 3 3 3 ns t ACE [...]

  • Page 5

    CY7C1019CV33 Document #: 38-05130 Rev . *F Page 5 of 10 Switching W aveforms Read Cycle No. 1 [1 1, 12] Read Cycle No. 2 (OE Controlled) [12, 13] Write Cycle No. 1 (CE Controlled) [14, 15] Notes: 1 1. Device is continuously selected. OE , CE = V IL . 12. WE is HIGH for read cycle. 13. Address valid pr ior to or coi ncident with CE t ransition LOW .[...]

  • Page 6

    CY7C1019CV33 Document #: 38-05130 Rev . *F Page 6 of 10 Write Cycle No. 2 (WE Controlled, OE HI GH During Write) [14, 15] Write Cycle No. 3 (WE Controlled, OE LOW) [15] Switching W aveforms (continued) t HD t SD t PWE t SA t HA t AW t SCE t WC t HZOE DATA IN VALID CE ADDRESS WE DATA I/O OE NOTE 16 DATA VALID t HD t SD t LZWE t PWE t SA t HA t AW t [...]

  • Page 7

    CY7C1019CV33 Document #: 38-05130 Rev . *F Page 7 of 10 Ordering Information Speed (ns) Ordering Code Package Diagram Package T ype Operating Range 10 CY7C1019CV33-10VC 51-85033 32-p in 400-Mil Molded SOJ Commercial CY7C1019CV33-10ZXC 51-85095 32-p in TSOP II (Pb-Free) CY7C1019CV33-10ZXI 32-pin TSOP II (Pb-Free) Industrial 12 CY7C1019CV33-12VC 51-8[...]

  • Page 8

    CY7C1019CV33 Document #: 38-05130 Rev . *F Page 8 of 10 Package Diagrams (continued) 51-85095 -** 32-pin TSOP II (51-85095) [+] Feedback[...]

  • Page 9

    CY7C1019CV33 Document #: 38-05130 Rev . *F Page 9 of 10 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wit hout notice. C ypr ess S em ic on duct or Corporation assumes no resp onsib ility for the u se of any circuitry o ther than circui try embodied in a Cypress prod uct. Nor does[...]

  • Page 10

    CY7C1019CV33 Document #: 38-05130 Rev . *F Page 10 of 10 Document History Page Document Title: CY7C1019CV33 128K x 8 St atic RAM Document Number: 38 -05130 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 109245 12/16/01 HGK New Data Sheet *A 1 13431 04/10/02 NSL AC T est Loads split based on spee d *B 1 15047 08/01/02 HGK Added TS[...]