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Cypress CY7C1353G manual

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Table of contents for the manual

  • Page 1

    4-Mbit (256K x 18) Flow-through SRAM wi t h N o BL™ Ar c hi tectu r e CY7C1353G Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05515 Rev . *E Revised July 09, 2007 Features • Supports up to 133-MHz bu s operations with zero wait states — Data is transferred on every cl[...]

  • Page 2

    CY7C1353G Document #: 38-05515 Rev . *E Page 2 of 13 Selection Guide 133 MHz 100 MHz Unit Maximum Access T ime 6.5 8.0 ns Maximum Operating Curren t 225 205 mA Maximum CMOS S tandby Cu rrent 40 40 mA Pin Configuration 100-Pin TQFP Pinout A A A A A1 A0 NC/288M NC/144M V SS V DD NC/36M A A A A A A A NC NC V DDQ V SS NC DQP A DQ A DQ A V SS V DDQ DQ A[...]

  • Page 3

    CY7C1353G Document #: 38-05515 Rev . *E Page 3 of 13 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the 25 6K address locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter . BW [A:B] Input- Synchronous Byte Write In put s, Active LOW . Qualified wit[...]

  • Page 4

    CY7C1353G Document #: 38-05515 Rev . *E Page 4 of 13 Functional Overview The CY7C1353G is a synchronous flow-thro ugh burst SRAM designed specifically to el iminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with th e Clock [...]

  • Page 5

    CY7C1353G Document #: 38-05515 Rev . *E Page 5 of 13 Linear Burst Address T a ble (MODE = GND) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 1 1 01 10 1 1 00 10 1 1 00 01 1 1 0 0 01 10 Interleaved Burst Address T able (MODE = Floating or V DD ) First Address A1, A0 Second Address A1, A0 Third Address[...]

  • Page 6

    CY7C1353G Document #: 38-05515 Rev . *E Page 6 of 13 Partial T ruth T able for Read/W rite [2, 3, 9] Function WE BW A BW B Read HX X Write – No bytes written L H H Write Byte A – (DQ A and DQP A )L L H Write Byte B – (DQ B and DQP B )L H L Write All Bytes L L L Note: 9. T able only lists a partial listing of the byte writ e combinatio ns. Any[...]

  • Page 7

    CY7C1353G Document #: 38-05515 Rev . *E Page 7 of 13 Maximum Ratings Exceeding maximum rati ngs may impair the useful life of the device. These user guid elines are not tested. S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emp erature with Power Applied ........... ............................ ...... –55?[...]

  • Page 8

    CY7C1353G Document #: 38-05515 Rev . *E Page 8 of 13 . Cap acit ance [12] Parameter Descr iption T est Co nditions 100 TQFP Max Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V V DDQ =3.3V 5p F C CLOCK Clock Input Ca pacitance 5 pF C IO IO Capacitance 5 pF Thermal Resist ance [12] Parameters Description T est Conditions 100 TQFP Pack[...]

  • Page 9

    CY7C1353G Document #: 38-05515 Rev . *E Page 9 of 13 Switching Characteristics Over the Operating Range [17, 18] Parameter Description –133 –100 Unit Min Max Min Max t POWER V DD (T ypical) to the first Access [13] 11 m s Clock t CYC Clock Cycle T ime 7.5 10 ns t CH Clock HIGH 2.5 4.0 ns t CL Clock LOW 2.5 4.0 ns Output Times t CDV Data Output [...]

  • Page 10

    CY7C1353G Document #: 38-05515 Rev . *E Page 10 of 13 Switching W aveforms Read/Write W avefo rms [19, 20, 21] Notes: 19. For this waveform ZZ is tied low . 20.When CE is LOW , CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW . When CE is HIGH , CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 21.Order of the Burst se quence is determined by the st atus of t[...]

  • Page 11

    CY7C1353G Document #: 38-05515 Rev . *E Page 1 1 of 13 NOP , ST ALL and DESELECT Cycles [1 9, 20, 22] ZZ Mode Timing [23,24] Notes: 22.The IGNORE CLOCK EDGE or ST ALL cycle (Clock 3) illustrates CEN being used to create a pau se. A write is not performed durin g this cycle. 23.Device must be deselected when ente ring ZZ mode. See truth ta ble for a[...]

  • Page 12

    CY7C1353G Document #: 38-05515 Rev . *E Page 12 of 13 © Cypress Semicon ductor Corporat ion, 2004- 2007. The informat ion contai ned herein is sub ject to change withou t notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry othe r than circuitr y embodied in a Cypress prod uct. Nor does it convey or impl[...]

  • Page 13

    CY7C1353G Document #: 38-05515 Rev . *E Page 13 of 13 Document History Page Document Title: CY7C1353G 4-Mbit (256K x 18) Flow-throug h SRAM with NoBL™ Architecture Document Number: 38-05515 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 224363 See ECN RKF New data sheet *A 288431 See ECN VBL Deleted 66 MHz Changed TQFP package [...]