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Cypress CY7C1231H manual

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Table of contents for the manual

  • Page 1

    2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ Architecture CY7C1231H Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 001-00207 Rev . *B Revised April 26, 2006 Features • Can support up to 133 -MHz bus operations with zero wait st ates — Data is transferred on every clock[...]

  • Page 2

    CY7C1231H Document #: 001-00207 Rev . *B Page 2 of 12 Selection Guide 133 MHz Unit Maximum Access T i me 6.5 ns Maximum Operating Current 225 mA Maximum CMOS S tandby Current 40 mA Pin Configuration 100-pin TQFP Pinout A A A A A1 A0 NC/288M NC/144M V SS V DD NC(36M) A A A A A NC/4M A NC NC V DDQ V SS NC DQP A DQ A DQ A V SS V DDQ DQ A DQ A V SS NC [...]

  • Page 3

    CY7C1231H Document #: 001-00207 Rev . *B Page 3 of 12 Pin Definitions Name I/O Descrip tion A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of th e 128K address locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter . BW [A:B] Input- Synchronous Byte Write Input s, active LOW . Qualified w[...]

  • Page 4

    CY7C1231H Document #: 001-00207 Rev . *B Page 4 of 12 Functional Overview The CY7C1231H is a synchronous flow-through burst SRAM designed specifically to el iminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with th e Clock [...]

  • Page 5

    CY7C1231H Document #: 001-00207 Rev . *B Page 5 of 12 Linear Burst Address T able (MODE = GND) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 1 1 01 10 1 1 00 10 1 1 00 01 1 1 00 01 10 Interleaved Burst Sequence First Address Second Address Third Address Fourth Address A1, A0 A1, A0 A1, A0 A1, A0 00 0[...]

  • Page 6

    CY7C1231H Document #: 001-00207 Rev . *B Page 6 of 12 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied ........... ............................ ...... –55°C to +125°C Supply V olt[...]

  • Page 7

    CY7C1231H Document #: 001-00207 Rev . *B Page 7 of 12 Cap acit ance [1 1] Parameter Description T est Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25°C , f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 5p F C CLOCK Clock Input Capacitance 5 pF C I/O I/O Capacit ance 5 pF Thermal Resist ance [1 1] Parameters Description T est Conditions 100 TQFP [...]

  • Page 8

    CY7C1231H Document #: 001-00207 Rev . *B Page 8 of 12 Switching Characteristics Over the Operating Range [12, 13] Parameter Description -133 Unit Min. Max. t POWER V DD (T ypical) to the first Access [14] 1 ms Clock t CYC Clock Cycle T ime 7.5 ns t CH Clock HIGH 2.5 ns t CL Clock LOW 2.5 ns Output Times t CDV Data Output V alid after CLK Rise 6.5 n[...]

  • Page 9

    CY7C1231H Document #: 001-00207 Rev . *B Page 9 of 12 Switching W aveforms Read/Write W aveforms [18, 19, 20] Notes: 18. For this waveform ZZ is tied LOW. 19. When CE is LOW , CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 20. Order of the Burst sequence is determined by the stat us of the [...]

  • Page 10

    CY7C1231H Document #: 001-00207 Rev . *B Page 10 of 12 NOP , ST ALL and Des elect Cyc les [1 8, 19, 21] ZZ Mode T iming [22, 23] Notes: 21. The IGNORE CLOCK EDGE or ST ALL cycle (Clock 3) illustrated CEN being used to create a pause. A writ e is not perform ed during this cycle. 22. Device must be deselected when entering ZZ mode. See T ruth T a bl[...]

  • Page 11

    CY7C1231H Document #: 001-00207 Rev . *B Page 1 1 of 12 © Cypress Semi con duct or Cor po rati on , 20 06 . The information contained he re i n is su bj ect to ch ange without notice. Cypress S em ic on duct or Corpo ration assu mes no resp onsib ility for th e u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor does [...]

  • Page 12

    CY7C1231H Document #: 001-00207 Rev . *B Page 12 of 12 Document History Page Document Title: CY7C1231H 2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ Archite ctur e Document Numb er: 001-00207 REV . ECN NO. Issue Date Orig. of Change Description of Cha ng e ** 347377 See ECN PCI New Data Sheet *A 428408 See ECN NXR Converted from Preliminary to [...]