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Cypress CY7C1372DV25 manual

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Table of contents for the manual

  • Page 1

    18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture CY7C1370DV25 CY7C1372DV25 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05558 Rev . *D Revised June 29, 2006 Features • Pin-comp atible and functionally equiv a le nt to ZBT™ • Supports 250-MHz bus o[...]

  • Page 2

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 2 of 27 A0, A1, A C MODE BW a BW b WE CE1 CE2 CE3 OE READ LOGIC DQs DQP a DQP b D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BURST LO[...]

  • Page 3

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 3 of 27 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQa DQa V DDQ V SS DQa DQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQd DQd DQd V SS V DDQ A A CE 1 CE 2 BW a CE 3 V DD V SS CLK WE CEN [...]

  • Page 4

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 4 of 27 Pin Configurations (continued) 234 5 6 7 1 A B C D E F G H J K L M N P R T U DQ a V DDQ NC/576 M NC/1G DQ c DQ d DQ c DQ d AA A A AV DDQ CE 2 A V DDQ V DDQ V DDQ V DDQ NC/144 M NC A DQ c DQ c DQ d DQ d TMS V DD A NC/72M DQP d A A ADV/LD AC E 3 NC V DD AA N C V SS V SS NC DQP b DQ [...]

  • Page 5

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 5 of 27 Pin Configurations (continued) 23 4 567 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d NC/36M NC/72M V DDQ BW d BW a CLK WE V SS V SS V SS V SS V DDQ V SS V DD V SS V SS V S[...]

  • Page 6

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 6 of 27 Pin Definitions Pin Name I/O T ype Pin Description A0 A1 A Input- Synchronous Address Inputs used to select one of the address lo cations . Sampled at the rising edge of the CLK. BW a BW b BW c BW d Input- Synchronous Byte Write Select Inputs, active LOW . Qualified with WE to con[...]

  • Page 7

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 7 of 27 Introduction Functional Overview The CY7C1370DV25 and CY7C1 372DV25 are synchronous-pipel ined Burst NoBL SRAMs designed specifi- cally to eliminate wait states during Write/Read transitions. All synchronous inp uts pass through input registers controlled by the rising edge of the[...]

  • Page 8

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 8 of 27 signals. The CY7C1370DV25 /CY7C1372DV25 provides byte write capability tha t is describ ed in the W rite Cycle Description table. Asserting the Wr ite Enable input (WE ) with the selected Byte Write S elect (BW ) input will selectively write to only the desired bytes. Bytes not se[...]

  • Page 9

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 9 of 27 T ruth T able [1, 2, 3, 4, 5, 6, 7] Operation Address Used CE ZZ ADV/LD WE BW x OE CEN CLK DQ Deselect Cycle None H L L X X X L L-H T ri-state Continue Deselect Cycle None X L H X X X L L-H T ri-state Read Cycle (Begin Burst) Exte rnal L L L H X L L L-H Data Out (Q) Read Cycle (Co[...]

  • Page 10

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 10 of 27 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1370DV25/CY7C1372 DV 25 incorporates a serial boundary scan test access port (T AP).This part is fully compliant with 1 149.1. The T AP operate s using JEDEC-standard 3.3V or 2.5V I/O logi c levels. The CY7C1370DV25/C Y7C1372DV25 [...]

  • Page 11

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 1 1 of 27 TA P R e g i s t e r s Registers are connected betwe en the TDI and TDO balls and allow data to be scanned into and ou t of the SRAM test circuitry . Only one registe r can be selected at a time through the instruction register . Data is serially loaded into the TDI ball on the [...]

  • Page 12

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 12 of 27 BYP ASS When the BYP ASS instruction is lo aded in the instruction register and the T AP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYP ASS instruct ion is that it shortens the boundary scan path when multiple [...]

  • Page 13

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 13 of 27 T AP AC Switching Characteristics Over the Operating Range [9, 10] Parameter Description Min. Max. Unit Clock t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH time 20 ns t TL TCK Clock LOW time 20 ns Output Times t TDOV TCK Clock LOW to TDO V [...]

  • Page 14

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 14 of 27 2.5V T AP AC T est Conditions Input pulse levels ... ............... ........... .............. ..... V SS to 2.5V Input rise and fall time ........... .............. ........... ... ........... ... 1 ns Input timing referenc e levels ............... .............. ............1.[...]

  • Page 15

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 15 of 27 Identification Codes Instruction C ode Descript ion EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register betw een TDI[...]

  • Page 16

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 16 of 27 165-Ball FBGA Boundary Scan Order [12, 14] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1N 6 3 1 D 1 0 6 1G 1 2N 7 3 2 C 1 1 6 2 D 2 3N 1 0 3 3 A 1 1 6 3 E 2 4P 1 1 3 4 B 1 1 6 4 F 2 5P 8 3 5 A 1 0 6 5G 2 6R 8 3 6 B 1 0 6 6 H 1 7R 9 3 7 A 9 6 7 H 3 8P 9 3 8 B 9 6 8 J 1 9P 1 0 3 9 C [...]

  • Page 17

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 17 of 27 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T e mperature with Power Applied ........... ............................ ...... –55 °C to +1[...]

  • Page 18

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 18 of 27 Cap acit ance [17] Parameter Descriptio n T es t Conditio ns 100 TQ FP Package 1 19 BGA Package 165 FBGA Package Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 2.5V . V DDQ = 2.5V 5 8 9 pF C CLK Clock Input Capacitance 5 8 9 pF C I/O Input/Output Capacitance 5 8 9 p[...]

  • Page 19

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 19 of 27 Switching Characteristics Over the Operating Range [22, 23] Parameter Description –250 –200 –167 Unit Min. Max. Min. Max. Min. Max. t Power [18] V CC (typic al) to the first access read or write 1 1 1 ms Clock t CYC Clock Cycle T i me 4.0 5 6 ns F MAX Maximum Operating Freq[...]

  • Page 20

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 20 of 27 Switching W aveforms Read/Write/T iming [24, 2 5, 26] Notes: 24. For this waveform ZZ is tied LOW . 25. When CE is LOW, CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW . When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 26. Order of the Burst sequence is determin ed by the[...]

  • Page 21

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 21 of 27 Notes: 27. The Ignore Clock Edge or S tall cycle (Clock 3) illustrated CEN being used to cr eate a pause. A write is not per formed during this cycle 28. Device must be deselected when entering ZZ mode. See cycle descr iption t able f or all possible signal conditions to deselect[...]

  • Page 22

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 22 of 27 Ordering Information Not all of the spe ed, package and temperature ran ges are availab le. Please contact your local sa les representative or visit www .cypress .com for a ctual produc t s offered. Spe e d (MHz) Ordering Code Package Diagram Part and Packag e T ype Operating Ran[...]

  • Page 23

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 23 of 27 250 CY7C1370DV25-250AXC 51-85050 100 -pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Co mmercial CY7C1372DV25-250AXC CY7C1370DV25-250BGC 51-851 15 1 19-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-250BGC CY7C1370DV25-250BGXC 51-851 15 1 19-ball Ball Grid Array (14 x[...]

  • Page 24

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 24 of 27 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD [...]

  • Page 25

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 25 of 27 Package Diagrams (continued) 51-851 15-*B 1 19-Ball BG A (1 4 x 22 x 2. 4 mm) (51- 85 1 15) [+] Feedback[...]

  • Page 26

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 26 of 27 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress [...]

  • Page 27

    CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev . *D Page 27 of 27 Document History Page Document Title: CY7C1370DV25/CY7C1372DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38 -05558 REV . ECN No. Issue Date Orig. of Change Description of Change ** 254509 See ECN RKF New data sheet *A 288531 See ECN SY[...]