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Cypress CY14B101L manual

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Table of contents for the manual

  • Page 1

    CY14B101L 1 Mbit (128K x 8) nvSRAM Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-06400 Rev . *I Revised January 30, 2009 Features ■ 25 ns, 35 ns, and 45 ns acce ss times ■ Pin compatible with ST K14CA8 ■ Hands off automatic STORE on power down with only a small cap[...]

  • Page 2

    CY14B101L Document Number: 001-06400 Rev . *I Page 2 of 18 Pinout s Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP Pin Definitions Pin Name Alt IO T ype Description A 0 –A 16 Input Address Inp uts. Used to select one of the 131, 072 bytes of the nvSRAM. DQ 0 -DQ 7 Input or Output Bidirect io na l Data IO Line s . Used as input or output line[...]

  • Page 3

    CY14B101L Document Number: 001-06400 Rev . *I Page 3 of 18 Device Operation The CY14B101L nvSRAM is made up of two functional compo - nents paired in the same physical cell. These ar e an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolati[...]

  • Page 4

    CY14B101L Document Number: 001-06400 Rev . *I Page 4 of 18 Hardware RECALL (Power Up) During power up or after any low power conditi on (V CC < V SWITCH ), an internal RECALL request is latched. When V CC once again exceeds the sense voltage of V SWITCH , a RECALL cycle is automatically initiated and takes t HRECALL to complete. Sof tware STOR E[...]

  • Page 5

    CY14B101L Document Number: 001-06400 Rev . *I Page 5 of 18 Preventing Store Disable the AutoS tore function by initiatin g an AutoS tore Disable sequence. A sequence of READ operations is performed in a manner similar to the software STORE initiation. T o initiate the AutoS tore Disable sequence, perform the following sequence of CE controlled READ[...]

  • Page 6

    CY14B101L Document Number: 001-06400 Rev . *I Page 6 of 18 . T able 1. Hardwar e Mode Selectio n CE WE OE A 15 – A 0 Mode IO Power H X X X Not Select ed Output H igh Z S tandby L H L X Read SRAM Output Data Active [3] L L X X Write SRAM Input Data Active LH L 0 x 4 E 3 8 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Read SRAM Read SRAM Read SRAM Read SRAM R[...]

  • Page 7

    CY14B101L Document Number: 001-06400 Rev . *I Page 7 of 18 Maximum Ratin gs Exceeding maximum ratings may shorten the useful life of the device. These user g uidelines are not tested. S torage T emperature ............. ... .. ... ............ –65 ° C to +150 ° C Ambient T emperature with Power Applied ............ ... ....................... .[...]

  • Page 8

    CY14B101L Document Number: 001-06400 Rev . *I Page 8 of 18 Dat a Retention and Endurance Parameter Description Min Unit DA T A R Data Retention at 55 ° C2 0 Y e a r s NV C Nonvolatile STORE Operations 200 K Cap acit ance In the following table, the capacitance parameters are listed. [6] Parameter Description T est Conditio ns Max Unit C IN Input C[...]

  • Page 9

    CY14B101L Document Number: 001-06400 Rev . *I Page 9 of 18 AC Switching Characteristics SRAM Read Cycle Parameter Description 25 ns 35 ns 45 n s Unit Min Max Min Max Min Max Cypress Parameter Alt t ACE t ELQV Chip Enable Access Time 25 35 45 ns t RC [7] t AVAV, t ELEH Read Cycle T ime 25 35 45 ns t AA [8] t AV Q V Address Access T ime 25 35 45 ns t[...]

  • Page 10

    CY14B101L Document Number: 001-06400 Rev . *I Page 10 of 18 SRAM Writ e Cycle Parameter Descriptio n 25 ns 35 ns 45 ns Unit Min Max Min Max Min Max Cypress Parameter Alt t WC t AVAV Write Cycle T ime 25 35 45 ns t PWE t WL WH, t WLEH Write Pulse Width 20 25 30 ns t SCE t EL WH, t ELEH Chip Enable T o End of W rite 20 25 30 ns t SD t DVWH, t DVEH Da[...]

  • Page 11

    CY14B101L Document Number: 001-06400 Rev . *I Page 1 1 of 18 AutoS tore or Power Up RECALL Parameter Alt Description CY14B101L Unit Min Max t HRECALL [13] t RESTORE Power up RECALL Duration 20 ms t STORE [14, 15 ] t HLHZ STORE Cycle Duration 12.5 ms V SWITCH Low V oltage T rigger Level 2.65 V t VCCRISE V CC Rise T ime 150 μ s Switching W aveforms [...]

  • Page 12

    CY14B101L Document Number: 001-06400 Rev . *I Page 12 of 18 Sof tware Controlled STORE/RECALL Cycle The software controlled ST ORE/RECALL cycle follows. [16, 17] Parameter Al t Desc ription 25 ns 35 ns 45 ns Unit Min Max Min Max Min Max t RC [17] t AVAV STORE/RECALL Initiation Cycle T ime 25 35 45 ns t SA t A VEL Address Setup T ime 0 0 0 ns t CW t[...]

  • Page 13

    CY14B101L Document Number: 001-06400 Rev . *I Page 13 of 18 Hardware STORE Cycle Parameter Alt Description CY14B101L Unit Min Max t PHSB t HLHX Hardware STORE Pulse Width 15 ns t DELA Y [18] t HLQZ , t BLQZ T ime Allowed to Complete SRAM Cycle 1 70 μ s t ss [19, 20] Soft Sequence Processing Time 70 us Switching W aveforms Figure 12. Hardware STORE[...]

  • Page 14

    CY14B101L Document Number: 001-06400 Rev . *I Page 14 of 18 Ordering Information Spe e d (ns) Ordering Code Package Diagram Package T ype Operating Range 25 CY14B101L-SZ25XCT 51-8512 7 32-pin SOIC Commercial CY14B101L-SZ25XC 51-85127 32-pin SOIC CY14B101L-SP25XCT 51-85061 48-pi n SSOP CY14B101L-SP25XC 51-85061 48-pi n SSOP CY14B101L-SZ25XIT 51-8512[...]

  • Page 15

    CY14B101L Document Number: 001-06400 Rev . *I Page 15 of 18 45 CY14B101L-SZ45XCT 51-8512 7 32-pin SO IC Commercial CY14B101L-SZ45XC 51-85127 32-pin SOIC CY14B101L-SP45XCT 51-85061 48-pi n SSOP CY14B101L-SP45XC 51-85061 48-pi n SSOP CY14B101L-SZ45XIT 51-85127 32-pin SOIC Industrial CY14B101L-SZ45XI 51-85127 32-pin SOIC CY14B101L-SP45XIT 51-85061 48-[...]

  • Page 16

    CY14B101L Document Number: 001-06400 Rev . *I Page 16 of 18 Figure 15. 48-Pin Shrunk Small Outline Package (51- 8506 1) Package Diagrams (continued) 51-85061-* C [+] Feedback[...]

  • Page 17

    CY14B101L Document Number: 001-06400 Rev . *I Page 17 of 18 Document History Page Document Title: CY14B101L 1 Mbit (128K x 8) nvSRAM Document Number: 00 1-064 00 Rev . ECN No. Submission Date Orig. of Change Description of Chang e ** 425138 TUP New data sheet *A 437321 TUP Show data sheet on External Web *B 471966 TUP Changed I CC3 from 5 mA to 10 [...]

  • Page 18

    Document Number: 001-06400 Rev . *I Revised January 30, 20 09 Pag e 18 of 18 AutoS tore and Qua ntumTr ap are registered tr ademarks of Cypress Se miconductor Corpor ation. All produ cts and comp any names mentio ned in this docum ent may be the trade marks of t heir respe ctive holders. CY14B101L © Cypress Semicondu ctor Corpor ation, 2006-200 9.[...]