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Cypress AutoStore STK17T88 manual

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  • Page 1

    STK17T88 32K x 8 AutoS tore™ nvSRAM with Real T ime Clock Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-52040 Rev . *A Revised March 17, 2009 Features ■ nvSRAM Combined With Integrated Real -Time Clock Functions (RT C , W a tc hdog T i mer , Clock Alarm, Power Monito[...]

  • Page 2

    STK17T88 Document Number: 001-52040 Rev . *A Page 2 of 22 Pin Configurations Figure 1. 48-Pin SS OP V SS A 14 A 12 A 7 A 6 DQ 0 DQ 1 V CC DQ 2 A 3 A 2 A 1 V CAP A 13 A 6 A 9 A 11 A 10 DQ 7 DQ 6 V SS A 0 NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC E X 1 X 2 23 24 A 5 INT [...]

  • Page 3

    STK17T88 Document Number: 001-52040 Rev . *A Page 3 of 22 Absolute Maximum Ratings V oltage on Input Relative to G round .................–0.5V to 4.1V V oltage on Input Relative to V SS ...........–0.5V to (V CC + 0.5V) V oltage on DQ 0-7 or HSB ......................–0.5V to (V CC + 0.5V) T emperature under Bias .............. .............[...]

  • Page 4

    STK17T88 Document Number: 001-52040 Rev . *A Page 4 of 22 AC T est Conditions Input Pulse Levels ....................... .......................... ... 0V to 3V Input Rise and Fall Times ... ........... ........... ........... ........... ....≤ 5ns Input and Output T iming Reference Levels .................... 1.5V Output Load .............. ....[...]

  • Page 5

    STK17T88 Document Number: 001-52040 Rev . *A Page 5 of 22 RTC DC Characteristics Figure 4. RTC Comp onent Configuration Symbol Parameter Commer cial Industrial Unit s Notes Min Max Min Max IBAK R T C Backup Current — 300 — 350 nA From either VRTCcap or VRTCbat VRTCbat RTC Battery Pin V oltage 1.8 3.3 1.8 3.3 V T yp ical = 3.0 V olts during norm[...]

  • Page 6

    STK17T88 Document Number: 001-52040 Rev . *A Page 6 of 22 SRAM READ Cycles #1 and #2 Figure 5. SRAM READ Cycle #1: Address Contro lled [3,4,6] Figure 6. SRAM READ Cycle #2: E and G Controll ed [6] Notes 3. W must be high during SRAM READ cycles. 4. Device is continuously selected with E and G both low 5. Measured ± 200mV from stead y state output [...]

  • Page 7

    STK17T88 Document Number: 001-52040 Rev . *A Page 7 of 22 SRAM WRITE Cycles #1 and #2 Figure 7. SRAM WRITE Cycle #1: W Controlled [7, 8] Figure 8. SRAM WRITE Cycle #2: E Controlled [7, 8] Notes 7. If W is low whe n E goes low , the outputs remain in the high- impedance state . 8. E or W must be ≥ V IH durin g address transitions. NO. Symbols Para[...]

  • Page 8

    STK17T88 Document Number: 001-52040 Rev . *A Page 8 of 22 AutoStore/Power Up RECALL Figure 9. Au toStore Power Up RECAL L Notes 9. t HRECALL starts from the time V CC rises above V SWITCH 10. If an SRAM WRITE has not t aken place since the last nonvolatile cycle, no STORE will t ake place 1 1. Indu strial Grade Devices require 15 ms Max. NO. Symbol[...]

  • Page 9

    STK17T88 Document Number: 001-52040 Rev . *A Page 9 of 22 Figure 10. Software Sto r e / Recall Cycle: E CONTROLLED [13] Sof tware-Controlled STORE/RECALL Cycle In the following table, the software controlled STORE and RECALL cycle p a rameters are li ste d. [12, 13] NO. Symbols Parameter STK17T88-35 STK17T88-45 Units Notes E Cont Alternate Min Max [...]

  • Page 10

    STK17T88 Document Number: 001-52040 Rev . *A Page 10 of 22 Hardware STORE Cycle Figure 1 1. Hardware ST ORE Cycle Sof t Sequence Commands Figure 12. Soft Sequence Command NO. Symbols Parameter STK17T88 Units Notes St andard Alternate Min Max 31 t DELA Y t HLQZ Hardware STORE to SRAM Disabled 1 70 µ s1 4 32 t HLHX Hardware ST ORE Pulse Width 15 ns [...]

  • Page 11

    STK17T88 Document Number: 001-52040 Rev . *A Page 1 1 of 22 MODE Selection E W G A 14 -A 0 Mode I/O Power Notes H X X X Not Selected Output High Z S tandby L H L X Read SRAM Outp ut Da ta Active L L X X Write SRAM Input Data Active LH L0 x 0 E 3 8 0x31C7 0x03E0 0x3C1F 0x303F Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Output Data Output Data [...]

  • Page 12

    STK17T88 Document Number: 001-52040 Rev . *A Page 12 of 22 nvSRAM Operation The STK17T88 nvSRAM is made up of two functional compo - nents paired in the same physical cell. Th ese are the SRAM memory cell and a nonvolatil e QuantumTrap™ cell. The SRAM memory cell operates like a standard f ast static RAM. Data in the SRAM can be transferred to th[...]

  • Page 13

    STK17T88 Document Number: 001-52040 Rev . *A Page 13 of 22 Sof tware STORE Data can be transferred from the SRAM to t he nonvolatile memory by a software address sequence. The STK17T88 software STORE cycle is initiated by executing s equential E controlled READ cycles from six specific address locations in exact ord er . During th e STORE cycle, pr[...]

  • Page 14

    STK17T88 Document Number: 001-52040 Rev . *A Page 14 of 22 Real Time Clock The clock registers maintain time up to 9,999 years in one-second increments. The user can set the time to any calendar time and the clock automat ically keeps track of days of the week and month, leap years, and cent ury tra nsition s. There are eight regist ers dedicated t[...]

  • Page 15

    STK17T88 Document Number: 001-52040 Rev . *A Page 15 of 22 minute, have one second eithe r shortened by 128 or lengthened by 256 oscillator cycles. If a binary “1” i s loaded int o the reg ister , only th e first 2 minute s of the 64 minu te cycle is modified; if a binary 6 is loaded, the first 12 are affected, and so on. Therefore each calibra[...]

  • Page 16

    STK17T88 Document Number: 001-52040 Rev . *A Page 16 of 22 Figure 15 is a functional diagram of the interrupt logic. Figure 15. Interrup t Block Diagram Interrupt Regist er W at chdog In terrupt Enable (WIE). When set to 1, the watch dog timer drives the I NT pin when a watchdo g time-out occurs. When WIE is set to 0, the watchdog time-o ut only se[...]

  • Page 17

    STK17T88 Document Number: 001-52040 Rev . *A Page 17 of 22 RTC Register Map *A binary value, not a BCD value. 0 - Not implemented, reserved for f uture use. Default Settings of non volatile Calibration an d Interrupt registers f rom factory Calibration Reg ister=00h Interrupt Registe r= 00 h The User should configure to the de sired va lue at start[...]

  • Page 18

    STK17T88 Document Number: 001-52040 Rev . *A Page 18 of 22 Register Map Det ail 0x7FFF Real Time Clock – Y ears D7 D6 D5 D4 D3 D2 D1 D0 10s Y ears Y ears Contains the lower two BCD di gits of the year . Low er nibble contains the value for years; upper nibble contains the value for 10s of years. Each nibble ope rat es from 0 to 9. The range for t[...]

  • Page 19

    STK17T88 Document Number: 001-52040 Rev . *A Page 19 of 22 WDW W atchdog Write Enable. Set t his bit to 1 to disable writing of the watchdog time-out value (WDT5- WDT0). This allows the user to strobe the w atchdog without di st urbing the time-out value. Setting this bit to 0 a llows bits 5-0 to be written. WDT W atchdo g ti me -out sele ctio n. T[...]

  • Page 20

    STK17T88 Document Number: 001-52040 Rev . *A Page 20 of 22 Ordering Codes 0x7FF0 Flags D7 D6 D5 D4 D3 D2 D1 D0 WDF AF PF OSCF 0 CAL W R WDF W atchdog T imer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user . It is cleared to 0 when the Flags register is read or on power up AF Alarm F[...]

  • Page 21

    STK17T88 Document Number: 001-52040 Rev . *A Page 21 of 22 Package Diagram Figure 16. 48-Pin SSOP (51-85061) 51-85061-* C [+] Feedback[...]

  • Page 22

    Document Number: 001-520 40 Rev . *A Revised March 17, 2009 Page 22 of 22 AutoS tore and Qua ntumTr ap are registered tr ademarks of Cypress Se miconductor Corpor ation. All produ cts and comp any names mentio ned in this document may be the trademarks of thei r respective holders. STK17T88 © Cypress Semiconducto r Corporatio n, 2009. The inform a[...]