Texas Instruments TSB12LV26 инструкция обслуживания

2000 Bus Solutions Data Manual[...]

Printed in U.S.A., 03/00 SLLS366A[...]

TSB12L V26 OHCI-Lynx PCI-Based IEEE 1394 Host Controller Data Manual Literature Number: SLLS366A March 2000 Printed on Recycled Paper[...]

IMPORT ANT NOTICE T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify , before placing orders, that information being relied on is current and complete. All product[...]

iii Contents Section Title Page 1 Introduction 1–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description 1–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features 1–1 . . . . . . . . . . . . . . . . . . . . . . . . . [...]

iv 4.7 Configuration ROM Header Register 4–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Bus Identification Register 4–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Bus Options Register 4–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 GUID High Register 4–[...]

v 7.5 Switching Characteristics for PHY -Link Interface 7–3 . . . . . . . . . . . . . . . . . 8 Mechanical Information 8–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

vi List of Illustrations Figure Title Page 2–1 T erminal Assignments 2–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 TSB12L V26 Block Diagram 3–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 GPIO2 and GPIO3 Logic Diagram 5–1 . . . . . . . . . . . . . . . . [...]

vii List of T ables T able Title Page 2–1 Signals Sorted by T erminal Number 2–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 Signal Names Sorted Alphanumerically to T erminal Number 2–3 . . . . . . . . . . 2–3 Power Supply T erminals 2–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

viii 4–10 Host Controller Control Register Description 4–13 . . . . . . . . . . . . . . . . . . . . . . . . 4–1 1 Self-ID Count Register Description 4–14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12 Isochronous Receive Channel Mask High Register Description 4–15 . . . . . . . 4–13 Isochronous Receive Channel Ma[...]

1–1 1 Introduction 1.1 Description The T exas Instruments TSB12L V26 is a PCI-to-1394 host controller compatible with the latest PCI Local Bus , PCI Bus Power Management Interface , IEEE 1394-1995, and 1394 Open Host Controller Interface Specification . The chip provides the IEEE 1394 link function, and is compatible with serial bus data rates of[...]

1–2 1.3 Related Documents • 1394 Open Host Controller Interface Specification 1.0 • P1394 Standard for a High Performance Serial Bus (IEEE 1394-1995) • P1394a Draft Standard for a High Performance Serial Bus (Supplement) • PC 99 Design Guide • PCI Bus Power Management Interface Specification (Revision 1.0) • PCI Local Bus Specificatio[...]

2–1 2 T erminal Descriptions This section provides the terminal descriptions for the TSB12L V26. Figure 2–1 shows the signal assigned to each terminal in the package. T able 2–1 is a listing of signal names arranged in terminal number order , and T able 2–2 lists terminals in alphanumeric order by signal names. 1 2 3 4 5 6 7 8 9 10 11 12 13[...]

2–2 T able 2–1. Signals Sorted by T erminal Number NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME 1 GND 26 PCI_AD25 51 PCI_SERR 76 PCI_RST 2 GPIO2 27 PCI_AD24 52 PCI_P AR 77 CYCLEOUT 3 GPIO3 28 PCI_C/BE3 53 PCI_C/BE1 78 CYCLEIN 4 SCL 29 PCI_IDSEL 54 PCI_AD15 79 REG_EN 5 SDA 30 GND 55 3.3 V CC 80 3.3 V CC 6 V CCP 31 PCI_[...]

2–3 T able 2–2. Signal Names Sorted Alphanumerically to T erminal Number TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. CYCLEIN 78 PCI_AD1 1 59 PCI_CLK 12 PHY_DA T A7 81 CYCLEOUT 77 PCI_AD12 58 PCI_CLKRUN 7 PHY_LINKON 98 GND 1 PCI_AD13 57 PCI_DEVSEL 47 PHY_LPS 99 GND 11 PCI_AD14 56 PCI_FRAME 43 PHY_LREQ 97 GND 24 PCI_AD[...]

2–4 T able 2–4. PCI System T erminals TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION G_RST 10 I Global power reset. This reset brings all of the TSB12L V26 internal registers to their default states, including those registers not reset by PCI_RST . When G_RST is asserted, the device is completely nonfunctional. When implementing wake capabil[...]

2–5 T able 2–5. PCI Address and Data T erminals TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD1 1 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 P[...]

2–6 T able 2–6. PCI Interface Control T erminals TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION PCI_C/BE0 PCI_C/BE1 PCI_C/BE2 PCI_C/BE3 65 53 41 28 I/O PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the same PCI terminals. During the address phase of a bus cycle PCI_C/BE3 –PCI_C/BE0 defines the bu[...]

2–7 T able 2–7. IEEE 1394 PHY/Link T erminals TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION PHY_CTL1 PHY_CTL0 92 93 I/O PHY -link interface control. These bidirectional signals control passage of information between the two devices. The TSB12L V26 can only drive these terminals after the PHY has granted permission following a link request ([...]

2–8[...]

3–1 3 TSB12L V26 Controller Programming Model This section describes the internal registers used to program the TSB12L V26. All registers are detailed in the same format: a brief description for each register , followed by the register offset and a bit table describing the reset state for each register . A bit description table, typically include[...]

3–2 Internal Registers ISO T ransmit Contexts Async T ransmit Contexts Physical DMA & Response PCI T arget SM PHY Register Access & Status Monitor Central Arbiter & PCI Initiator SM Cycle Start Generator & Cycle Monitor Synthesized Bus Reset Receive FIFO Link T ransmit Link Receive PCI Host Bus Interface Resp Timeout Request Filte[...]

3–3 3.1 PCI Configuration Registers The TSB12L V26 is a single-function PCI device. The configuration header is compliant with the PCI Local Bus Specification as a standard header . T able 3–2 illustrates the PCI configuration header that includes both the predefined portion of the configuration space and the user definable registers. T able 3?[...]

3–4 3.3 Device ID Register The device ID register contains a value assigned to the TSB12L V26 by T exas Instruments. The device identification for the TSB12L V26 is 8020h. Bit 15 14 13 12 11 10 9876543210 Name Device ID T ype RRRRRRRRRRRRRRRR Default 1000000000100000 Register: Device ID T ype: Read-only Offset: 02h Default: 8020h 3.4 Command Regi[...]

3–5 3.5 Status Register The status register provides status over the TSB12L V26 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification . See T able 3–4 for a complete description of the register contents. Bit 15 14 13 12 11 10 9876543210 Name Status T ype RCU RCU RCU RCU RCU R R RCU R R R R R R [...]

3–6 3.6 Class Code and Revision ID Register The class code and revision ID register categorizes the TSB12L V26 as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See T able 3–5 for a complete description of the [...]

3–7 3.8 Header T ype and BIST Register The header type and BIST register indicates the TSB12L V26 PCI header type, and indicates no built-in self test. See T able 3–7 for a complete description of the register contents. Bit 15 14 13 12 11 10 9876543210 Name Header type and BIST T ype RRRRRRRRRRRRRRRR Default 0000000000000000 Register: Header ty[...]

3–8 3.10 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. See the OHCI Base Address Register , Section 3.9, for bit field details. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name TI extension base address T ype R/W R/W R/W R/W[...]

3–9 3.12 Power Management Capabilities Pointer Register The power management capabilities pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides. The TSB12L V26 configuration header double-words at offsets 44h and 48h provide the power management registers. This register is read[...]

3–10 3.14 MIN_GNT and MAX_LA T Register The MIN_GNT and MAX_LA T register is used to communicate to the system the desired setting of bits 15–8 of the latency timer and class cache line size register (offset 0Ch, see Section 3.7). If a serial ROM is detected, then the contents of this register are loaded through the serial ROM interface after a[...]

3–1 1 3.16 Capability ID and Next Item Pointer Register The capability ID and next item pointer register identifies the linked list capability item and provides a pointer to the next capability item. See T able 3–13 for a complete description of the register contents. Bit 15 14 13 12 11 10 9876543210 Name Capability ID and next item pointer T y[...]

3–12 3.17 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the TSB12L V26 related to PCI power management. See T able 3–14 for a complete description of the register contents. Bit 15 14 13 12 11 10 9876543210 Name Power management capabilities T ype RU RU RU RU RU RU RRRRRRRRRR Defa[...]

3–13 3.18 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power management function. This register is not affected by the internally generated reset caused by the transition from the D3 hot to D0 state. See T able 3–15 for a complete description of the re[...]

3–14 3.20 Miscellaneous Configuration Register The miscellaneous configuration register provides miscellaneous PCI-related configuration. See T able 3–17 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Miscellaneous configuration T ype RRRRRRRRRRRRRRRR Default 0000000000000000 Bit 15[...]

3–15 3.21 Link Enhancement Control Register The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial ROM, if present. After these bits are set, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the host controller control register (OHCI offset 50h/54h, see Section 4.16[...]

3–16 T able 3–18. Link Enhancement Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 1 enab_accel R/W Enable acceleration enhancements. OHCI-L ynx compatible. When set to 1, this bit notifies the PHY that the link supports the 1394a acceleration enhancements, i.e., ack-accelerated, fly-by concatenation, etc. It is recomme[...]

3–17 3.23 GPIO Control Register The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports. See T able 3–20 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name GPIO control T ype R/W R R/W R/W R R R RWU R/W R R/W R/W R R R RW U Default 0000000000000000 Bit 15[...]

3–18[...]

4–1 4 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2-Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 3.9). These registers are the primary interface for controlling the TSB12L V26 IEEE 1394 link [...]

4–2 T able 4–1. OHCI Register Map (Continued) DMA CONTEXT REGISTER NAME ABBREVIA TION OFFSET Self ID Reserved — 60h Self ID buffer SelfIDBuf fer 64h Self ID count SelfIDCount 68h Reserved — 6Ch — Isochronous receive channel mask high IRChannelMaskHiSet 70h Isochrono u s recei v e channel mask high IRChannelMaskHiClear 74h Isochronous rece[...]

4–3 T able 4–1. OHCI Register Map (Continued) DMA CONTEXT REGISTER NAME ABBREVIA TION OFFSET Asynchronous context control ContextControlSet 180h Asychronous As y nchrono u s conte x t control ContextControlClear 184h Asychronous Request T ransmit Reserved — 188h [ A TRQ ] Asynchronous context command pointer CommandPtr 18Ch Reserved — 190h?[...]

4–4 4.1 OHCI V ersion Register This register indicates the OHCI version support, and whether or not the serial ROM is present. See T able 4–2 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name OHCI version T ype RRRRRRRRRRRRRRRR Default 0000000 X 00000001 Bit 15 14 13 12 11 1 0 98765432[...]

4–5 4.2 GUID ROM Register The GUID ROM register is used to access the serial ROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI version register (OHCI offset 00h, see Section 4.1) is set. See T able 4–3 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name GUID ROM T ype RSU R R [...]

4–6 4.3 Asynchronous T ransmit Retries Register The asynchronous transmit retries register indicates the number of times the TSB12L V26 attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See T able 4–4 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23[...]

4–7 4.5 CSR Compare Register The CSR compare register is used to access the bus management CSR registers from the host through compare-swap operations. This register contains the data to be compared with the existing value of the CSR resource. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CSR compare T ype RRRRRRRRRRRRRRRR Default XXXX[...]

4–8 4.7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See T able 4–6 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Configuration ROM header T ype R/W R/W R/W R/W R/[...]

4–9 4.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See T able 4–7 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Bus options T ype R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X 0 0 0 0 X X X [...]

4–10 4.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a hardware reset, which is an illegal GUID value. If a serial ROM is detected, t[...]

4–1 1 4.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See T able 4–8 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Configuration RO[...]

4–12 4.14 Posted Write Address High Register The posted write address high register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. See T able 4–9 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Posted wr[...]

4–13 4.16 Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the TSB12L V26. See T able 4–10 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Host controller control T ype R RSC R R R R R R RC RSC R R RSC RSC RSC RSCU De[...]

4–14 4.17 Self-ID Buffer Pointer Register The self-ID buffer pointer register points to the 2-Kbyte aligned base address of the buf fer in host memory where the self-ID packets are stored during bus initialization. Bits 31–1 1 are read/write accessible. Reserved bits 10–0 are read-only and return 0s when read. Bit 31 30 29 28 27 26 25 24 23 2[...]

4–15 4.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register is used to enable packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register . See T able 4–12 for[...]

4–16 T able 4–12. Isochronous Receive Channel Mask High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 6 isoChannel38 RSC When this bit is set, the TSB12L V26 is enabled to receive from iso channel number 38. 5 isoChannel37 RSC When this bit is set, the TSB12L V26 is enabled to receive from iso channel number 37. 4 isoChannel3[...]

4–17 4.21 Interrupt Event Register The interrupt event set/clear register reflects the state of the various TSB12L V26 interrupt sources. The interrupt bits are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register . The only mechanism to clear a bit in this register is to wr[...]

4–18 T able 4–14. Interrupt Event Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 17 busReset RSCU Indicates that the PHY chip has entered bus reset mode. 16 selfIDcomplete RSCU A selfID packet stream has been received. It is generated at the end of the bus initialization process. This bit is turned off simultaneously when bit [...]

4–19 4.22 Interrupt Mask Register The interrupt mask set/clear register is used to enable the various TSB12L V26 interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register . In all cases except masterIntEnable (bit 31) and V endorSpecific (bit 30), the enables for each int[...]

4–20 4.23 Isochronous T ransmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set. Upon determining that th[...]

4–21 4.24 Isochronous T ransmit Interrupt Mask Register The isochronous transmit interrupt mask set/clear register is used to enable the isochTx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register . In all cases the enables[...]

4–22 4.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set. Upon determining that the interrup[...]

4–23 4.27 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. See T able 4–18 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Fairness cont[...]

4–24 4.28 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the TSB12L V26. It contains controls for the receiver and cycle timer . See T able 4–19 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 [...]

4–25 4.29 Node Identification Register The node identification register contains the address of the node on which the OHCI-L ynx chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15–6) and the NodeNumber field (bits 5–0) is referred to as the node ID. See T able 4–20 for a complete[...]

4–26 4.30 PHY Layer Control Register The PHY layer control register is used to read or write a PHY register . See T able 4–21 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PHY layer control T ype RU R R R RU RU RU RU RU RU RU RU RU RU RU RU Default 0000000000000000 Bit 15 14 13 12 [...]

4–27 4.31 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset. When the TSB12L V26 is cycle master , this register is transmitted with the cycle start message. When the TSB12L V26 is not cycle master , this register is loaded with the data field in an incoming cycle start. In the eve[...]

4–28 4.32 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register is used to enable asynchronous receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined. If the bit correspon[...]

4–29 T able 4–23. Asynchronous Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 18 asynReqResource50 RSC If this bit is set for local bus node number 50, then asynchronous requests received by the TSB12L V26 from that node are accepted. 17 asynReqResource49 RSC If this bit is set for local bus node number 49,[...]

4–30 4.33 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register is used to enable asynchronous receive requests on a per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register . See T able 4–[...]

4–31 4.34 Physical Request Filter High Register The physical request filter high set/clear register is used to enable physical receive requests on a per-node basis and handles the upper node IDs. When a packet is destined for the physical request context and the node ID has been compared against the ARRQ registers, then the comparison is done aga[...]

4–32 T able 4–25. Physical Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 19 physReqResource51 RSC If this bit is set for local bus node number 51, then physical requests received by the TSB12L V26 from that node are handled through the physical request context. 18 physReqResource50 RSC If this bit is set f[...]

4–33 4.35 Physical Request Filter Low Register The physical request filter low set/clear register is used to enable physical receive requests on a per-node basis and handles the lower node IDs. When a packet is destined for the physical request context and the node ID has been compared against the asynchronous request filter registers, then the n[...]

4–34 4.36 Physical Upper Bound Register (Optional Register) The physical upper bound register is an optional register and is not implemented. It returns all 0s when read. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Physical upper bound T ype RRRRRRRRRRRRRRRR Default 0000000000000000 Bit 15 14 13 12 11 1 0 9876543210 Name Physical upp[...]

4–35 4.37 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See T able 4–27 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Asynchronous context control T ype R R R R R R R R R R R R R[...]

4–36 4.38 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the TSB12L V26 accesses when software enables the context by setting the asynchronous context control register (see Section 4.37) bit 15 (run). See T able 4–28 for a compl[...]

4–37 4.39 Isochronous T ransmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, … , 7). See T able 4–29 for a complete description of [...]

4–38 4.40 Isochronous T ransmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the TSB12L V26 accesses when software enables an isochronous transmit context by setting the isochronous transmit context control register (see Section 4.39[...]

4–39 T able 4–30. Isochronous Receive Context Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 29 cycleMatchEnable RSCU When this bit is set, the context begins running only when the 13-bit cycleMatch field (bits 24–12) in the isochronous receive context match register (see Section 4.43) matches the 13-bit cycleCount f[...]

4–40 4.42 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the TSB12L V26 accesses when software enables an isochronous receive context by setting the isochronous receive context control register (see Section 4.41) bit[...]

4–41 4.43 Isochronous Receive Context Match Register The isochronous receive context match register is used to start an isochronous receive context running on a specified cycle number , to filter incoming isochronous packets based on tag values, and to wait for packets with a specified sync value. The n value in the following register addresses i[...]

4–42[...]

5–1 5 GPIO Interface The general-purpose input/output (GPIO) interface consists of two GPIO ports. GPIO2 and GPIO3 power up as general-purpose inputs and are programmable via the GPIO control register . Figure 5–1 shows the logic diagram for GPIO2 and GPIO3 implementation. DQ GPIO Read Data GPIO Write Data GPIO_Invert GPIO Enable GPIO Port Figu[...]

5–2[...]

6–1 6 Serial ROM Interface The TSB12L V26 provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI configuration registers through a serial ROM. The TSB12L V26 communicates with the serial ROM via the 2-wire serial interface. After power-up the serial interface initializes the locations listed in T able 6–1[...]

6–2 T able 6–2. Serial ROM Map BYTE ADDRESS BYTE DESCRIPTION 00 PCI maximum latency (0h) PCI_minimum grant (0h) 01 PCI vendor ID 02 PCI vendor ID (msbyte) 03 PCI subsystem ID (lsbyte) 04 PCI subsystem ID 05 [7] Link_enhancement - Control.enab_unfair [6] HCControl. ProgramPhy Enable [5] RSVD [4] RSVD [3] RSVD [2] Link_enhancement- Control.enab_ [...]

7–1 7 Electrical Characteristics 7.1 Absolute Maximum Ratings Over Operating T emperature Ranges † Supply voltage range, V CC –0.5 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply voltage range, V CCP –0.5 V to 5.5 V . . . . . . . . . . . . . . . . . . . . . [...]

7–2 7.2 Recommended Operating Conditions OPERA TION MIN NOM MAX UNIT V CC Core voltage Commercial 3.3 V 3 3.3 3.6 V V CCP PCI I/O clam p ing voltage Commercial 3.3 V 3 3.3 3.6 V V CCP PCI I/O clamping v oltage Commercial 5 V 4.5 5 5.5 V † PCI 3.3 V 0.475 V CCP V CCP V IH † High level in p ut voltage PCI 5 V 2 V CCP V V IH † High - le v el i[...]

7–3 7.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) OPERA TION TEST CONDITIONS MIN MAX UNIT PCI I OH = – 0.5 mA 0.9 V CC PCI I OH = – 2 mA 2.4 V OH High-level output voltage PHY interface I OH = – 4 µ A 2.8 V PHY interface I OH = – 8 mA V CC – 0.6 Miscellaneous ‡ I OH = – 4 mA V CC – [...]

7–4[...]

8–1 8 Mechanical Information The TSB12L V26 is packaged in a 100-terminal PZ package. The following shows the mechanical dimensions for the PZ package. PZ (S-PQFP-G100) PLASTIC QUAD FLA TP ACK 4040149 /B 11/96 50 26 0,13 NOM Gage Plane 0,25 0,45 0,75 0,05 MIN 0,27 51 25 75 1 12,00 TYP 0,17 76 100 SQ SQ 15,80 16,20 13,80 1,35 1,45 1,60 MAX 14,20 0[...]

8–2[...]

IMPORT ANT NOTICE T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify , before placing orders, that information being relied on is current and complete. All product[...]