NEC 78K/0 Series инструкция обслуживания

User’s Manual Printed in Japan © 78K/0 Series Instructions Document No . U12326EJ4V0UM00 (4th edition) Date Published October 2001 N CP(K) 1995 Common to 78K/0 Series[...]

2 User's Manual U12326EJ4V0UM [MEMO][...]

3 User's Manual U12326EJ4V0UM Caution: Purchase of NEC I 2 C components conveys a license under the Philips I 2 C Patent Rights to use these components in an I 2 C system, provided that the system conforms to the I 2 C Standard Specification as defined by Philips. IEBus is a trademark of NEC Corporation. NOTES FOR CMOS DEVICES 1 PRECAUTION AGA[...]

4 User's Manual U12326EJ4V0UM The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that countr[...]

5 User's Manual U12326EJ4V0UM Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering [...]

6 User's Manual U12326EJ4V0UM Major Revisions in This Edition Page Description Throughout Deletion of all information except for information common to the 78K/0 Series (for individual product information, refer to the user’s manual of each product). The mark shows major revised points.[...]

7 User's Manual U12326EJ4V0UM INTRODUCTION Target Readers This manual is intended for users who wish to understand the functions of 78K/0 Series products and to design and develop its application systems and programs. Purpose This manual is intended to give users an understanding of the various kinds of instruction functions of 78K/0 Series pr[...]

8 User's Manual U12326EJ4V0UM Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Documents Common to 78K/0 Series Document Name Document No. User’s Manual Instructions This manual Application Note Note Basic I U12704E Basic II U1012[...]

9 User's Manual U12326EJ4V0UM CONTENTS CHAPTER 1 MEMORY SPACE ........................................................................................................ ....... 12 1.1 Memory Spaces ............................................................................................................... .1 2 1.2 Internal Program Memory (Int[...]

10 User's Manual U12326EJ4V0UM CHAPTER 5 EXPLANATION OF INSTRUCTIONS ................................................................................. 46 5.1 8-Bit Data Transfer Instructions ...................................................................................... 48 5.2 16-Bit Data Transfer Instructions ..........................[...]

11 User's Manual U12326EJ4V0UM LIST OF FIGURES Figure No. Title Page 2-1 Program Counter Configuration ............................................................................................... ............... 14 2-2 Program Status Word Configuration .........................................................................................[...]

12 User's Manual U12326EJ4V0UM CHAPTER 1 MEMORY SPACE 1.1 Memory Spaces The 78K/0 Series product program memory map varies depending on the internal memory capacity. For details of memory-mapped address area, refer to the user’s manual of each product. 1.2 Internal Program Memory (Internal ROM) Space Each 78K/0 Series product has internal RO[...]

13 CHAPTER 1 MEMORY SPACE User's Manual U12326EJ4V0UM (3) RAM for VFD display There are some products in the 78K/0 Series to which RAM for VFD display is allocated. This RAM can also be used as an ordinary RAM area. (4) Internal expansion RAM There are some products in the 78K/0 Series to which internal expansion RAM is allocated. (5) RAM for [...]

14 User's Manual U12326EJ4V0UM CHAPTER 2 REGISTERS 2.1 Control Registers The control registers control the program sequence, statuses and stack memory. A program counter, a program status word and a stack pointer are the control registers. 2.1.1 Program counter (PC) The program counter is a 16-bit register that holds the address information of[...]

15 CHAPTER 2 REGISTERS User's Manual U12326EJ4V0UM (1) Interrupt enable flag (IE) This flag controls the interrupt request acknowledgement operations of the CPU. When IE = 0, the IE flag is set to interrupt disable (DI), and interrupts other than non-maskable interrupts are all disabled. When IE = 1, the IE flag is set to interrupt enable (EI)[...]

16 CHAPTER 2 REGISTERS User's Manual U12326EJ4V0UM Interrupt and BRK instructions PSW PC15-PC8 PC15-PC8 PC7-PC0 Lower half register pairs SP SP _ 2 SP _ 2 CALL, CALLF and CALLT instructions PUSH rp instruction SP _ 1 SP SP SP _ 2 SP _ 2 SP _ 1 SP PC7-PC0 SP _ 3 SP _ 2 SP _ 1 SP SP SP _ 3 Upper half register pairs 2.1.3 Stack pointer (SP) This [...]

17 CHAPTER 2 REGISTERS User's Manual U12326EJ4V0UM 2.2 General-Purpose Registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. These registers consist of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). In addition that each register can be used as an 8-bit [...]

18 CHAPTER 2 REGISTERS User's Manual U12326EJ4V0UM Figure 2-6. General-Purpose Register Configuration (a) Absolute names (b) Functional names BANK0 BANK1 BANK2 BANK3 FEFFH FEE0H R0 15 0 7 0 16-bit processing 8-bit processing FEE7H RP3 RP2 RP1 RP0 R1 R2 R3 R4 R5 R6 R7 FEE8H FEEFH FEF0H FEF7H FEF8H BANK0 BANK1 BANK2 BANK3 FEFFH FEE0H X 15 0 7 0 [...]

19 CHAPTER 2 REGISTERS User's Manual U12326EJ4V0UM 2.3 Special Function Registers (SFRs) Unlike a general-purpose register, each special-function register has a special function. Special function registers are allocated in the 256-byte area FF00H to FFFFH. Special function registers can be manipulated, like general-purpose registers, by operat[...]

20 User's Manual U12326EJ4V0UM CHAPTER 3 ADDRESSING 3.1 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When [...]

21 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 15 0 PC 87 70 fa 10 to fa 8 11 10 00001 64 3 CALLF fa 7 to fa 0 3.1.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the “ CALL !addr16 ” or “ BR !addr16 ” or “ CALLF ![...]

22 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 15 1 15 0 PC 70 Low addr. High addr. Memory (Table) Effective address+1 Effective address 01 00000000 87 87 65 0 0 1 11 76 5 1 0 ta 4 – 0 Instruction code 3.1.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the[...]

23 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 3.1.4 Register addressing [Function] The register pair (AX) contents to be specified by an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the “ BR AX ” instruction is executed. [Illustration] 70 rp 07 AX 15 0 PC 87[...]

24 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 3.2 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.2.1 Implied addressing [Function] This addressing automatically specifies the address of the registers that function as an[...]

25 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 3.2.2 Register addressing [Function] Register addressing accesses a general-purpose register as an operand. The general-purpose register to be accessed is specified by the register bank selection flags (RBS0 and RBS1) and the register specification codes (Rn and RPn) in the instruction codes.[...]

26 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 3.2.3 Direct addressing [Function] Direct addressing directly addresses the memory indicated by the immediate data in the instruction word. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !FE00H; When setting !addr16 to FE00H [Illustr[...]

27 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 15 0 Short direct memory Effective address 1 111111 87 0 7 OP code saddr-offset α When 8-bit immediate data is 20H to FFH, α = 0. When 8-bit immediate data is 00H to 1FH, α = 1. 3.2.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed w[...]

28 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 15 0 SFR Effective address 1 111111 87 0 7 OP code sfr-offset 1 3.2.5 Special-function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to[...]

29 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 15 0 8 D 7 E 0 7 7 0 A DE Memory Memory address specified by register pair DE Contents of memory to be addressed are transferred 3.2.6 Register indirect addressing [Function] Register indirect addressing addresses memory with register pair contents specified as an operand. The register pair t[...]

30 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 3.2.7 Based addressing [Function] 8-bit immediate data is added to the contents of the HL register pair as a base register and the sum is used to address the memory. The HL register pair to be accessed is in the register bank specified by the register bank select flag (RBS0 and RBS1). Additio[...]

31 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 3.2.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN instructions are executed or the register is saved/reset upon generation of an interru[...]

32 User's Manual U12326EJ4V0UM CHAPTER 4 INSTRUCTION SET This chapter lists the instructions in the 78K/0 Series instruction set. The instructions are common to all 78K/0 Series products. 4.1 Operation For the operation list for each product, refer to the user’s manual of each product. 4.1.1 Operand identifiers and description methods Operan[...]

33 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 4.1.2 Description of “operation” column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Progr[...]

34 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 4.1.4 Description of number of clocks 1 instruction clock cycle is 1 CPU clock cycle (f CPU ) selected by the processor clock control register (PCC). 4.1.5 Instructions listed by addressing type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, D[...]

35 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 2nd Operand #byte A r Note sfr saddr !addr16 PSW [DE] [HL] [HL+byte] $addr16 1 None [HL+B] 1st Operand [HL+C] A ADD MOV MOV MOV MOV MOV MOV MOV MOV ROR ADDC XCH XCH XCH XCH XCH XCH XCH ROL SUB ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUB[...]

36 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 2nd Operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None 1st Operand A.bit MOV1 BT SET1 BF CLR1 BTCLR sfr.bit MOV1 BT SET1 BF CLR1 BTCLR saddr.bit MOV1 BT SET1 BF CLR1 BTCLR PSW.bit MOV1 BT SET1 BF CLR1` BTCLR [HL].bit MOV1 BT SET1 BF CLR1 BTCLR CY MOV1 MOV1 MOV1 MOV1 MOV1 SE[...]

37 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ 2nd Operand AX !addr16 !addr11 [addr5] $addr16 1st Operand Basic Instructions BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound Instructions BT BF BTCLR DBNZ (5) Other instructions ADJB[...]

38 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 4.2 Instruction Codes 4.2.1 Description of instruction code table rr p R B R 2 R 1 R 0 reg P 1 P 0 reg-pair RB 1 RB 0 reg-bank 0 0 0 R0 X 0 0 RP0 AX 0 0 RB0 0 0 1 R1 A 0 1 RP1 BC 0 1 RB1 0 1 0 R2 C 1 0 RP2 DE 1 0 RB2 0 1 1 R3 B 1 1 RP3 HL 1 1 RB3 100 R 4 E 101 R 5 D 110 R 6 L 111 R 7 H B[...]

39 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 4.2.2 Instruction code list Instruction Mnemonic Operands Operation Code Group B1 B2 B3 B4 8-Bit Data MOV r,#byte 1010 0 R 2 R 1 R 0 Data Transfer saddr,#byte 0001 0001 Saddr-offset Data sfr,#byte 0001 0011 Sfr-offset Data A,r Note 0110 0 R 2 R 1 R 0 r,A Note 0111 0 R 2 R 1 R 0 A,saddr 1[...]

40 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 16-Bit Data MOVW rp,#word 0001 0 P 1 P 0 0 Low byte High byte Transfer saddrp,#word 1110 1110 Saddr-offset Low byte High byte sfrp,#word 1111 1110 Sfr-offset Low byte High byte AX,saddrp 1000 1001 Saddr-offset saddrp,AX 1001 1001 Saddr-offset AX,sfrp 1010 1001 Sfr-offset sfrp,AX 1011 100[...]

41 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 8-Bit SUB A,#byte 0001 1101 Data Operation saddr,#byte 1001 1000 Saddr-offset Data A,r Note 0110 0001 0001 1 R 2 R 1 R 0 r , A 0110 0001 0001 0 R 2 R 1 R 0 A,saddr 0001 1110 Saddr-offset A,!addr16 0001 1000 Low addr High addr A,[HL] 0001 1111 A,[HL+byte] 0001 1001 Data A,[HL+B] 0011 0001[...]

42 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 8-Bit OR A,#byte 0110 1101 Data Operation saddr,#byte 1110 1000 Saddr-offset Data A,r Note 0110 0001 0110 1 R 2 R 1 R 0 r , A 0110 0001 0110 0 R 2 R 1 R 0 A,saddr 0110 1110 Saddr-offset A,!addr16 0110 1000 Low addr High addr A,[HL] 0110 1111 A,[HL+byte] 0110 1001 Data A,[HL+B] 0011 0001 [...]

43 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 16-Bit ADDW AX,#word 1100 1010 Low byte High byte Operation SUBW AX,#word 1101 1010 Low byte High byte CMPW AX,#word 1110 1010 Low byte High byte Multiply/ MULU X 0011 0001 1000 1000 divide DIVUW C 0011 0001 1000 0010 Increment/ INC r 0100 0 R 2 R 1 R 0 decrement saddr 1000 0001 Saddr-of[...]

44 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM Bit OR1 CY,saddr.bit 0111 0001 0 B 2 B 1 B 0 0110 Saddr-offset Manipulation CY,sfr.bit 0111 0001 0 B 2 B 1 B 0 1110 Sfr-offset CY,A.bit 0110 0001 1 B 2 B 1 B 0 1110 CY,PSW.bit 0111 0001 0 B 2 B 1 B 0 0110 0001 1110 CY,[HL].bit 0111 0001 1 B 2 B 1 B 0 0110 XOR1 CY,saddr.bit 0111 0001 0 B [...]

45 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM Unconditional BR !addr16 1001 1011 Low addr High addr Branch $addr16 1111 1010 jdisp A X 0011 0001 1001 1000 Conditional BC $addr16 1000 1101 jdisp Branch BNC $addr16 1001 1101 jdisp BZ $addr16 1010 1101 jdisp BNZ $addr16 1011 1101 jdisp BT saddr.bit,$addr16 1 B 2 B 1 B 0 1100 Saddr-offs[...]

46 User's Manual U12326EJ4V0UM CHAPTER 5 EXPLANATION OF INSTRUCTIONS This chapter explains the instructions of 78K/0 Series products. Each instruction is described with a mnemonic, including description of multiple operands. The basic configuration of instruction description is shown on the next page. For the number of instruction bytes and th[...]

47 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM DESCRIPTION EXAMPLE Mnemonic Full name Move MO V Byte Data Transfer Meaning of instruction [Instruction format] MOV dst, src: Indicates the basic description format of the instruction. [Operation] dst ← src: Indicates instruction operation using symbols. [Operand] Indicates[...]

48 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.1 8-Bit Data Transfer Instructions The following instructions are 8-bit data transfer instructions. MOV ... 49 XCH ... 50[...]

49 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Move MO V Byte Data Transfer [Instruction format] MOV dst, src [Operation] dst ← src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) MOV r, #byte MOV A, PSW saddr, #byte PSW, A sfr, #byte A, [DE] A , r Note [DE], A r , A Note A, [HL] A, saddr [HL], A saddr, A [...]

50 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Exchange XCH Byte Data Exchange [Instruction format] XCH dst, src [Operation] dst ↔ src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) XCH A , r Note XCH A, [HL] A, saddr A, [HL+byte] A, sfr A, [HL+B] A, !addr16 A, [HL+C] A, [DE] Note Except r = A [Flag] ZA C[...]

51 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.2 16-Bit Data Transfer Instructions The following instructions are 16-bit data transfer instructions. MOVW ... 52 XCHW ... 53[...]

52 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Move Word MO VW Word Data Transfer [Instruction format] MOVW dst, src [Operation] dst ← src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) MOVW rp, #word MOVW sfrp, AX saddrp, #word AX, rp Note sfrp, #word rp, AX Note AX, saddrp AX, !addr16 saddrp, AX !addr16[...]

53 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Exchange Word XCHW Word Data Exchange [Instruction format] XCHW dst, src [Operation] dst ↔ src [Operand] Mnemonic Operand(dst,src) XCHW AX, rp Note Note Only when rp = BC, DE or HL [Flag] ZA C C Y [Description] • The 1st and 2nd operand contents are exchanged. [Descriptio[...]

54 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.3 8-Bit Operation Instructions The following are 8-bit operation instructions. ADD ... 55 ADDC ... 56 SUB ... 57 SUBC ... 58 AND ... 59 OR ... 60 XOR ... 61 CMP ... 62[...]

55 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Add ADD Byte Data Addition [Instruction format] ADD dst, src [Operation] dst, CY ← dst + src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) ADD A, #byte ADD A, !addr16 saddr, #byte A, [HL] A , r Note A, [HL+byte] r, A A, [HL+B] A, saddr A, [HL+C] Note Except [...]

56 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Add with Carry ADDC Addition of Byte Data with Carry [Instruction format] ADDC dst, src [Operation] dst, CY ← dst + src + CY [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) ADDC A, #byte ADDC A, !addr16 saddr, #byte A, [HL] A , r Note A, [HL+byte] r, A A, [HL+[...]

57 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Subtract SUB Byte Data Subtraction [Instruction format] SUB dst, src [Operation] dst, CY ← dst – src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) SUB A, #byte SUB A, !addr16 saddr, #byte A, [HL] A , r Note A, [HL+byte] r, A A, [HL+B] A, saddr A, [HL+C] No[...]

58 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Subtract with Carry SUBC Subtraction of Byte Data with Carry [Instruction format] SUBC dst, src [Operation] dst, CY ← dst – src – CY [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) SUBC A, #byte SUBC A, !addr16 saddr, #byte A, [HL] A , r Note A, [HL+byte] [...]

59 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM And AND Logical Product of Byte Data [Instruction format] AND dst, src [Operation] dst ← dst ∧ src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) AND A, #byte AND A, !addr16 saddr, #byte A, [HL] A , r Note A, [HL+byte] r, A A, [HL+B] A, saddr A, [HL+C] Note[...]

60 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Or OR Logical Sum of Byte Data [Instruction format] OR dst, src [Operation] dst ← dst ∨ src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) OR A, #byte OR A, !addr16 saddr, #byte A, [HL] A , r Note A, [HL+byte] r, A A, [HL+B] A, saddr A, [HL+C] Note Except r[...]

61 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Exclusive Or XOR Exclusive Logical Sum of Byte Data [Instruction format] XOR dst, src [Operation] dst ← dst ∨ src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) XOR A, #byte XOR A, !addr16 saddr, #byte A, [HL] A , r Note A, [HL+byte] r, A A, [HL+B] A, saddr[...]

62 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Compare CMP Byte Data Comparison [Instruction format] CMP dst, src [Operation] dst – src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) CMP A, #byte CMP A, !addr16 saddr, #byte A, [HL] A , r Note A, [HL+byte] r, A A, [HL+B] A, saddr A, [HL+C] Note Except r = [...]

63 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.4 16-Bit Operation Instructions The following are 16-bit operation instructions. ADDW ... 64 SUBW ... 65 CMPW ... 66[...]

64 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Add Word ADD W Word Data Addition [Instruction format] ADDW dst, src [Operation] dst, CY ← dst + src [Operand] Mnemonic Operand(dst,src) ADDW AX, #word [Flag] ZA C C Y ××× [Description] • The destination operand (dst) specified by the 1st operand is added to the source[...]

65 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Subtract Word SUBW Word Data Subtraction [Instruction format] SUBW dst, src [Operation] dst, CY ← dst – src [Operand] Mnemonic Operand(dst,src) SUBW AX, #word [Flag] ZA C C Y ××× [Description] • The source operand (src) specified by the 2nd operand is subtracted from[...]

66 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Compare Word CMPW Word Data Comparison [Instruction format] CMPW dst, src [Operation] dst – src [Operand] Mnemonic Operand(dst,src) CMPW AX, #word [Flag] ZA C C Y ××× [Description] • The source operand (src) specified by the 2nd operand is subtracted from the destinati[...]

67 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.5 Multiply/Divide Instructions The following are multiply/divide instructions. MULU ... 68 DIVUW ... 69[...]

68 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Multiply Unsigned MULU Unsigned Multiplication of Data [Instruction format] MULU src [Operation] AX ← A × src [Operand] Mnemonic Operand(src) MULU X [Flag] ZA C C Y [Description] • The A register contents and the source operand (src) data are multiplied as unsigned data [...]

69 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Divide Unsigned Word DIVUW Unsigned Division of Word Data [Instruction format] DIVUW dst [Operation] AX (quotient), dst (remainder) ← AX ÷ dst [Operand] Mnemonic Operand(dst) DIVUW C [Flag] ZA C C Y [Description] • The AX register contents are divided by the destination [...]

70 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.6 Increment/Decrement Instructions The following are increment/decrement instructions. INC ... 71 DEC ... 72 INCW ... 73 DECW ... 74[...]

71 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Increment INC Byte Data Increment [Instruction format] INC dst [Operation] dst ← dst + 1 [Operand] Mnemonic Operand(dst) INC r saddr [Flag] ZA C C Y ×× [Description] • The destination operand (dst) contents are incremented by only one. • If the increment result is 0, [...]

72 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Decrement DEC Byte Data Decrement [Instruction format] DEC dst [Operation] dst ← dst – 1 [Operand] Mnemonic Operand(dst) DEC r saddr [Flag] ZA C C Y ×× [Description] • The destination operand (dst) contents are decremented by only one. • If the decrement result is 0[...]

73 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Increment Word INCW Word Data Increment [Instruction format] INCW dst [Operation] dst ← dst + 1 [Operand] Mnemonic Operand(dst) INCW rp [Flag] ZA C C Y [Description] • The destination operand (dst) contents are incremented by only one. • Because this instruction is freq[...]

74 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Decrement Word DECW Word Data Decrement [Instruction format] DECW dst [Operation] dst ← dst – 1 [Operand] Mnemonic Operand (dst) DECW rp [Flag] ZA C C Y [Description] • The destination operand (dst) contents are decremented by only one. • Because this instruction is f[...]

75 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.7 Rotate Instructions The following are rotate instructions. ROR ... 76 ROL ... 77 RORC ... 78 ROLC ... 79 ROR4 ... 80 ROL4 ... 81[...]

76 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Rotate Right RO R Byte Data Rotation to the Right [Instruction format] ROR dst, cnt [Operation] (CY, dst 7 ← dst 0 , dst m – 1 ← dst m ) × one time [Operand] Mnemonic Operand(dst,cnt) ROR A, 1 [Flag] ZA C C Y × [Description] • The destination operand (dst) contents [...]

77 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Rotate Left RO L Byte Data Rotation to the Left [Instruction format] ROL dst, cnt [Operation] (CY, dst 0 ← dst 7 , dst m+1 ← dst m ) × one time [Operand] Mnemonic Operand(dst,cnt) ROL A, 1 [Flag] ZA C C Y × [Description] • The destination operand (dst) contents specif[...]

78 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Rotate Right with Carry R ORC Byte Data Rotation to the Right with Carry [Instruction format] RORC dst, cnt [Operation] (CY ← dst 0 , dst 7 ← CY, dst m – 1 ← dst m ) × one time [Operand] Mnemonic Operand(dst,cnt) RORC A, 1 [Flag] ZA C C Y × [Description] • The des[...]

79 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Rotate Left with Carry R OLC Byte Data Rotation to the Left with Carry [Instruction format] ROLC dst, cnt [Operation] (CY ← dst 7 , dst 0 ← CY, dst m+1 ← dst m ) × one time [Operand] Mnemonic Operand(dst,cnt) ROLC A, 1 [Flag] ZA C C Y × [Description] • The destinati[...]

80 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Rotate Right Digit R OR4 Digit Rotation to the Right [Instruction format] ROR4 dst [Operation] A 3-0 ← (dst) 3-0 , (dst) 7-4 ← A 3-0 , (dst) 3-0 ← (dst) 7-4 [Operand] Mnemonic Operand(dst) ROR4 [HL] Note Note Specify an area other than the SFR area as operand [HL]. [Fla[...]

81 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Rotate Left Digit R OL4 Digit Rotation to the Left [Instruction format] ROL4 dst [Operation] A 3-0 ← (dst) 7-4 , (dst) 3-0 ← A 3-0 , (dst) 7-4 ← (dst) 3-0 [Operand] Mnemonic Operand(dst) ROL4 [HL] Note Note Specify an area other than the SFR area as operand [HL]. [Flag][...]

82 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.8 BCD Adjust Instructions The following are BCD adjust instructions. ADJBA ... 83 ADJBS ... 84[...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 83 User's Manual U12326EJ4V0UM Decimal Adjust Register for Addition ADJB A Decimal Adjustment of Addition Result [Instruction format] ADJBA [Operation] Decimal Adjust Accumulator for Addition [Operand] None [Flag] ZA C C Y ××× [Description] • The A register, CY flag and AC flag are decimally adjusted [...]

84 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Decimal Adjust Register for Subtraction ADJBS Decimal Adjustment of Subtraction Result [Instruction format] ADJBS [Operation] Decimal Adjust Accumulator for Subtraction [Operand] None [Flag] ZA C C Y ××× [Description] • The A register, CY flag and AC flag are decimally a[...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 85 User's Manual U12326EJ4V0UM 5.9 Bit Manipulation Instructions The following are bit manipulation instructions. MOV1 ... 86 AND1 ... 87 OR1 ... 88 XOR1 ... 89 SET1 ... 90 CLR1 ... 91 NOT1 ... 92[...]

86 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Move Single Bit MO V1 1 Bit Data Transfer [Instruction format] MOV1 dst, src [Operation] dst ← src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) MOV1 CY, saddr.bit MOV1 saddr.bit, CY CY, sfr.bit sfr.bit, CY CY, A.bit A.bit, CY CY, PSW.bit PSW.bit, CY CY, [HL[...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 87 User's Manual U12326EJ4V0UM And Single Bit AND1 1 Bit Data Logical Product [Instruction format] AND1 dst, src [Operation] dst ← dst ∧ src [Operand] Mnemonic Operand(dst,src) AND1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Flag] ZA C C Y × [Description] • Logical product of bit [...]

88 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Or Single Bit OR1 1 Bit Data Logical Sum [Instruction format] OR1 dst, src [Operation] dst ← dst ∨ src [Operand] Mnemonic Operand(dst,src) OR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Flag] ZA C C Y × [Description] • The logical sum of bit data of [...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 89 User's Manual U12326EJ4V0UM Exclusive Or Single Bit XOR1 1 Bit Data Exclusive Logical Sum [Instruction format] XOR1 dst, src [Operation] dst ← dst ∨ src [Operand] Mnemonic Operand(dst,src) XOR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Flag] ZA C C Y × [Description] • The excl[...]

90 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Set Single Bit (Carry Flag) SET1 1 Bit Data Set [Instruction format] SET1 dst [Operation] dst ← 1 [Operand] Mnemonic Operand(dst) SET1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit CY [Flag] dst = PSW.bit dst = CY In all other cases Z AC CY Z AC CY Z AC CY ××× 1 [Description][...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 91 User's Manual U12326EJ4V0UM Clear Single Bit (Carry Flag) CLR1 1 Bit Data Clear [Instruction format] CLR1 dst [Operation] dst ← 0 [Operand] Mnemonic Operand(dst) CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit CY [Flag] dst = PSW.bit dst = CY In all other cases Z AC CY Z AC CY Z AC CY ××× 0 [Descript[...]

92 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Not Single Bit (Carry Flag) NO T1 1 Bit Data Logical Negation [Instruction format] NOT1 dst [Operation] dst ← dst [Operand] Mnemonic Operand(dst) NOT1 CY [Flag] ZA C C Y × [Description] • The CY flag is inverted. [Description example] NOT1 CY; The CY flag is inverted.[...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 93 User's Manual U12326EJ4V0UM 5.10 Call Return Instructions The following are call return instructions. CALL ... 94 CALLF ... 95 CALLT ... 96 BRK ... 97 RET ... 98 RETI ... 99 RETB ... 100[...]

94 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Call CALL Subroutine Call (16 Bit Direct) [Instruction format] CALL target [Operation] (SP – 1) ← (PC+3) H , (SP – 2) ← (PC+3) L , SP ← SP – 2, PC ← target [Operand] Mnemonic Operand(target) CALL !addr16 [Flag] ZA C C Y [Description] • This is a subroutine cal[...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 95 User's Manual U12326EJ4V0UM Call Flag CALLF Subroutine Call (11 Bit Direct Specification) [Instruction format] CALLF Target [Operation] (SP – 1) ← (PC+2) H , (SP – 2) ← (PC+2) L , SP ← SP – 2, PC ← target [Operand] Mnemonic Operand(target) CALLF !addr11 [Flag] ZA C C Y [Description] • Th[...]

96 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Call Table CALL T Subroutine Call (Refer to the Call Table) [Instruction format] CALLT [addr5] [Operation] (SP – 1) ← (PC+1) H , (SP – 2) ← (PC+1) L , SP ← SP – 2, PC H ← (00000000, addr5+1) PC L ← (00000000, addr5) [Operand] Mnemonic Operand([addr5]) CALLT [a[...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 97 User's Manual U12326EJ4V0UM Break BRK Software Vectored Interrupt [Instruction format] BRK [Operation] (SP – 1) ← PSW, (SP – 2) ← (PC+1) H , (SP – 3) ← (PC+1) L , IE ← 0, SP ← SP – 3, PC H ← (3FH), PC L ← (3EH) [Operand] None [Flag] ZA C C Y [Description] • This is a software int[...]

98 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Return RET Return from Subroutine [Instruction format] RET [Operation] PC L ← (SP), PC H ← (SP+1), SP ← SP+2 [Operand] None [Flag] ZA C C Y [Description] • This is a return instruction from the subroutine call made with the CALL, CALLF and CALLT instructions. • The [...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 99 User's Manual U12326EJ4V0UM Return from Interrupt RETI Return from Hardware Vectored Interrupt [Instruction format] RETI [Operation] PC L ← (SP), PC H ← (SP+1), PSW ← (SP+2), SP ← SP+3, NMIS ← 0 [Operand] None [Flag] ZA C C Y RRR [Description] • This is a return instruction from the vectored[...]

100 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Return from Break RETB Return from Software Vectored Interrupt [Instruction format] RETB [Operation] PC L ← (SP), PC H ← (SP+1), PSW ← (SP+2), SP ← SP+3 [Operand] None [Flag] ZA C C Y RRR [Description] • This is a return instruction from the software interrupt gene[...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 101 User's Manual U12326EJ4V0UM 5.11 Stack Manipulation Instructions The following are stack manipulation instructions. PUSH ... 102 POP ... 103 MOVW SP, src ... 104 MOVW AX, SP ... 104[...]

102 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Push PUSH Push [Instruction format] PUSH src [Operation] When src = rp When src = PSW (SP – 1) ← src H , (SP – 1) ← src (SP – 2) ← src L ,S P ← SP – 1 SP ← SP – 2 [Operand] Mnemonic Operand(src) PUSH PSW rp [Flag] ZA C C Y [Description] • The data of th[...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 103 User's Manual U12326EJ4V0UM Pop POP Pop [Instruction format] POP dst [Operation] When dst = rp When dst = PSW dst L ← (SP), dst ← (SP) dst H ← (SP+1), SP ← SP+1 SP ← SP+2 [Operand] Mnemonic Operand(dst) POP PSW rp [Flag] dst =rp PSW Z AC CY Z AC CY RRR [Description] • Data is returned from [...]

104 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM MO VW SP , src Move Word MO VW AX, SP Word Data Transfer with Stack Pointer [Instruction format] MOVW dst, src [Operation] dst ← src [Operand] Mnemonic Operand(dst,src) MOVW SP, #word SP, AX AX, SP [Flag] ZA C C Y [Description] • This is an instruction to manipulate the [...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 105 User's Manual U12326EJ4V0UM 5.12 Unconditional Branch Instruction The unconditional branch instruction is shown below. BR ... 106[...]

106 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Branch BR Unconditional Branch [Instruction format] BR target [Operation] PC ← target [Operand] Mnemonic Operand(target) BR !addr16 AX $addr16 [Flag] ZA C C Y [Description] • This is an instruction to branch unconditionally. • The word data of the target address operan[...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 107 User's Manual U12326EJ4V0UM 5.13 Conditional Branch Instructions Conditional branch instructions are shown below. BC ... 108 BNC ... 109 BZ ... 110 BNZ ... 111 BT ... 112 BF ... 113 BTCLR ... 114 DBNZ ... 115[...]

108 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Branch if Carry BC Conditional Branch with Carry Flag (CY = 1) [Instruction format] BC $addr16 [Operation] PC ← PC+2+jdisp8 if CY = 1 [Operand] Mnemonic Operand($addr16) BC $addr16 [Flag] ZA C C Y [Description] • When CY = 1, data is branched to the address specified by [...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 109 User's Manual U12326EJ4V0UM Branch if Not Carry BNC Conditional Branch with Carry Flag (CY = 0) [Instruction format] BNC $addr16 [Operation] PC ← PC+2+jdisp8 if CY = 0 [Operand] Mnemonic Operand($addr16) BNC $addr16 [Flag] ZA C C Y [Description] • When CY = 0, data is branched to the address specif[...]

110 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Branch if Zero BZ Conditional Branch with Zero Flag (Z = 1) [Instruction format] BZ $addr16 [Operation] PC ← PC+2+jdisp8 if Z = 1 [Operand] Mnemonic Operand($addr16) BZ $addr16 [Flag] ZA C C Y [Description] • When Z = 1, data is branched to the address specified by the o[...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 111 User's Manual U12326EJ4V0UM Branch if Not Zero BNZ Conditional Branch with Zero Flag (Z = 0) [Instruction format] BNZ $addr16 [Operation] PC ← PC+2+jdisp8 if Z = 0 [Operand] Mnemonic Operand($addr16) BNZ $addr16 [Flag] ZA C C Y [Description] • When Z = 0, data is branched to the address specified b[...]

112 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Branch if True BT Conditional Branch by Bit Test (Byte Data Bit = 1) [Instruction format] BT bit, $addr16 [Operation] PC ← PC+b+jdisp8 if bit = 1 [Operand] Mnemonic Operand(bit,$addr16) b(Number of bytes) BT saddr.bit, $addr16 3 sfr.bit, $addr16 4 A.bit, $addr16 3 PSW.bit,[...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 113 User's Manual U12326EJ4V0UM Branch if False BF Conditional Branch by Bit Test (Byte Data Bit = 0) [Instruction format] BF bit, $addr16 [Operation] PC ← PC+b+jdisp8 if bit = 0 [Operand] Mnemonic Operand(bit,$addr16) b(Number of bytes) BF saddr.bit, $addr16 4 sfr.bit, $addr16 4 A.bit, $addr16 3 PSW.bit[...]

114 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Branch if True and Clear BTCLR Conditional Branch and Clear by Bit Test (Byte Data Bit = 1) [Instruction format] BTCLR bit, $addr16 [Operation] PC ← PC+b+jdisp8 if bit = 1, then bit ← 0 [Operand] Mnemonic Operand(bit,$addr16) b(Number of bytes) BTCLR saddr.bit, $addr16 4[...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 115 User's Manual U12326EJ4V0UM Decrement and Branch if Not Zero DBNZ Conditional Loop (R1 ≠ 0) [Instruction format] DBNZ dst, $addr16 [Operation] dst ← dst – 1, then PC ← PC+b+jdisp16 if dst R1 ≠ 0 [Operand] Mnemonic Operand(dst,$addr16) b(Number of bytes) DBNZ B, $addr16 2 C, $addr16 2 saddr, $[...]

116 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.14 CPU Control Instructions The following are CPU control instructions. SEL RBn ... 117 NOP ... 118 EI ... 119 DI ... 120 HALT ... 121 STOP ... 122[...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 117 User's Manual U12326EJ4V0UM Select Register Bank SEL RBn Register Bank Selection [Instruction format] SEL RBn [Operation] RBS0, RBS1 ← n; (n = 0-3) [Operand] Mnemonic Operand(RBn) SEL RBn [Flag] ZA C C Y [Description] • The register bank specified by the operand (RBn) is made a register bank for us[...]

118 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM No Operation NOP No Operation [Instruction format] NOP [Operation] no operation [Operand] None [Flag] ZA C C Y [Description] • Only the time is consumed without processing.[...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 119 User's Manual U12326EJ4V0UM Enable Interrupt EI Interrupt Enabled [Instruction format] EI [Operation] IE ← 1 [Operand] None [Flag] ZA C C Y [Description] • The maskable interrupt acknowledgeable status is set (by setting the interrupt enable flag (IE) to (1)). • No interrupts are acknowledged bet[...]

120 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Disable Interrupt DI Interrupt Disabled [Instruction format] DI [Operation] IE ← 0 [Operand] None [Flag] ZA C C Y [Description] • Maskable interrupt acknowledgment by vectored interrupt is disabled (with the interrupt enable flag (IE) cleared (0)). • No interrupts are [...]

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 121 User's Manual U12326EJ4V0UM Halt HAL T HALT Mode Set [Instruction format] HALT [Operation] Set HALT Mode [Operand] None [Flag] ZA C C Y [Description] • This instruction is used to set the HALT mode to stop the CPU operation clock. The total power consumption of the system can be decreased with interm[...]

122 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Stop ST OP Stop Mode Set [Instruction format] STOP [Operation] Set STOP Mode [Operand] None [Flag] ZA C C Y [Description] • This instruction is used to set the STOP mode to stop the main system clock oscillator and to stop the whole system. Power consumption can be minimiz[...]

123 User's Manual U12326EJ4V0UM APPENDIX A REVISION HISTORY The following table shows the revision history of the previous editions. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. Edition Major Revision from Previous Edition Applied to: 2nd Addition of the following versions: Throughout ?[...]

124 User's Manual U12326EJ4V0UM APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) [8-bit data transfer instructions] MOV ... 49 XCH ... 50 [16-bit data transfer instructions] MOVW ... 52 XCHW ... 53 [8-bit operation instructions] ADD ... 55 ADDC ... 56 SUB ... 57 SUBC ... 58 AND ... 59 OR ... 60 XOR ... 61 CMP ... 62 [16-bit operation instr[...]

125 User's Manual U12326EJ4V0UM [Unconditional branch instruction] BR ... 106 [Conditional branch instructions] BC ... 108 BNC ... 109 BZ ... 110 BNZ ... 111 BT ... 112 BF ... 113 BTCLR ...114 DBNZ ... 115 [CPU control instructions] SEL RBn ... 117 NOP ... 118 EI ... 119 DI ... 120 HALT ... 121 STOP ... 122 APPENDIX B INSTRUCTION INDEX (MNEMON[...]

126 User's Manual U12326EJ4V0UM APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) [A] ADD ... 55 ADDC ... 56 ADDW ... 64 ADJBA ... 83 ADJBS ... 84 AND ... 59 AND1 ... 87 [B] BC ... 108 BF ... 113 BNC ... 109 BNZ ... 111 BR ... 106 BRK ... 97 BT ... 112 BTCLR ... 114 BZ ... 110 [C] CALL ... 94 CALLF ... 95 CALLT ... 96 CLR1 ... 91 [...]

127 User's Manual U12326EJ4V0UM [S] SEL RBn ... 117 SET1 ... 90 STOP ... 122 SUB ... 57 SUBC ... 58 SUBW ... 65 [X] XCH ... 50 XCHW ... 53 XOR ... 61 XOR1 ... 89 APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER)[...]

128 User's Manual U12326EJ4V0UM [MEMO][...]

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