Intel 82801EB инструкция обслуживания

Intel ® 82801EB (ICH5) I/O 82801ER (ICH5R), and 82801DB (ICH4) Controller Hub: AC ’97 PRM Programmers Reference Manual (P RM) April 2003 Docum ent Num ber: 252751-001 R[...]

R 2 AC ’ 97 Programmer’s Reference Manual INFORM ATION I N THIS DOCUM ENT IS PROVI DED IN CONNECTION WITH INTEL ® PRODUCTS. NO LICENSE, EXPRESS O R IM PLI ED, BY ESTOPPEL OR OTHERWISE, TO ANY I NTELL ECTUAL PROPERTY RI GHTS I S GRANTED BY THIS DOCUM ENT. EX CEPT AS PROVI DED I N INTEL’S TERM S AND CONDITI ONS OF SALE FOR SUCH PRODUCTS, I NTE[...]

R AC ’ 97 Programmer’s Reference Manual 3 Contents 1 Introduction ................................................................................................................... ....... 7 1.1 About This Doc um ent ............................................................................................. 7 1.2 Reference Doc um ents and In[...]

R 4 AC ’ 97 Programmer’s Reference Manual 3.6.3.1 Determ ining the Presenc e of Secondar y and Tertiary Codecs................................................................................. 34 3.6.3.2 Determ ining the Presence of a Modem Function ................ 35 3.6.4 Resum e Context Recovery ..............................................[...]

R AC ’ 97 Programmer’s Reference Manual 5 Figures Figure 1. Block Diagram of Platform Chips et with Intel ® ICH5 Component ...................... 13 Figure 2. Intel ® ICH5 AC ’97 Controller Connection to Its Com panion Codecs ................ 14 Figure 3. Generic Form of Buf fer Des criptor ( One Entry in the List) .........................[...]

R 6 AC ’ 97 Programmer’s Reference Manual Revision History Revision Number Description Revisi on Date -001 Initi al Release. April 2003[...]

Introduction R AC ’ 97 Programmer’s Reference Manual 7 1 Introduction 1.1 A bout This Document This docum ent w as prepared to ass ist In dependent Ha rdw are and Soft w are Vendors (IHVs and ISVs) in support ing the Int el ® I/O controller h ub (ICH5) A C ’97 cont roller feature s et. This document also applies to the previous gen eration o[...]

Introduction R 8 AC ’ 97 Programmer’s Reference Manual Device Name Vendor ID Device ID Subsystem Vendor ID Subsystem Device ID Base Class Code Sub-Class Code Prog. Interface Revision ID Bus Number (P CI Addr ) Device Number Function Number Microsoft PNP Device Node ID Intel Desi red Device Description (INF name) Name for: Microsoft Windows* Ope[...]

Introduction R AC ’ 97 Programmer’s Reference Manual 9 Device Name Vendor ID Device ID Subsystem Vendor ID Subsystem Device ID Base Class Code Sub-Class Code Prog. Interface Revision ID Bus Number (P CI Addr ) Device Number Function Number Microsoft PNP Device Node ID Intel Desi red Device Description (INF name) Name for: Microsoft Windows* Ope[...]

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Overv iew R AC ’ 97 Programmer’s Reference Manual 11 2 Overview In thi s docum ent , “ICH 5” stands for I/O C ontroller H ub 5. The ICH5 prov ides an A C ’ 97- compliant controller. Referen ces to the “A C ’97 Component Specification” ref er to the Audio Codec ’97 S pecification , Revision 2.1, Revi sion 2.2, an d Rev ision 2.3. T[...]

Overv iew R 12 AC ’ 97 Programmer’s Reference Manual Table 2. A udio Features Distribution Matrix A C ’97 A udio Controller Features Intel ® ICH Intel ® ICH2 Intel ® ICH3 Intel ® ICH4 Intel ® ICH5 16 bits S tereo PCM Output ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ 16 bits S tereo PCM Input ⌧ ⌧ ?[...]

Overv iew R AC ’ 97 Programmer’s Reference Manual 13 Figure 1. Block Diagram o f Platform Chip set w ith Intel ® ICH5 Component Intel ® ICH5 USB 2.0 (Supports 6 USB ports) System Management (TCO) IDE-Pri mary GPIO SMBus 2.0/ I 2 C IDE-Secondary Power Management PCI Bus ... Clock Generators S L O T S L O T A GP MCH LAN Connect A C’97 Codec(s[...]

Overv iew R 14 AC ’ 97 Programmer’s Reference Manual Figure 2. Intel ® ICH5 A C ’97 Co ntroller Con nection t o Its Compan ion Codecs Intel ® IC H Digital Cont roller Prim ary Codec A C '97/AC '97 2.x/A MC '97 RESET# SDATA_OU T SYNC BIT_CLK SDATA_IN_ 2 SDATA_IN_ 1 SDATA_IN_ 0 A C '97/M C ' 97 2.x/AMC '97 A C &a[...]

Overv iew R AC ’ 97 Programmer’s Reference Manual 15 2.1.2 Dedicated S/P DIF DMA Output Channel The ICH5 controller pro vides a dedicated DMA engine w ith the capability of outputtin g either PCM o r AC-3 d ata to the S/P D IF link fo r p ass-thro ugh to an exter nal CE audio de cod er. T his capability allow s for simu ltaneous output of PCM/A[...]

Overv iew R 16 AC ’ 97 Programmer’s Reference Manual 2.1.5 Second Independent Input DM A Engines The ICH5 continues to provide two sets of input DMA eng ines that allow for the secondary or tertiary codecs to provide recording PCM data streams on the prim ary codec w hile simultaneously providing recording capabilities from the secon dary or te[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R AC ’ 97 Programmer’s Reference Manual 17 3 Intel ® ICH5 AC ’97 Controller Theory of Operation The ICH5 AC ’ 97 digital controller (DC ) interface is an implem entation of the A C-link, w ith additional featu res to support th e transaction and device pow er manag emen t. T he ICH5 AC [...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R 18 AC ’ 97 Programmer’s Reference Manual Drivers can distribute output and input data in appropriate slots associated with available codec(s). For exam ple a 6-chan nel data stream can be separated into three, 2- chann el codec stream s as long as the codecs are program med to decode the a[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R AC ’ 97 Programmer’s Reference Manual 19 Table 4. M od em Registers Device 31 Function 6 Modem Offset Register Defaul t Comments 04h-05h Comm and (COM) 0000h Bit 2: Bus Mast er Enable Bit 0: I/O Spac e Enable 10h-13h Native Audio Mixer Bas e Address 00000001h Addres s in the 64-K I/O s pac[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R 20 AC ’ 97 Programmer’s Reference Manual 3.2 DMA Engines The ICH5 AC ’ 97 controller uses a scatter ga ther m echanism to access mem ory. There are five, 16-bit D MA en gin es for A udio: 2 PCM Stereo In , 2 MIC m ono in, and S/P D IF Out . There is one, 20-bit PC M 2/4/6 chan nel surrou[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R AC ’ 97 Programmer’s Reference Manual 21 Table 6. BD Control and Length (DWORD 1: 04 -07h) Bit Description 31 Interrupt on Completion (IOC) 1= Enable , 0 = Dis able. W hen this it is set, it m eans t he controll er should is sue an int errupt upon com pleti on of this buffer. It s hould al[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R 22 AC ’ 97 Programmer’s Reference Manual The following steps describe the driver initialization pro cess for a single DMA engine. The sam e process sh ould be repeated for each DMA eng ine. 1. Create the bu ffer des criptor list structu r e in non- pageable m emory. 2. Write th e Buffer De[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R AC ’ 97 Programmer’s Reference Manual 23 Table 10. M od em Last Valid Ind ex Modem Last V alid Index (LVI ) I/O A ddress: Line IN MBAR + 05h (MILVI) Line OUT MBAR + 15h (MOLVI), 5. After L VI registers are updated, softw are sets the run bit in the control register to execute th e descript[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R 24 AC ’ 97 Programmer’s Reference Manual // Advance tail to next value tail++; } 3.2.4 Stopping Transfer s There are tw o w ays that DMA transfers can be s topped. 1. By sim p ly turn ing off the Bus Master run/pause bit. This w ill halt the current DMA tran sfer imm ediately. Data in the [...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R AC ’ 97 Programmer’s Reference Manual 25 2. As a result of th e DMA engine reach ing the L ast Valid Index, no fu rther access to m emory, therefore FIFO w ill not drain. This condition is an error if softw a re is not able to update the descriptor list before the DMA engine reach es the L[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R 26 AC ’ 97 Programmer’s Reference Manual 3.4.3 FI FO Organizati on The ICH5 AC ’97 controller su pports 16-bit sam ples on all ch annels except PCM Out , w hich also support s 20-bi t sam ples. Data will be w ritten to the FIFO in sample pairs followin g the order of valid slots in a cha[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R AC ’ 97 Programmer’s Reference Manual 27 Figure 7. Incompatible Implementation of Sample Ra te Conversion with Repeating Slots over Next Frames Frame n Frame n + 1 Frame n + 2 Frame n + 3 CMD DATA MDM CDC RSVD RSVD RSVD RSVD RSVD RSVD I/O Control CMD ADR TAG X X CMD DATA MDM CDC MIC RSVD R[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R 28 AC ’ 97 Programmer’s Reference Manual Table 12. SDM Reg ister Description Bit Ty pe Reset Description 7:6 RW 00 PCM In 2, Microphone I n 2 Data In Line (D21L): W hen t he SE bit is set , thes e bits indicat e which SDATA _IN line shoul d be used by the hardware for decodi ng the input s[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R AC ’ 97 Programmer’s Reference Manual 29 Shadow ing in mem ory is effectiv e as long as the codec itself does not chang e the value of the registers. Theref ore, the statu s of the GPIOs con figu red as inputs on the most recent f rame is accessible to sof tw are by readin g the reg ister [...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R 30 AC ’ 97 Programmer’s Reference Manual 3.6 Pow er Management Power m anagemen t of th e driver/codec interaction requ ires careful sequen cing in the ICH5 A C ’97 environm ent. In the ICH5 AC ’97 environm ent it is possible to have two drivers sharing th e same AC- link interf ace fo[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R AC ’ 97 Programmer’s Reference Manual 31 Conf igu ration 5 is a tw o-codec audio topology . In this con figuration concerns are on th e proper pow er down sequence. How ever, no driver in teraction is expected as only the audio driver execut es po wer management funct ions. Config uration [...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R 32 AC ’ 97 Programmer’s Reference Manual • Mo de m D3 co nfigura tio n is de pe ndent on wake-up on ri ng event e nab le. I f wake-up o n ring i s enab led , GP IO canno t go d own in D3. Note: When a codec section is pow ered back on the Powerdow n Control/Status register (in d ex 26h) [...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R AC ’ 97 Programmer’s Reference Manual 33 Configurati on Numbers 3 to 6: Dual Funct ion Singl e or Dual Codec Configurati ons: Table 16. Po wer St ate M appin g for Audio in Dual Codec Deskt op T ransition PR<0:5> + (EAPD) +12 +5 from +12 +3.3 Digital +3.3 Vaux Digital Commen ts E A P[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R 34 AC ’ 97 Programmer’s Reference Manual Table 17. Po wer St ate M apping for M odem in Dual Codec Deskto p Tran sition PR<A : D> + ML NK (other power control (PRx) bit s do not apply for Intel ® ICH5 implementation) +12 +5 from +12 +3.3 Digital +3.3 Vaux Digital Commen ts Sdata_In [...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R AC ’ 97 Programmer’s Reference Manual 35 3.6.3.2 Determining the Presence of a Modem Function In the case of an AMC config uration, only the primary cod ec ready bit w ill b e indicated. In order to determin e proper pow er dow n conf iguration , the audio driver n eeds to determine the pr[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R 36 AC ’ 97 Programmer’s Reference Manual 3.6.5.1 Primary Audio Request ed to D3 The audio pow er ma nagem ent procedure attemptin g to get th e audio codec to D3 state. If MD3 == true // (sleeping?) { Audio_Power_Manage_Reg = D3 + PR4 + PR5; // yes, sleep plus AC Link down } Else { Audio_P[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R AC ’ 97 Programmer’s Reference Manual 37 3.6.5.4 A udio Primary Request ed to D0 The audio power m anagem ent procedure will attem pt to get the audio codec to D0 state. AD3 = false // set to "audio awake" // Setting the flag first avoid race condition during D3->D0 // transit[...]

Intel® ICH5 AC ’97 Controller Theory of Oper ation R 38 AC ’ 97 Programmer’s Reference Manual A pseudo code representation is as follows: void Link_reset(void) { If Cold_Reset# == True // AC_RESET# asserted, D3 when cold! { Cold_Reset# = False; // De-assert AC_RESET# Wake-up! } Else { Warm_reset = True; // D3 is Hot! Do warm reset } }[...]

Surround Audio Support R AC ’ 97 Programmer’s Reference Manual 39 4 Surround Audio Support The AC ’97 Component Specification allow s for up to six channels of audio supported in the A C- link. The audio dev ice driver m ust determ ine the num ber of audio chann els available in th e codec(s) and properly enable the IC H5 AC ’ 97 controller[...]

Surround Audio Support R 40 AC ’ 97 Programmer’s Reference Manual Table 20. Multiple Codec A udio Channel Distribution Split A udio Codec Configuration Primary Secondary T ertiary Total Channels L/R - - 2 L/R S-L/R - 4 L/R S-L/ R; C/LFE - 6 L/R S-L/R C/LFE 6 Legend: L/R: Lef t St ereo Channel (Slot 3); Right Stereo Channel (S lot 4) S-L/R: Surr[...]

Surround Audio Support R AC ’ 97 Programmer’s Reference Manual 41 Table 22. AC-Link PCM 4/6 -Chann els Enable Bits PCM 4/ 6 Enable: Enables the PCM Output to be in 4 channel or 6-channel mode. PCM Slots Enable : (PCM OUT DMA) S/PDIF Slots Ena ble: (S/PDI F Out DM A ) 00 = 2 channel m ode (default). 3, 4 (L and R) 7, 8 01 = 4 channel m ode. 3, 4[...]

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20-Bits PCM Support R AC ’ 97 Programmer’s Reference Manual 43 5 20-Bits PCM Support The ICH5 A C ’97 con troller prov ides su pport for 16- or 20-bit PCM out. S oftw are can determ ine if 20-bit s amples are s upported in the con troller by reading the s ample capabilities bits in GLOB_STA registers as follows: M BBAR + 30h: Global Status Re[...]

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Independent S-P/DIF Output Capability R AC ’ 97 Programmer’s Reference Manual 45 6 Independent S-P/DIF Output Capability The ICH5 AC ’97 controller provi des an in dependent DMA en gin e for S- P/DIF ou tput th at operates independently of the six ch annels PCM Out stream . T his allows th e S-P/DIF data stream to be independent of the PCM st[...]

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Support for Double Rate Audio R AC ’ 97 Programmer’s Reference Manual 47 7 Support for Double Rate Audio The ICH5 AC’ 97 controller has the capability of supporting a s tereo 96 kHz st ream u sing the AC’ 97 Double Rate Audio (DRA ) support. This capability is en abled by program min g the controller to use four-ch annel m o de, which w ill[...]

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Independent Input Channels Capability R AC ’ 97 Programmer’s Reference Manual 49 8 Independent Input Channels Capability ICH5 AC ’97 controller provides capability for tw o DMA channels dedicated to independent PCM and Microphon e audio stream s. T hese allow improved featu r es that enable application s such as audio m obile dockin g and m i[...]

Independent Input Channels Capability R 50 AC ’ 97 Programmer’s Reference Manual Bit Descripti on 11 Reserved 3 Steer Enabl e (SE): W hen set, the S DATA_I N lines are t reated separat ely and not OR’d t ogether before being sent t o the DMA engines . W hen c leared, the S DATA_I N lines are OR’ d together, and t he “Microphone In 2” an[...]

Intel® ICH5 AC ’ 97 Modem Driver R AC ’ 97 Programmer’s Reference Manual 51 9 Intel ® ICH5 AC ’97 Modem Driver The AC ’97 Component Specification allow s for a m odem codec to be connected to th e AC- link interface. This allow s for the developmen t of a softw are stack that provides modem fun ctionality, i.e. a soft modem . Currently [...]

Intel® ICH5 AC ’97 M odem Driver R 52 AC ’ 97 Programmer’s Reference Manual The first invocation of the h ost based modem task provides an initial buff e r and one or more buff ers of s purious data (h enceforth , spurious buff ers). T he task ch ooses or computes each of th e spurious bu ffer(s) based on s ignal s tate at end of im mediatel[...]

Intel® ICH5 AC ’ 97 Modem Driver R AC ’ 97 Programmer’s Reference Manual 53 while (tail <= Prefetched_Index) { tail++; // Happens IFF Spurious Data was used } if ( ((tail <= LastValidIndex) || (tail == free)) &&(((tail+1) <= LastValidIndex) || ((tail+1) == free)) ) { Descriptor.BufferPtr[tail] = &buffer; Descriptor.Buffe[...]