Intel 8086-2 инструкция обслуживания

September 1990 Order Number: 231455-005 8086 16-BIT HMOS MICROPROCESSOR 8086/8086-2/8086-1 Y Direct Addressing Capability 1 MByte of Memory Y Architecture Designed for Powerful Assembly Language and Efficient High Level Languages Y 14 Word, by 16-Bit Register Set with Symmetrical Operations Y 24 Operand Addressing Modes Y Bit, Byte, Word, and Block[...]

8086 Table 1. Pin Description The following pin function descriptions are for 8086 systems in either minimum or maximum mode. The ‘‘Local Bus’’ in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to additional bus buffers). Symbol Pin No. Type Name and Function AD 15 –A D 0 2 – 16, 39 I/O[...]

8086 Table 1. Pin Description (Continued) Symbol Pin No. Type Name and Function READY 22 I READY: is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The READY signal from memory/IO is synchronized by the 8284A Clock Generator to form READY. This signal is active HIGH. The 8086 READY input is not [...]

8086 Table 1. Pin Description (Continued) Symbol Pin No. Type Name and Function S 2 ,S 1 ,S 0 26 – 28 O These signals float to 3-state OFF in ‘‘hold acknowledge’’. These status lines are encoded as shown. (Continued) S 2 S 1 S 0 Characteristics 0 (LOW) 0 0 Interrupt Acknowledge 0 0 1 Read I/O Port 0 1 0 Write I/O Port 0 1 1 Halt 1 (HIGH) [...]

8086 Table 1. Pin Description (Continued) Symbol Pin No. Type Name and Function QS 1 ,Q S 0 24, 25 O QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue operation is performed. QS 1 and QS 0 provide status to allow external tracking of the internal 8086 instruction queue. QS 1 QS 0 Characteristics 0 (LOW) 0 No Operati[...]

8086 FUNCTIONAL DESCRIPTION General Operation The internal functions of the 8086 processor are partitioned logically into two processing units. The first is the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the block dia- gram of Figure 1. These units can interact directly but for the most part perform as separate a[...]

8086 231455 – 3 Figure 3a. Memory Organization In referencing word data the BIU requires one or two memory cycles depending on whether or not the starting byte of the word is on an even or odd ad- dress, respectively. Consequently, in referencing word operands performance can be optimized by lo- cating data on even address boundaries. This is an [...]

8086 231455 – 5 Figure 4a. Minimum Mode 8086 Typical Configuration 231455 – 6 Figure 4b. Maximum Mode 8086 Typical Configuration 8[...]

8086 can occur between 8086 bus cycles. These are re- ferred to as ‘‘Idle’’ states (T i ) or inactive CLK cycles. The processor uses these cycles for internal house- keeping. During T 1 of any bus cycle the ALE (Address Latch Enable) signal is emitted (by either the processor or the 8288 bus controller, depending on the MN/MX strap). At the[...]

8086 Status bits S 3 through S 7 are multiplexed with high- order address bits and the BHE signal, and are therefore valid during T 2 through T 4 .S 3 and S 4 indi- cate which segment register (see Instruction Set de- scription) was used for this bus cycle in forming the address, according to the following table: S 4 S 3 Characteristics 0 (LOW) 0 A[...]

8086 MASKABLE INTERRUPT (INTR) The 8086 provides a single interrupt request input (INTR) which can be masked internally by software with the resetting of the interrupt enable FLAG status bit. The interrupt request signal is level trig- gered. It is internally synchronized during each clock cycle on the high-going edge of CLK. To be re- sponded to, [...]

8086 EXTERNAL SYNCHRONIZATION VIA TEST As an alternative to the interrupts and general I/O capabilities, the 8086 provides a single software- testable input known as the TEST signal. At any time the program may execute a WAIT instruction. If at that time the TEST signal is inactive (HIGH), pro- gram execution becomes suspended while the proc- essor[...]

8086 lines D 7 –D 0 as supplied by the inerrupt system logic (i.e., 8259A Priority Interrupt Controller). This byte identifies the source (type) of the interrupt. It is multi- plied by four and used as a pointer into an interrupt vector lookup table, as described earlier. BUS TIMINGÐMEDIUM SIZE SYSTEMS For medium size systems the MN/MX pin is co[...]

8086 ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias ÀÀÀÀÀÀ0 § Ct o7 0 § C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65 § Ct o a 150 § C Voltage on Any Pin with Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 1.0V to a 7V Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2.5W NOTICE: This is a production dat[...]

8086 A.C. CHARACTERISTICS (8086: T A e 0 § Ct o7 0 § C, V CC e 5V g 10%) (8086-1: T A e 0 § Ct o7 0 § C, V CC e 5V g 5%) (8086-2: T A e 0 § Ct o7 0 § C, V CC e 5V g 5%) MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS Symbol Parameter 8086 8086-1 8086-2 Units Test Conditions Min Max Min Max Min Max TCLCL CLK Cycle Period 200 500 100 500 125 500 [...]

8086 A.C. CHARACTERISTICS (Continued) TIMING RESPONSES Symbol Parameter 8086 8086-1 8086-2 Units Test Min Max Min Max Min Max Conditions TCLAV Address Valid Delay 10 110 10 50 10 60 ns TCLAX Address Hold Time 10 10 10 ns TCLAZ Address Float TCLAX 80 10 40 TCLAX 50 ns Delay TLHLL ALE Width TCLCH-20 TCLCH-10 TCLCH-10 ns TCLLH ALE Active Delay 80 40 5[...]

8086 A.C. TESTING INPUT, OUTPUT WAVEFORM 231455-11 A.C. Testing: Inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’. Timing measurements are made at 1.5V for both a Logic ‘‘1’’ and ‘‘0’’. A.C. TESTING LOAD CIRCUIT 231455 – 12 C L Includes Jig Capacitance WAVEFORMS MINIMUM MODE 231455 – 13 17[...]

8086 WAVEFORMS (Continued) MINIMUM MODE (Continued) 231455 – 14 SOFTWARE HALTÐ RD, WR, INTA e V OH DT/R e INDETERMINATE NOTES: 1. All signals switch between V OH and V OL unless otherwise specified. 2. RDY is sampled near the end of T 2 ,T 3 ,T W to determine if T W machines states are to be inserted. 3. Two INTA cycles run back-to-back. The 808[...]

8086 A.C. CHARACTERISTICS MAX MODE SYSTEM (USING 8288 BUS CONTROLLER) TIMING REQUIREMENTS Symbol Parameter 8086 8086-1 8086-2 Units Test Min Max Min Max Min Max Conditions TCLCL CLK Cycle Period 200 500 100 500 125 500 ns TCLCH CLK Low Time 118 53 68 ns TCHCL CLK High Time 69 39 44 ns TCH1CH2 CLK Rise Time 10 10 10 ns From 1.0V to 3.5V TCL2CL1 CLK [...]

8086 A.C. CHARACTERISTICS (Continued) TIMING RESPONSES Symbol Parameter 8086 8086-1 8086-2 Units Test Min Max Min Max Min Max Conditions TCLML Command Active 10 35 10 35 10 35 ns Delay (See Note 1) TCLMH Command Inactive 10 35 10 35 10 35 ns Delay (See Note 1) TRYHSH READY Active to 110 45 65 ns Status Passive (See Note 3) TCHSV Status Active Delay[...]

8086 A.C. CHARACTERISTICS (Continued) TIMING RESPONSES (Continued) Symbol Parameter 8086 8086-1 8086-2 Units Test Min Max Min Max Min Max Conditions TRHAV RD Inactive to Next TCLCL-45 TCLCL-35 TCLCL-40 ns Address Active TCHDTL Direction Control 50 50 50 ns C L e 20 – 100 pF for all 8086 Active Delay Outputs (In (Note 1) addition to 8086 TCHDTH Di[...]

8086 WAVEFORMS MAXIMUM MODE 231455 – 15 22[...]

8086 WAVEFORMS (Continued) MAXIMUM MODE (Continued) 231455 – 16 NOTES: 1. All signals switch between V OH and V OL unless otherwise specified. 2. RDY is sampled near the end of T 2 ,T 3 ,T W to determine if T W machines states are to be inserted. 3. Cascade address is valid between first and second INTA cycle. 4. Two INTA cycles run back-to-back.[...]

8086 WAVEFORMS (Continued) ASYNCHRONOUS SIGNAL RECOGNITION 231455 – 17 NOTE: 1. Setup requirements for asynchronous signals only to guarantee recognition at next CLK. BUS LOCK SIGNAL TIMING (MAXIMUM MODE ONLY) 231455 – 18 RESET TIMING 231455 – 19 REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY) 231455 – 20 NOTE: The coprocessor may not dri[...]

8086 WAVEFORMS (Continued) HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY) 231455 – 21 25[...]

8086 Table 2. Instruction Set Summary Mnemonic and Instruction Code Description DATA TRANSFER MOV e Move: 76543210 76543210 76543210 76543210 Register/Memory to/from Register 100010dw m o d r e g r / m Immediate to Register/Memory 1100011w m o d000r / m data data if w e 1 Immediate to Register 1011wr e g data data if w e 1 Memory to Accumulator 101[...]

8086 Table 2. Instruction Set Summary (Continued) Mnemonic and Instruction Code Description ARITHMETIC 76543210 76543210 76543210 76543210 ADD e Add: Reg./Memory with Register to Either 000000dw m o dr e gr / m Immediate to Register/Memory 100000sw m o d000r / m data data if s: w e 01 Immediate to Accumulator 0000010w data data if w e 1 ADC e Add w[...]

8086 Table 2. Instruction Set Summary (Continued) Mnemonic and Instruction Code Description LOGIC 76543210 76543210 76543210 76543210 NOT e Invert 1111011w m o d010r / m SHL/SAL e Shift Logical/Arithmetic Left 110100vw m o d100r / m SHR e Shift Logical Right 110100vw m o d101r / m SAR e Shift Arithmetic Right 110100vw m o d111r / m ROL e Rotate Lef[...]

8086 Table 2. Instruction Set Summary (Continued) Mnemonic and Instruction Code Description JMP e Unconditional Jump: 76543210 76543210 76543210 Direct within Segment 11101001 disp-low disp-high Direct within Segment-Short 11101011 disp Indirect within Segment 11111111 m o d100r / m Direct Intersegment 11101010 offset-low offset-high seg-low seg-hi[...]

8086 Table 2. Instruction Set Summary (Continued) Mnemonic and Instruction Code Description 76543210 76543210 PROCESSOR CONTROL CLC e Clear Carry 11111000 CMC e Complement Carry 11110101 STC e Set Carry 11111001 CLD e Clear Direction 11111100 STD e Set Direction 11111101 CLI e Clear Interrupt 11111010 STI e Set Interrupt 11111011 HLT e Halt 1111010[...]