Epson ARM720T инструкция обслуживания

ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU MANUAL EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION http://www.epsondevice.com Issue April, 2004 Printed in Japan C A Document code: 405003400 CORE CPU MANUAL ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU MANUAL ARM720T Revision 4 (AMBA AHB Bus Int[...]

NO TICE No part of this material may be reproduced or duplicated in any form or by any means without the written permis- sion of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its a[...]

Preface 1 Introduction 2 Programmer ’ s Model 3 Configuration 4 Instruction and Dat a Cache 5W r i t e B u f f e r 6 The Bus Interface 7 Memory Management Unit 8 Coprocessor Interface 9 Debugging Y our System 10 ETM Interface 1 1 T est Support A Signal Descriptions Glossary Index[...]

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CONTENTS A R M 720T CORE CPU MANUAL EPSON i Contents Preface About this document ......... ............................................................................. .......... xi 1 Introduction 1.1 About the ARM720T pr ocessor .................. ............................ ............ ....... 1-1 1.2 Coprocessors .......................... ..[...]

CONTENTS ii EPSON ARM720T CORE CPU MANUAL 6.9 Reset .............. ................................. ........................................................ 6-13 7 Memory Management Unit 7.1 About the MMU ........... ............................ .......................................... ......... 7-1 7.2 MMU program-accessible regist ers ........[...]

CONTENTS ARM720T CORE CPU MANUAL EPSON i ii 10 ETM Interface 10.1 About the ETM interface ...... ............................................ ........................ 10-1 10.2 Enabling and disabl ing the ETM7 interfac e . ............................................ 10-1 10.3 Connections between the ETM7 macrocell and the ARM720T processor . .....[...]

CONTENTS iv EPSON ARM720T CORE CPU MANUAL List of Figures Figure 1-1 720T Block diagram ............ ............................................................... ......... 1-2 Figure 1-2 ARM720T processor functional signals ...... .......................................... ....... 1-3 Figure 1-3 ARM instruction set format s .................. ..[...]

CONTENTS ARM720T CORE CPU MANUAL EPSON v Figure 9-4 Clock synchronization ...... .................................................................. ......... 9-8 Figure 9-5 The ARM720T core, TAP contro ller, and EmbeddedICE-RT macrocell ... 9-10 Figure 9-6 Domain Access Control R egister ................. ................................. .........[...]

CONTENTS v i EPSON ARM720T CORE CPU MANUAL List of Tables Table 1-1 Key to tables ...... ................................................. ............................... ......... 1-6 Table 1-2 ARM instruction summary ... ............................................................... ......... 1-8 Table 1-3 Addressing mode 2 .......... ..........[...]

CONTENTS ARM720T CORE CPU MANUAL EPSON vii Table 9-7 Determining the cause of entry to debug state .......... ........................ ....... 9-32 Table 9-8 SIZE[1:0] signal encoding .. ............................................................. .......... 9-35 Table 9-9 Debug control regi ster bit assignments ... .............. ............... [...]

CONTENTS viii EPSON ARM DD I 0229B THIS P AG E IS B LANK.[...]

Preface[...]

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Preface ARM720T CORE CPU MANUAL EPSON xi Preface This preface introduces the ARM720T Revision 4 (AMBA AHB Bus Interface V ersion) CORE CPU Manual . It contains the following sectio ns: About this document ............... ..................... ..................... ..................... ................... xi About this document This document is a t[...]

Preface xii EPSON ARM720T CORE CPU MANUAL Chapter 8 Coprocessor Interface Read this chapter for a descriptio n on how to connect coprocessors to the ARM1 156F-S coprocessor interface. Chapter 9 Debugging Y our System Read this chapter for a descriptio n of the hardware extensions and integrated on-chip debug support for the ARM720T processor . Chap[...]

Preface ARM720T CORE CPU MANUAL EPSON x iii Timing diagram conventions This manual contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labeled when they occur . Therefore, no additional meaning must be attached unless specifically stated. Key to timing diagram convention[...]

Preface xiv EPSON ARM720T CORE CPU MANUAL THIS P AGE IS BLANK.[...]

1 Introduction[...]

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1: Introduction ARM720T CORE CPU MANUAL EPSON 1-1 1 Introduction This chapter provides an introduction to the ARM720T processor . It contains the following sections: 1.1 About the ARM720T processor ................ ......................... ..................... .... 1-1 1.2 Coprocessors ........................ ..................... ..............[...]

1: Introduction 1-2 EPSON ARM720T CORE CPU MANUAL A block diagram of the ARM720T processor is shown in Figure 1-1. Figure 1-1 720T Blo ck diagram MMU D ata and addres s b u ffe r s AM B A in t e r f ac e 8KB c ac he C ontrol and c l oc k i ng l ogic A R M 720T c ore Sy s tem c ontr ol c opr oc es s or V i rtual addr es s bus AM B A AH B bus i nterf[...]

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-3 The functional signals on the ARM720T processor are shown in Figure 1-2. Figure 1-2 ARM720T p rocessor functional signals 1.1.1 EmbeddedICE-RT logic The EmbeddedICE-RT logic provides integrated on-chip debug support for the ARM720T core. It enables you to program the conditions under which a breakpo[...]

1: Introduction 1-4 EPSON ARM720T CORE CPU MANUAL Changes to the programmer ’ s model T o prov ide support for the EmbeddedICE-RT macro cell, the following changes have been made to the programmer ’ s model for the ARM720T processor: Debug Control Register There are two new bits in the Debug Control Register: Bit 4 Monitor mode enable. Use this[...]

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-5 1.2 Coprocessors The ARM720T processor has an in ternal coprocessor designated CP15 for internal control of the device (see Chapter 3 Configuration ). The ARM720T processor also includes a port for the connection of on-chip external coprocessors. This enables extension of the ARM720T functionality i[...]

1: Introduction 1-6 EPSON ARM720T CORE CPU MANUAL 1.3.1 Format summary This section provides a summary of the ARM and Thumb instruction sets: • ARM instruction set on page 1-7 • Thumb instruction set on page 1-14 A key to the instructio n set tables is shown in T able 1-1. The ARM7TDMI-S core on the ARM720T processor is an implementation of the[...]

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-7 1.3.2 ARM instruction set This section gives an overview of the ARM inst ructions available. For full details of these instructions, see the ARM Architecture Reference Manual . The ARM instruction set formats are shown in Figure 1-3. Figure 1-3 ARM instructio n se t forma ts Note: Some instruction c[...]

1: Introduction 1-8 EPSON ARM720T CORE CPU MANUAL The ARM instruction set summa ry is shown in T able 1-2. T able 1-2 ARM instru ctio n su mm ary Operation Assembler Move Move MOV{cond}{S} <Rd>, <Oprnd2> Move NOT MVN{cond}{S} <Rd>, <Oprnd2> Move SPSR to regist er MRS{cond} <Rd>, SPSR Move CPSR to regist er MRS{cond} &l[...]

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-9 Load Word LDR{cond} <Rd>, <a_mode2> Word with User Mode privilege LDR{cond}T <Rd>, <a_mode2P> Byte LDR{cond}B <Rd>, <a_mode2> Byte with User Mod e privilege LDR{cond}BT <Rd>, <a_mode 2P> Byte signed LDR{cond}SB <Rd>, <a_mode 3> Halfword LDR[...]

1: Introduction 1-10 EPSON ARM720T CORE CPU MANUAL Addressing mode 2, <a_mode2> , is shown in T able 1-3. Coprocessors Data operations CDP{cond} p<cpnum>, <op1>, <CRd>, <CRn>, <CRm>, <op2> Move to ARM reg from coproc MRC{cond} p<cpnum>, <op1>, <Rd>, <CRn> , <CRm>, <op2> M[...]

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-11 Addressing mode 2 (privileged), <a_mode2P> , is shown in T able 1-4. Addressing mode 3 (signed byte, and halfword data transfer), <a_mode3> , is shown in Ta b l e 1 - 5 . Addressing mode 4 (load), <a_mode4L> , is shown in T able 1-6. T able 1-4 Ad dressing mode 2 (privileg ed) Ope[...]

1: Introduction 1-12 EPSON ARM720T CORE CPU MANUAL Addressing mode 4 (store), <a_mod e4S> , is shown in T a ble 1-7. Addressing mode 5 (copro cessor data tra nsfer), <a_mode5> , is shown in T able 1-8. Operand 2, <Oprnd2> , is shown in T able 1-9. Fields, {field} , are shown in T able 1-10. T able 1-7 Addre ssing mode 4 (store) Ad[...]

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-13 Condition fields, {cond} , are shown in T able 1-1 1. T able 1-1 1 Co ndition fields Suffix Description Condition(s) EQ Equal Z set NE Not equal Z clear CS Unsigned higher, or same C set CC Unsigned lower C clear MI Negative N set PL Positive, or zero N clear VS Overflow V set VC No overflow V clea[...]

1: Introduction 1-14 EPSON ARM720T CORE CPU MANUAL 1.3.3 Thumb instruction set This section gives an overview of the Thumb inst ructions available. For full details of these instructions, see the ARM Architecture Reference Manual . The Thumb instruction set formats are shown in Figure 1-4. Figure 1-4 Thum b instruction set forma ts 15 14 13 12 11 1[...]

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-15 The Thumb instruction set summa ry is shown in T able 1-12. T able 1-12 Th umb inst ruction summ ary Operation Assembler Move Immediate MOV <Rd>, #<8bit_Imm> High to Low MOV <Rd>, <Hs> Low to High MOV <Hd>, <Rs> High to High MOV <H d>, <Hs> Arithmetic[...]

1: Introduction 1-16 EPSON ARM720T CORE CPU MANUAL Shift/Rotate Logical shift left LSL <Rd>, <Rs>, #<5bit_shift_imm> LSL <Rd>, <Rs> Logical shift right LSR <Rd>, <Rs>, #<5bit_shift_imm> LSR <Rd>, <Rs> Arithmetic shift right ASR <Rd>, <Rs>, #<5bit_shift_imm> ASR <Rd>[...]

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-17 Note: All thumb fetches are done as 32-b it bus transactions using the 32-bit thumb prefetch buffer. Load With register offset word LD R <Rd> , [<Rb>, <Ro>] halfword LDRH <R d>, [<Rb>, <Ro>] signed halfword LDRSH <Rd>, [<Rb> , <Ro>] byte LDRB &l[...]

1: Introduction 1-18 EPSON ARM720T CORE CPU MANUAL 1.4 Silicon revisions This manual is for revision r4p2 of the ARM720T macrocell. See Product revision status on page xii for details of revision numbering. There are no functional differences from previous revisions.[...]

2 Programmer’s Model[...]

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2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-1 2 Programmer ’ s Model This chapter describes the programmer ’ s model for the ARM720T processor . It contains the following sectio ns: 2.1 Processor operating states .......... ..................... ..................... ..................... 2-1 2.2 Memory formats ......... ...........[...]

2: Programmer’s Model 2-2 EPSON ARM720T CORE CPU MANUAL 2.2 Memory format s The ARM720T processor views memory as a line ar collection of bytes numbered upwards from zero, as follows: Bytes 0 to 3 Hold the first stored word. Bytes 4 to 7 Hold the second stored word. Bytes 8 to 1 1 Hold the third stored word. W ords are stored in me mory as big or[...]

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-3 2.2.2 Little-endian format In little-endian format, the lowest numbered byte in a word is considered the least signi ficant byte of the word, and the highest numbered byte the most significa nt. Byte 0 of the memory system is t herefore connect ed to data lines 7 to 0. Little-endian format i[...]

2: Programmer’s Model 2-4 EPSON ARM720T CORE CPU MANUAL 2.5 Operating modes The ARM720T processor supports seven modes of operation, as shown in T able 2-1. 2.5.1 Changing operating modes Mode changes can be made under software contro l, by external interrupts or during exception processing. Most application pr ograms execute in User mode. The no[...]

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-5 Interrupt modes FIQ mode has seven banked registers mapped to r8-14 (r8_fiq-r14_fiq). In ARM state, many FIQ handlers can use these banked registers to av oid having to save any registers onto a stack. User , IRQ, Supervisor , Abort, and Undefined modes each have two banked registers, mapped[...]

2: Programmer’s Model 2-6 EPSON ARM720T CORE CPU MANUAL 2.6.2 The Thumb st ate register set The Thumb state register set is a subset of th e ARM state set. Y ou have direct access to: • eight general registers, (r0–r7) •t h e P C •a Stack Pointer (SP) register •a Link Register (LR) •t h e C P S R . There are banked SPs, LRs, and Saved[...]

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-7 2.6.3 The relationship between ARM and Thumb st ate registers The Thumb st ate registers re late to the A R M state registers in the following ways: • Thumb state r0– r7, and ARM state r0–r7 are identical • Thumb state CPSR and SPSR s, and ARM state CPSR and SPSRs are identical • T[...]

2: Programmer’s Model 2-8 EPSON ARM720T CORE CPU MANUAL 2.7 Program st atus registers The ARM720T processor contains a CPSR, and five SPSRs for use by exception handlers. These regist ers : • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operating mode[...]

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-9 2.7.3 Reserved bit s The remaining bits in the PSRs are reserved. When changing flag or control bits of a PSR, you must ensure that these unused bits are not altere d. Also, your program must not rely on them containing specific values, because in future processors they might read as one or [...]

2: Programmer’s Model 2-10 EPSON ARM720T CORE CPU MANUAL 2.8 Exceptions Exceptions arise whenever the normal flow of a program has to be halted temporarily , for example to service an interrupt from a periphe ral. Before an exception can be handled, the current processo r state is preserved so that th e original program can resume when the handle[...]

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-11 2.8.2 Action on leav ing an exception On completion, the exception handler: 1 Moves the LR, minus an offset where appropriate, to the PC. The offset varies depending on the type of exception. 2 Copies the SPSR back to the CPSR. 3 Clears the interrupt di sabl e fl ags , if they were set on e[...]

2: Programmer’s Model 2-12 EPSON ARM720T CORE CPU MANUAL 2.8.4 Fast interrupt request The FIQ exception is used for most performance-critical interrupts in a system. In ARM state the processor has sufficient private registers to remove the necessity for register saving, minimizing the overhead of context switching. FIQ is externally generated by [...]

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-13 After fixing the reason for the abort, the handler must execute the following irrespective of the processor state (ARM or Thumb): SUBS PC, r14_abt, #4 for a Prefetch Abort SUBS PC, r14_abt, #8 for a Data Abort This restores both the PC and the CPSR, and retries the aborted instruction. Note[...]

2: Programmer’s Model 2-14 EPSON ARM720T CORE CPU MANUAL 2.8.10 Exception priorities When multiple exceptions arise at the same time , a fixed priority system determines the order in which they are handled: 1 Reset (highest priority). 2 Data Abort. 3F I Q . 4I R Q . 5P r e f e t c h A b o r t . 6 Undefined Instruction, SWI (lowest priority). 2.8.[...]

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-15 2.9 Relocation of low virtual addresses by the FCSE PID The ARM720T processor provides a mechanism, Fast Context Switch Extension (FCSE), to translate virtual addresses to physical addres ses based on the current value of the FCSE Process IDentifier (PID). The virtual address produced by th[...]

2: Programmer’s Model 2-16 EPSON ARM720T CORE CPU MANUAL 2.10 Reset When the HRESETn signal goes LOW , the ARM72 0T processor: 1 Abandons the executing instruction. 2 Flushes the cache and Translation Lookaside Buffer (TLB). 3 Disables the Write Buffer (WB), cache, and MMU. 4 Resets t he FCSE PID. 5 Continues to fetch instructions from incrementi[...]

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-17 2.1 1 Implement ation-defined behavior of instructions The ARM Architecture Reference Manual defines the instruction set of the ARM720T processor: • See Indexed addressing on a Data Abort for the behavior of instructions that are identified as implementation-defined in the ARM Architectur[...]

2: Programmer’s Model 2-18 EPSON ARM720T CORE CPU MANUAL THIS P AGE IS BLANK.[...]

3 Configuration[...]

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3: Configuration ARM720T CORE CPU MANUAL EPSON 3-1 3 Configuration This chapter describes the configuration of the ARM720T processor . It contains the following sections. 3.1 About configuration .... ..................... ..................... ................. ..................... 3-1 3.2 Internal coprocessor instructions ................ .......[...]

3: Configuration 3-2 EPSON ARM720T CORE CPU MANUAL 3.2 Internal coprocessor instructions The instruction set for the ARM720T processo r enables yo u to implement specialized additional instructions using coprocessors. Th ese are separate processing units that are coupled to the ARM720T processor , although CP15 is built into the ARM720T processor .[...]

3: Configuration ARM720T CORE CPU MANUAL EPSON 3-3 3.3 Registers The ARM720T processor contains registers that control the cache and MMU operation. Y ou can access these registers using MCR and MRC in structions to CP15 with the processor in a privileged mode. T able 3 -1 shows a summary of valid CP15 registers. Y ou must not attempt to read from, [...]

3: Configuration 3-4 EPSON ARM720T CORE CPU MANUAL 3.3.2 Control Register Reading from CP15 Register 1 reads the control bits. The CRm and opcode_2 fields Should Be Zero when reading CP15 Register 1. Control Register read format is shown in Figure 3-4. Figure 3-4 Control Re gister read format W riting to CP15 Register 1 se ts the control bits . The[...]

3: Configuration ARM720T CORE CPU MANUAL EPSON 3-5 Bits 12:10 When read, this returns an Unpredictable value. When written, it Should Be Zero, or a value read from these bits on the same processor . Note: Using a read-write-modify sequence when modifying this register provides the greatest future compatibility. V Bit 13 Location of exception vector[...]

3: Configuration 3-6 EPSON ARM720T CORE CPU MANUAL 3.3.4 Domain Access Control Register Reading from CP15 Register 3 returns the value of the Domain Access Control Register . W riting to CP15 Register 3 writes the value of the Domain Access Control Register . The Domain Access Contro l Register consists of 16 2-bit fields, each of which defines the[...]

3: Configuration ARM720T CORE CPU MANUAL EPSON 3-7 3.3.6 Fault Address Register Reading CP15 Register 6 returns the value of the Fault Address Register (F AR). The F AR holds the virtual address of the access that wa s attempted when a fault occurred. The F AR is only updated on data faults. There is no update on prefetch faults. W rit ing to CP15 [...]

3: Configuration 3-8 EPSON ARM720T CORE CPU MANUAL In the instructions shown in T able 3-3, c7 is the preferred value for the CRn field, because it indicates a unified MMU. Reading from CP15 Register 8 is undefined. The Invalidate TLB single entry function in validates any TLB entry corresponding to the Modified V irtual Address (MV A) given in Rd [...]

3: Configuration ARM720T CORE CPU MANUAL EPSON 3-9 3.3.10 Register 14, reserved Accessing this register is undefined. W riting to Register 14 is Undefined. 3.3.1 1 T est Register The CP15 Register 15 is used for device-speci fic test operations. For more information, see Chapter 1 1 T est Support .[...]

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4 Instruction and Data Cache[...]

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4: Instruction and Data Cache ARM720T CORE CPU MANUAL EPSON 4-1 4 Instruction and Dat a Cache This chapter describes the instruction and data cache. It contains the following sections: 4.1 About the instruction and data cache ............. ..................... ..................... 4-1 4.2 IDC validity ............ ..................... ..........[...]

4: Instruction and Data Cache 4-2 EPSON ARM720T CORE CPU MANUAL 4.1.3 Read-lock-write The IDC treats the read-lock-writ e instruction as a special case: Read phase Always forces a read of external memory , regardless of whether the data is contained in the cache. Wr i t e p h a s e Is treated as a normal write operat ion. If the data is already in [...]

5 Write Buffer[...]

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5: Write Buffer ARM720T CORE CPU MANUAL EPSON 5-1 5 W rite Buffer This chapter describes the write buffer . It contains the following sections: 5.1 About the write buffer ................. ..................... ..................... ..................... 5-1 5.2 W rite buffer operation ......... .... .... .... ..... .... .... .... .... ..... .... .[...]

5: Write Buffer 5-2 EPSON ARM720T CORE CPU MANUAL 5.2 W rite buffer operation Y ou control the operation of the write buffer with CP15 register 1, the Control Register (see Control Regi ste r on page 3-4). When the CPU performs a write operation, the translation entry for that address is inspected and the stat e of the B bit determines the subseque[...]

6 The Bus Interface[...]

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6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-1 6 The Bus Interface This chapter describes the signals on the bus interface of the ARM720T processor . It contains the following sections: 6.1 About the bus interface ............... ..................... ..................... ..................... 6-1 6.2 Bus interface signals ................[...]

6: The Bus Interface 6-2 EPSON ARM720T CORE CPU MANUAL Figure 6-1 shows a transfer with no wait states (this is the simplest type of transfer). Figure 6-1 Simple AHB transfer A granted bus master starts an AHB transfer by driving the address and control signals. These signals provide the following information about the transfer: • address •d i [...]

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-3 6.2 Bus interface signals The signals in the ARM720T processor bus in terface can be grouped into the following categories: T r ansfer type HTRANS[1:0] See Tr a n s f e r t y p e s on page 6-5. Address and control HADDR[31:0] HWRITE HSIZE[2: 0] HBURST[2:0] HPROT[3:0] See Address and control sig[...]

6: The Bus Interface 6-4 EPSON ARM720T CORE CPU MANUAL The AHB bus master interface signals are shown in Figure 6-2. Figure 6-2 AHB bus master i nterface AH B m a st e r HBUS REQ HL O C K HRE A DY HRE S E T n HW RI T E HC L KEN HC L K HT RA NS [ 1 :0 ] HRDA T A [ 3 1 :0 ] H WD AT A [31: 0] HP RO T [ 3 :0 ] HBURS T [ 2 :0 ] H SI Z E [2: 0] HA DDR[ 3[...]

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-5 6.3 T ransfer types The ARM720T processor bus interface is pipe lined, so the address-class signals and the memory request signals are broadcast in the bus cycle ahead of the bus cycle to which they refer . This gives the ma ximum ti me for a me mo ry cycle to decode the address and respond to [...]

6: The Bus Interface 6-6 EPSON ARM720T CORE CPU MANUAL Figure 6-4 shows some examples of different transfer types. Figure 6-4 Transf er type examples In Figure 6-4: • The first transfer is the start of a burst and is therefore nonsequential. • The master performs the second transfer of the burst immediately. • The master performs the third tr[...]

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-7 6.4 Address and control signals The address and control signals are de scribed in the following sections: • HADDR[31:0] • HWRITE • HSIZE[2:0] • HBURST[2:0] on page 6-8 • HPROT[3:0] on page 6-8. 6.4.1 HADDR[31:0] HADDR[31:0] is the 32-bit address bus that spec ifies the address for the[...]

6: The Bus Interface 6-8 EPSON ARM720T CORE CPU MANUAL 6.4.4 HBURST[2:0] HBURST[2:0] indicates the type of burst generate d by the ARM7 20T core, as shown in Ta b l e 6 - 3 . For more details of burst operation, see the AMBA Specification (Rev 2.0) . 6.4.5 HPROT[3:0] HPROT[3:0] is the protection control bus. These si gnals provide additional inform[...]

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-9 6.5 Slave transfer response signals After a master has started a transfer , the slave determines how the transfer progresses. No provision is made in the AHB specif ication for a bus master to cancel a transfer after it has begun. Whenever a slave is accessed it must provide a response using th[...]

6: The Bus Interface 6-10 EPSON ARM720T CORE CPU MANUAL 6.5.2 HRESP[1:0] HRESP[1:0] is used by the slave to show the status of a t ransfer . The HRESP[1:0] encodings are shown in T a ble 6-5. For a full description of the slave transfer responses, see the AMBA Specification (Rev 2.0) . 6.6 Dat a buses T o enable you to implement an AHB system witho[...]

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-11 6.6.2 HRDA T A[31:0] The read data bus is driven by the approp riate sl ave during read transfer s. If the slave extends the read transfer by holding HREADY LOW , the slave has to provide valid data only at the end of the final cycle of the transfer , as indicated by HREADY HIGH. For transfers[...]

6: The Bus Interface 6-12 EPSON ARM720T CORE CPU MANUAL T a ble 6-7 shows active byte lanes for big-endian systems. 6.7 Arbitration The arbitration mechanism is describe d fully in the AMBA Specific ation (Rev 2.0) . This mechanism is used to ensure that only one mast er has access to the bus at any one time. The arbiter performs this function by o[...]

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-13 6.8 Bus clocking There are two clock inputs on the ARM720T processor bus interface. 6.8.1 HCLK The bus is clocked by the system clock, HCLK . This clock times all bus transfers. All signal timings are related to the rising edge of HCLK . 6.8.2 HCLKEN HCLK is enabled by t he HCLKEN signal. Y ou[...]

6: The Bus Interface 6-14 EPSON ARM720T CORE CPU MANUAL THIS P AGE IS BLANK.[...]

7 Memory Management Unit[...]

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7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-1 7 Memory Management Unit This chapter describes the Memory Management Unit (MMU). It contains the following sections: 7.1 About the MMU ............... ..................... ..................... ..................... ............ 7-1 7.2 MMU program-accessible register s ......... .......[...]

7: Memory Management Un it 7-2 EPSON ARM720T CORE CPU MANUAL 7.1.1 Access permissions and domains For large and small pages, access permissions are defined for each su bpage (4KB for small pages, 16KB for large pages). Se ctions and tiny pages have a si ngle set of access permissions. All regions of memory have an associated do main. A domain is th[...]

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-3 7.2 MMU program-accessible registers T able 7 -1 lists the CP15 registers that are used in conjunction with page table descriptors stored in memory to determine the operation of the MMU. All the CP15 MMU registers, except register c8, contain state. Y ou can read them using MRC instruction[...]

7: Memory Management Un it 7-4 EPSON ARM720T CORE CPU MANUAL 7.3 Address tr anslation The MMU translates V As generated by the CPU co re, and by CP15 regist er c13, into physical addresses to access external me mory . It also derives and checks the access permission, using the TLB. The MMU table walking hardware is used to add entrie s to the TLB. [...]

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-5 The translation ta ble has up to 40 96 x 32-bit en tries, each describing 1MB of virtual memory . This enables up to 4GB of virtual memory to be addressed. Figure 7-2 shows the table walk process. Figure 7-2 Translat in g page tables T ranslation table 4096 entries TTB base Indexed by modi[...]

7: Memory Management Un it 7-6 EPSON ARM720T CORE CPU MANUAL 7.3.2 Level one fetch Bits [31:14] of the T ranslation T able Base Register ar e concatenated with bits [31:20] of the MV A to produce a 30-bit addr ess as shown in Figure 7-3. Figure 7-3 Accessing translation table le vel one descriptors This address selects a 4-byte translation table en[...]

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-7 Level one descriptor bit assignments are shown in T able 7-2. The two least significant bits of the level one de scriptor indicate the de scriptor type as shown in T able 7-3. T able 7-2 Level one descriptor bits Bits Description Section C oarse Fine 31:20 31:10 31:12 These bits form the c[...]

7: Memory Management Un it 7-8 EPSON ARM720T CORE CPU MANUAL 7.3.4 Section descriptor A section descriptor provides th e base address of a 1MB block of memory . Figure 7-5 shows the format of a section descriptor . Figure 7-5 Section de scriptor Section descriptor bit assignme nts are described in T able 7 -4. 7.3.5 Coarse p age t able descriptor A[...]

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-9 Coarse page table descriptor bit a ssignments are described in T a ble 7-5. 7.3.6 Fine p age t able descriptor A fine page table descriptor provides the base address of a page table that contains level two descriptors for large page, small page, or tiny page accesses. Fine pa ge tables hav[...]

7: Memory Management Un it 7-10 EPSON ARM720T CORE CPU MANUAL 7.3.7 T ranslating section references Figure 7-8 shows the complete section translation sequence. Figure 7-8 Section translat io n Note: You must check access permissions contai ned in the level one descriptor before generating the physical address. 7.3.8 Level two descriptor If the leve[...]

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-11 A level two descriptor defines a tiny , a small, or a large page descriptor , or is invalid: • a large page descriptor provides the base address of a 6 4KB block of me mory • a small page descriptor provides the base address of a 4KB block of memory • a tiny page descriptor provides[...]

7: Memory Management Un it 7-12 EPSON ARM720T CORE CPU MANUAL 7.3.9 T ranslating la rge p age references Figure 7-10 shows the comp lete translation sequence for a 64KB large page. Figure 7-10 Large pa ge translation from a coarse page table Because the upper four bits of the page index and low-order four bits of the coarse page table index overlap[...]

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-13 7.3.10 T ranslating sm all page references Figure 7-1 1 shows the complete transl ation sequence for a 4KB small page. Figure 7-11 Small page tr anslation from a coarse page table If a small page descriptor is in cluded in a fine page table, the upper two bits of the page index and low-or[...]

7: Memory Management Un it 7-14 EPSON ARM720T CORE CPU MANUAL 7.3.1 1 T ranslating tiny p age references Figure 7-12 shows the complete transl ation sequence for a 1KB tiny page. Figure 7-12 Tiny page t ranslation from a fine page ta ble Page translation involves one additional step beyond that of a section translation. The level one descriptor is [...]

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-15 7.4 MMU fault s and CPU abort s The MMU generat es an abo rt on the following types of faults: • alignment faults (data accesses only) • translation faults • domain faults • permission faults. In addition, an external abort can be raised by the external system. This can happen onl[...]

7: Memory Management Un it 7-16 EPSON ARM720T CORE CPU MANUAL 7.5 Fault address and fault st atus registers On an abort, the MMU places an encoded 4-b it value, FS[3:0], along with the 4-bit encoded domain number , in the da ta FSR, and the MV A associated with the abort is latched int o the F AR. If an access violation simultaneously genera tes mo[...]

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-17 7.6 Domain access control MMU accesses are primarily controlled through the use of domains. There are 16 domains and each has a 2-bit field to define access to it . T w o types of user are supported, clients and managers. The domains are define d in the Domain Access Control Register . Fi[...]

7: Memory Management Un it 7-18 EPSON ARM720T CORE CPU MANUAL T able 7-10 shows how to interpret the Access Permission (AP) bits and how their interpretation is dependent on the S and R bits (control register bits 8 and 9). T able 7-1 1 Interpreting ac cess permission (AP) bit s AP S R Supervisor permissions User permissions Description b00 0 0 N o[...]

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-19 7.7 Fault checking sequence The sequence the MMU uses to check for access faults is different for se ctions and pages. The sequence for both types of access is shown in Figure 7-14. Figure 7-14 Se quence for checking faults The conditions that generate each of the faults are described in:[...]

7: Memory Management Un it 7-20 EPSON ARM720T CORE CPU MANUAL 7.7.2 T ranslation fault There are two types of translation fault: Section A section translation fault is genera ted if the level one descriptor is marked as invalid. This happens if bits [1:0] of the descriptor are both 0. Page A page translation fault is generate d if the level two des[...]

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-21 7.8 External aborts In addition to the MMU-ge nerated aborts, the ARM72 0T processor can be externally abor ted by the AMBA bus. This can be us ed to flag an error on an ex ternal memory access. However , not all accesses can be aborted in this way and the Bus Interface Unit (BIU) ignores[...]

7: Memory Management Un it 7-22 EPSON ARM720T CORE CPU MANUAL THIS P AGE IS BLANK.[...]

8 Coprocessor Interface[...]

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8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-1 8 Coprocessor Interface This chapter describes the coprocessor interfac e on the ARM720T processor . It contains the following sectio ns: 8.1 About coprocessors ...................... ..................... ..................... ..................... 8-1 8.2 Coprocessor interface signals ...[...]

8: Coprocessor Interface 8-2 EPSON ARM720T CORE CPU MANUAL The coprocessor: 1 Decodes instructions to determ ine whether it can accept the instruction. 2 Indicates whether it can accept the instruction (by signaling on EXTCP A and EXTCPB ). 3 Fetches any values required from its own register bank. 4 Performs the operation required by the instructio[...]

8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-3 8.2 Coprocessor interface signals The signals used to interface the ARM72 0T co re to a coprocessor are grouped into four categories. The clock and clock control signals include the main processor clock and bus reset: •H C L K •E X T C P C L K E N • HRESETn. The pipeline-following sig[...]

8: Coprocessor Interface 8-4 EPSON ARM720T CORE CPU MANUAL 8.3 Pipeline-following signals Every coprocessor in the system must contain a pipeline follower to track the instructions executing in the ARM720T processor pipeline . The coprocessors connect to the ARM720T processor input data bus, EXTCPDOUT[31:0] , over which instructions are fetched, an[...]

8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-5 8.4 Coprocessor interface handshaking The ARM720T core and any coprocessors in the system perform a handshake using the signals shown in T able 8-2. These signals are explained in more detail in Coprocessor signaling on page 8-6. 8.4.1 The coprocessor The coprocessor decodes the instruction[...]

8: Coprocessor Interface 8-6 EPSON ARM720T CORE CPU MANUAL 8.4.3 Coprocessor signaling The coprocessor signals as follows: Coprocessor absent If a coprocessor cannot accept the instruction currently in Decode it must leave EXTCP A and EXTCPB both HIGH. Coprocessor present If a coprocessor can accept an instruction, and can start that instruction im[...]

8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-7 8.4.5 Coprocessor register transfer instructions The coprocessor register transfer instructions, MCR and MRC, transfer data between a register in the ARM720T processor register bank and a register in the coprocessor register bank. An example sequence for a coprocessor register transfer is s[...]

8: Coprocessor Interface 8-8 EPSON ARM720T CORE CPU MANUAL 8.4.7 Coprocessor load and store operations The coprocessor load and store instructions, LDC and STC, are used to transfer data betwee n a coprocessor and memory . They can be used to transfer either a single word of data or a number of the coprocessor registers. There is no limit to the nu[...]

8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-9 8.5 Connecting coprocessors A coprocessor in a system based on an ARM720T processor must have 32-bit connections to: • transfer data from memory (instruction stream and LDC) • write data from the ARM720T processor (MCR) • read data to the ARM720T processor (MRC). 8.5.1 Connecting a si[...]

8: Coprocessor Interface 8-10 EPSON ARM720T CORE CPU MANUAL 8.6 Not using an external coprocessor If you are implem enting a system tha t does no t include any external coprocessors, you must tie both EXTCP A and EXTCPB HIGH. This indicates that no external coprocessors are present in the system. If any coprocessor instructions are received, they t[...]

9 Debugging Your System[...]

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9: Debugging Your Sy stem ARM720T CORE CPU MANUAL EPSON 9-1 9 Debugging Y our System This chapter describes how to de bug a system based on an ARM720 T processor . It contains the following sectio ns: 9.1 About debugging your system ................. ......................... ..................... .... 9-2 9.2 Controlling debugging ............. ..[...]

9: Debugging Your Syste m 9-2 EPSON ARM720T CORE CPU MANUAL 9.1 About debugging your system The advanced debugging features of the ARM72 0T processor make it easier to develop application software, operating sy stems, and th e hardware itself. 9.1.1 A typical debug system The ARM720T processor forms one component of a debug system that interfaces f[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-3 9.2 Controlling debugging The major blocks of the ARM720T processor are: ARM CPU core This has hardware support for debug. EmbeddedICE-RT macrocell A set of registers and comparators that you use to generate debug exceptions (such as breakpoints). This unit is described in The EmbeddedICE-[...]

9: Debugging Your Syste m 9-4 EPSON ARM720T CORE CPU MANUAL 9.2.1 Debug modes Y ou can perform debugging in either of the following modes: Halt mode When the system is in halt mode, the core enters debug state when it encounters a breakpoint or a watc hpoint. In debug state, the core is stopped and isolated from the rest of the system. When debug h[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-5 9.3 Entry into debug st ate If the system is in halt mode, any of the following types of interrupt force the processor into debug state: • a breakpoint (a given instruction fetch) • a watchpoint (a data access) • an external debug request. Note: In monitor mode, the processor continu[...]

9: Debugging Your Syste m 9-6 EPSON ARM720T CORE CPU MANUAL 9.3.1 Entry into debug st ate on breakpoint The ARM720T processor marks instructions as being breakpointed as they enter the instruction pipeline, but the core does not en ter debug state until the instruction reaches the Execute stage. Breakpointed instructions are not exe cuted. In stead[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-7 9.3.3 Entry into debug st ate on debug request An ARM720T core in halt mode can be forced in to debug state on debug request in either of the following ways: • through EmbeddedICE-RT programming (see Programming breakpoints on page 9-36, and Programming watchpoints on page 9-38.) • by [...]

9: Debugging Your Syste m 9-8 EPSON ARM720T CORE CPU MANUAL 9.3.5 Clocks The system and test clocks must be synchronized externally to the processor . The ARM Multi-ICE debug agent directly supports one or more cores within an ASIC design. Synchronizing off-chip debug clocking with th e ARM720T processor requires a three-stage synchronizer . The of[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-9 9.4 Debug interface The ARM720T processor debug interface is ba sed on IEEE Std. 1 149.1- 1990, Standard T est Access Port and Boundary-Scan Architecture . Refer to this standard for an explanation of the terms used in this chapter , and for a description of the T AP controller states. 9.4[...]

9: Debugging Your Syste m 9-10 EPSON ARM720T CORE CPU MANUAL 9.6 The EmbeddedICE-RT macrocell The ARM720T processor Embedde dICE-RT macrocell module provides integrated on-chip debug support for the ARM720T core. The EmbeddedICE-RT module is connected directly to the core and therefore functions on the virtual address of the processor before reloca[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-11 Abort status register This register identifies whethe r an abort exception entry was caused by a breakpoint, a watchpoint, or a rea l abort. For more information, se e Abort status regist er on page 9-38. Debug Communications Channel (DCC) The DCC passes information between the target and[...]

9: Debugging Your Syste m 9-12 EPSON ARM720T CORE CPU MANUAL 9.8 EmbeddedICE-RT register map The locations of the EmbeddedICE-RT registers are shown in T able 9-1. 9.9 Monitor mode debugging The ARM720T processor contains logic that enables the debugging of a system without stopping the core entirely . This means that critical interrupt rout ines c[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-13 9.9.2 Restrictions on mo nitor-mode debugging There are several restrictions you must be aw are of when the ARM core is configured for monitor-mode debugging: • Breakpoints and watchpoints cannot be data-dependent in monitor mode. No support is provided for use of the range functionalit[...]

9: Debugging Your Syste m 9-14 EPSON ARM720T CORE CPU MANUAL 9.10 The debug communications channel The ARM720T EmbeddedICE-RT macrocell contains a Debug Communication Channel (DCC) for passing information between the target and the host debugger . This is implemented as coprocessor 14. The DCC comprises two registers, as follows: DCC Control Regist[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-15 The Domain Access Control Register bit assignments are shown in T able 9-2. Note: If execution is halted, bit 0 might remain asserted. The debugger can clear it by writing to the Domain Access Control Register. Writing to this register is rarely nece ssary, because in normal operation the[...]

9: Debugging Your Syste m 9-16 EPSON ARM720T CORE CPU MANUAL 9.10.2 Communication s through the DCC Messages can be sent and received through the DCC. Sending a message to the debugger Messages are sent from the processor to the debugger as follows: 1 When the processor wishes to send a messa ge to EmbeddedICE-RT , it first checks that the communic[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-17 9.1 1 Scan chains and the JT AG interface There are three JT AG-style scan chains within the ARM720T processor . These enable debugging and EmbeddedICE-RT programming. A JT AG-style T est Access Port (T AP) controller controls the sc an chains. For more details of the JT AG specification,[...]

9: Debugging Your Syste m 9-18 EPSON ARM720T CORE CPU MANUAL Scan chain 15 Scan chain 15 is dedicated to the system cont rol coprocessor registers (the CP15 registers). There are 37 bits in scan chain 15. From D BGTDI to DBGTDO , the order of the bits is: •r e a d / w r i t e b i t • instruction encoding bi ts [3:0] (see Table 9-3) • data bus[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-19 9.12 The T AP controller The T AP controller is a state machine that de termines the state of the boundary-scan test signals DBGTDI and DBGTDO . Figure 9-8 shows the state transitions that occur in the T AP controller . Figure 9-8 Test access port controll er state transitions From IEEE S[...]

9: Debugging Your Syste m 9-20 EPSON ARM720T CORE CPU MANUAL 9.13 Public JT AG instructions T a ble 9-4 shows the public JT AG instructions. In the following descriptions, the ARM720T processor samples DBGTDI and DBGTMS on the rising edge of HCLK with DBGTCKEN HIGH. The T AP con troller states are shown in Figure 9-8 on page 9-19. 9.13.1 SCAN_N (b0[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-21 9.13.3 IDCODE (b1 1 10) The IDCODE instruction connects the device id entification code register (or ID register) between DBGTDI and DBGTDO . The ID register is a 32-bit register that enables the manufacturer , part number , and version of a component to be read through the T AP . See ARM[...]

9: Debugging Your Syste m 9-22 EPSON ARM720T CORE CPU MANUAL 9.14 T est dat a registers The six test data registers that can connect between DBGTDI and DBGTDO are described in the following sections: • Bypass register • ARM720T processor device identi fication (ID) code register • Instruction register on page 9-23 • Scan path select registe[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-23 9.14.3 Instruction register Purpose Changes the current T AP instruction. Length 4 bits. Operating mode In the SHIF T -IR state, the instruction register is selected as the serial path between DBGTDI , and DBGTDO . During the CAPTURE-IR state, th e binary value 0001 is loaded into this re[...]

9: Debugging Your Syste m 9-24 EPSON ARM720T CORE CPU MANUAL 9.14.5 Scan chains 1 and 2 The scan chains enable serial access to the co re logic, and to the EmbeddedICE-RT hardware for programming purposes. Each scan chain cell is simple and comprises a serial register and a multiplexor . The scan cells perform three basic functions: •c a p t u r [...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-25 During SHIF T -DR, a data value is shifted into the serial register . Bits 32 to 36 specify the address of the EmbeddedICE-RT register to be accessed. During UPDA TE-DR, this register is either read or written depending on the value of bit 37 (0 = read, 1 = write). See Figure 9-12 on pa g[...]

9: Debugging Your Syste m 9-26 EPSON ARM720T CORE CPU MANUAL 9.16 Examining the core and the system in debug st ate When the ARM720T processor is in debug state, you can examine the co re and system state by forcing the load and store multiples into the instruction pipeline. Before you can examine the core and system st ate, the debugg er must dete[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-27 9.16.1 Determining the core st ate When the processor has entered debug state from Thumb state, the simp lest course of action is for the debugger to force the core back into ARM state. The debugger can then execute the same sequence of instructions to determine the processor state. T o f[...]

9: Debugging Your Syste m 9-28 EPSON ARM720T CORE CPU MANUAL All these instructions execute at debug speed. De bug speed is much slower than system speed. This is because between each core clock, 33 clocks occur in order to shift in an instruction, or shift out data. Executing instructions this slow ly is acceptable for ac cessing the core state be[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-29 When the ARM720T processor returns to debug st ate after a system speed access, bit 33 of scan chain 1 is set HIGH. The state of bit 33 gives the debug ger information about why the core entered debug state the first time this scan chain is read. 9.17 Exit from debug st ate Leaving debug [...]

9: Debugging Your Syste m 9-30 EPSON ARM720T CORE CPU MANUAL Figure 9-3 on page 9- 5 shows that the final memory access occurs in the cycle after DBGACK goes HIGH. This is the point at which the cycle counter must be disabled. Figure 9-1 1 on page 9-29 shows that the first memory access th at the cycle counter has not previously seen occurs in the [...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-31 9.18.3 W atchpoint with another exception If a watchpointed access simultaneously causes a Data Abort, the ARM720T processor enters debug state in abort mode. Entry into debug is held off until the core changes into abort mode and has fetched the instruct ion from the abort vector . A sim[...]

9: Debugging Your Syste m 9-32 EPSON ARM720T CORE CPU MANUAL 9.18.6 Summary of return address calculations T o determine whether entry to debug state wa s due to a breakpoint, watchpoint, or debug request ( DBGRQ ), bit 33 ( DBGBREAK ) of scan chain 1 must be consulted together with bit 12 ( DBGMOE ) of the debug status register (register 1 of scan[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-33 9.19.2 Interrupt s When the ARM720T processor enters debug st ate, interrupts are automatically disabled. If an interrupt is pending during the instruct ion prior to entering debug state, the ARM720T processor enters debug state in the mode of the interrupt. On entry to debug state, the d[...]

9: Debugging Your Syste m 9-34 EPSON ARM720T CORE CPU MANUAL Figure 9-12 EmbeddedICE-RT block d iagram The data to be written is shifted into the 32-bit data field, the address of the register is shifted into the 5-bit address field, and the read/write bit is set. The data to be written is scann ed into the 32-b it data fiel d, the address o f the [...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-35 9.20.2 Using the dat a, and address mask registers For each value register in a regist er pair , there is a mask register of the same format. Set ting a bit to 1 in the mask register has the effect of making the corresponding bit in the value register disregarded in the comparison. For ex[...]

9: Debugging Your Syste m 9-36 EPSON ARM720T CORE CPU MANUAL DBGEXT[1:0] Is an external input to EmbeddedICE-RT logic that enables the watchpoint to be dependent on some external condition. The DBGEXT input for W atchpoint 0 is labeled DBGEXT[0] . The DBGEXT input for W atchpoint 1 is labeled DBGEXT[1] . CHAIN Can be connected to the chain ou tput [...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-37 3 Program the data value register only when you require a data-dependent breakpoint, that is only when you have to match the actual instruction code fetched as well as the address. If the data valu e is not required, program the data mask register to 0xFFFFFFFF (all bits set). Otherwise p[...]

9: Debugging Your Syste m 9-38 EPSON ARM720T CORE CPU MANUAL 9.22 Programming watchpoint s This section contains examples of how to prog ram the watchpoint unit to generate br eakpoints and watchpoints. Many other ways of programming the watch point unit registers are possible. For example, simple range breakpoints can be provided by setting one or[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-39 9.24 Debug control register The Debug Control Register is si x bits wide. W rites to the Debug Control Register occur when a watchpoint unit register is written. Reads of the Debug Control Register occur when a watchpoint unit register is read. See Watchpoint unit registers on page 9-33 f[...]

9: Debugging Your Syste m 9-40 EPSON ARM720T CORE CPU MANUAL 9.24.1 Disabling interrupt s IRQs and FIQs are disabled under the following conditions: • during debugging ( DBGACK HIGH) • when the INTDIS bit is set. The core interrupt enable signal, IFEN , is driven as shown in T able 9-10. 9.24.2 Forcing DBGRQ Figure 9-17 on page 9-42 shows that [...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-41 9.25 Debug st atus register The debug status register is 13 bits wide. If it is accessed for a write (with the read/write bit set), the status bits are written. If it is acce ssed for a read (with the read/write bit clear), the status bits are read. The format of the deb ug status registe[...]

9: Debugging Your Syste m 9-42 EPSON ARM720T CORE CPU MANUAL The structure of the debug control and status registers is shown in Figure 9-17. Figure 9-17 Debu g control and status register structur e Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 0 Bit 2 Bit 1 De bug co nt ro l re giste r De bug sta t us re giste r TB IT (from co re) T R ANS [1 ] (from co re) +[...]

9: Debugging Your Sys tem ARM720T CORE CPU MANUAL EPSON 9-43 9.26 Coupling breakpoint s and watchpoint s Y ou can couple watchpoint units 1 and 0 together using the CHA IN and RANGE inputs. The use of CHAIN enables W atchpoint 0 to be triggered only if W atchpoint 1 has previously matched. The use of RANGE enables simple range checking to be perfor[...]

9: Debugging Your Syste m 9-44 EPSON ARM720T CORE CPU MANUAL 9.26.2 DBGRNG signal The DBGRNG signal is derived as follows: DBGRNG = ((({Av[31:0],Cv[4:0]} XNOR {A[31:0],C[4:0]}) OR {Am[31:0],Cm[4:0]}) == 0xFFFFFFFFF) AND ((({Dv[31:0],Cv[7:5]} XNOR {D[31:0],C[7:5]}) OR Dm[31:0],Cm[7:5]}) == 0x7FFFFFFFF) The DBGRNG output of watchpoint register 1 prov[...]

10 ETM Interface[...]

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10: ETM Interface ARM720T CORE CPU MANUAL EPSON 10-1 10 ETM Interface This chapter describes the ETM interface that is provided on the ARM720T processor . It contains the following sections: 10.1 About the ETM interface ............ ..................... ..................... ................... 10-1 10.2 Enabling and disabling the ETM7 interface .[...]

10: ETM Interface 10-2 EPSON ARM720T CORE CPU MANUAL 10.3 Connecti ons between th e ETM7 macrocell and the ARM720T processor T able 10-1 shows the connections that you must make between th e ETM7 macrocell and the ARM720T processor . T able 10-1 Co nnections between the ETM7 macrocell and th e ARM720T proce ssor ETM7 macrocell signal name ARM720T p[...]

10: ETM Interface ARM720T CORE CPU MANUAL EPSON 10-3 10.4 Clocks and reset s The ARM720T processor uses a single clock, HCLK , as both the main system clock and the JT AG clock. Y ou must connect the processor clock to both HCLK and TCK on the ETM. Y ou can then use TCKEN to control the JT AG in terface. T o trace through a warm reset of the ARM720[...]

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11 Test Support[...]

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11: Test Support ARM720T CORE CPU MANUAL EPSON 11-1 11 T est Support This chapter describes the test methodology and the CP15 test registers for the ARM720T processor synthesized logic and TCM. It contains the following sections: 1 1.1 About the ARM720T test registers ...... ..................... ..................... ........... 1 1-1 1 1.2 Automa[...]

11: Test Support 11-2 EPSON ARM720T CORE CPU MANUAL 1 1.2 Automatic T est Pattern Generation (A TPG) Scan insertion is already performed and fi xed for the ARM720T processor . Y ou can use Automatic T est Pattern Generation (A TPG) too ls to create the necessary scan patterns to test the logic outputs from all registers. A summary of ARM720T A TPG [...]

11: Test Support ARM720T CORE CPU MANUAL EPSON 11-3 1 1.3 T est St ate Register The test sta te register contai ns only one bit , bit 0: Bit 0 set Enable MMU and cache test. Bit 0 clear Disable MMU and cache test. At reset ( HRESETn LOW), bit 0 is cleared. The test state register operations are shown in T a ble 1 1-2. Note: Cache and MMU t est oper[...]

11: Test Support 11-4 EPSON ARM720T CORE CPU MANUAL T a ble 1 1-3 summarizes register c7, c9, and c15 operations. The CAM read format for Rd is shown in Figure 1 1-2. Figure 11-2 Rd format, CAM read The CAM write format for R d is shown in Figure 1 1-3. Figure 11-3 Rd format, CAM write In Figure 1 1-3, bit labels have the following meanings: V Va l[...]

11: Test Support ARM720T CORE CPU MANUAL EPSON 11-5 The RAM read format for Rd is shown in Figure 1 1-4. Figure 11-4 Rd format, RAM read The RAM write format for Rd is shown in Figure 1 1-5. Figure 11-5 Rd format, RAM write The CAM match, RAM read format for Rd is shown in Figure 1 1-6. Figure 11-6 Rd form at, CAM match RAM read The CAM read format[...]

11: Test Support 11-6 EPSON ARM720T CORE CPU MANUAL The CAM match, RAM read format for data is shown in Figure 1 1-9. Figure 11-9 Data format, CAM match RAM read 1 1.4.1 Addressing the CAM and RAM For the CAM read or write, and RAM read or write operations you must specify the segment, index, and word (for the RAM operations). The CAM and RAM opera[...]

11: Test Support ARM720T CORE CPU MANUAL EPSON 11-7 Example 1 1-1 shows sample code fo r performing software test of the cache. It contains typical operations with register C15.C. Example 11-1 Cach e test operations ; CAM write, read and check for segment 2 ; Write cache victim pointer with index 0, segment 2 MOV r0,#0 ORR r1,r0,#2 :SHL: 0x5 MCR p1[...]

11: Test Support 11-8 EPSON ARM720T CORE CPU MANUAL ; Now read and check MOV r8,#8 MOV r2,#0x10 MOV r1,#0 loop1 MCR p15,3,r1,c15,c3,0 ; write C15 .C to ‘0’ MCR p15,2,r2,c15,c11,2 ; read RAM to C15.C MRC p15,3,r5,c15,c3,0 ; read C15.C to R4 ADD r2,r2,#0x04 CMP r5,r0 BNE TEST_FAIL SUBS r8,r8,#1 BNE loop1 B TEST_PASS 1 1.5 MMU test registers and o[...]

11: Test Support ARM720T CORE CPU MANUAL EPSON 11-9 The CP15 register c15 operations that oper ate on the CAM, RAM1, and RAM2 are shown in T able 1 1-5. Note: For the CAM match, RAM1 read operation a TLB miss will not cause a page walk. These register c15 operations are all issued as MCR, which means that the read and match operations have to be la[...]

11: Test Support 11-10 EPSON ARM720T CORE CPU MANUAL Figure 1 1-12 shows the format of Rd fo r CAM writes and data for CAM reads. Figure 11-12 Rd format, CA M write and data format, CAM read In Figure 1 1-12 on page 1 1 -10, V is the V alid bit, P is the Preserve bit, and SIZE_C sets the memory region size . The allowed values of SIZE_C are shown i[...]

11: Test Support ARM720T CORE CPU MANUAL EPSON 11-11 In Figure 1 1-13, AP[3:0] determin es the setting of the access permission bits for a memory region. The allowed values are shown in T able 1 1-8. Figure 1 1-14 shows the data format for RAM1 reads. Figure 11-14 Data format, RAM1 read In Figure 1 1-14, bits [24:22] are only valid for a match oper[...]

11: Test Support 11-12 EPSON ARM720T CORE CPU MANUAL In Figure 1 1-15, SIZE_R2 sets the memory regi on size. The allowed values of SIZE_R2 are shown in T able 1 1-10 . Note: The encoding for SIZE_R2 is different from SIZE_C. 1 1.5.1 Addressing the CAM, RAM1, and RAM2 For the CAM read or write, RAM1 read or write, and RAM2 read or write operations, [...]

11: Test Support ARM720T CORE CPU MANUAL EPSON 11-13 Example 1 1-2 shows sample code fo r performing software test of the MMU. It contains typical operations with C15.M. Example 11- 2 MMU test operations ; MMU write, read and check for CAM, RAM1 and RAM2 ; Load victim pointer with 0 MOV r0,#0 MCR p15,0,r0,c10,c0,0 ; Write pattern 0 x5A5A5A50 in CAM[...]

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Appendix A Signal Descriptions[...]

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A: Signal Descriptions ARM720T CORE CPU MANUAL EPSON A-1 A Signal Descriptions This chapter describes the interface signals of the ARM720T processor . It contains the following sectio ns: A.1 AMBA interface signals ...... ..................... ..................... ......................... .... A-1 A.2 Coprocessor interface signals ..... .........[...]

A: Signal Descriptions A-2 EPSON ARM720T CORE CPU MANUAL A.2 Coprocessor interface signals The coprocessor interface signals are shown in T able A-2. T able A-2 Coprocessor in terface signal descriptio ns Name Type Description EXTCPA Input Exter nal coprocessor absent. This signal must be HIGH if no external coprocessor is present. EXTCPB Input Ext[...]

A: Signal Descriptions ARM720T CORE CPU MANUAL EPSON A-3 A.3 JT AG and test signals JT AG and test signal descriptions are shown in T able A -3. T able A-3 JT AG and test signal descripti ons Name Type Description DBGIR[3:0] Output TAP instruction r egister. These signals reflect the current instruction loaded in to the TAP controller instruction r[...]

A: Signal Descriptions A-4 EPSON ARM720T CORE CPU MANUAL A.4 Debugger signals The debugger signal descriptions are shown in T able A-4. DBGTDO Output Test data out. JTAG test data out signal. DBGTMS Input Test mode select. JTAG test mode sele ct signal. a. These signals are only active when scan chain 0 is selected. T able A-4 Debugg er signal desc[...]

A: Signal Descriptions ARM720T CORE CPU MANUAL EPSON A-5 A.5 Embedded trace macrocell interface signals The ETM interface s ignals are shown in T able A-5. DBGRNG[1:0] Output Rang e out. These signals indicate that the re levant EmbeddedICE-RT watch point register has matched the condition s curre ntly present on the address, data, and control buse[...]

A: Signal Descriptions A-6 EPSON ARM720T CORE CPU MANUAL ETMTBIT Output Thumb state. This signal, when HIGH, indicates th at the processor is executing the THUMB instruction set. When LOW, the processor is executing the ARM instruction set. ETMBIGEND Output Big -endian format. When this signal is HIGH, the processor treats bytes in memory as being [...]

A: Signal Descriptions ARM720T CORE CPU MANUAL EPSON A-7 A.6 A TPG test signals A TPG test signals used by the ARM720T processo r are shown in T able A-6. A.7 Miscellaneous signals Miscellaneous signals used by the ARM720T processor are shown in T able A-7. T able A-6 A TPG test signal descriptions Name Type Description TESTENABLE Input This signal[...]

A: Signal Descriptions A-8 EPSON ARM720T CORE CPU MANUAL THIS P AGE IS BLANK.[...]

Glossary[...]

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Glossary ARM720T CORE CPU MANUAL EPSON Glossary-1 Glossary This glossary describes some of the terms used in this manual. Where terms can have several meanings, the meaning presented here is intended. Abort Is caused by an illegal memory access . Abort can be caused by the external memory system, an external MMU , or the EmbeddedICE-RT logic. Addre[...]

Glossary Glossary-2 EPSON ARM720T CORE C PU MANUAL Complex Instruction Set Computer A microprocessor that recognizes a large number of instructions. See also Reduced Instruction Set Computer . CPSR See Program Status Register . Control bit s The b ottom eight bits of a program stat us register . The control bits change when an exception arises and [...]

Glossary ARM720T CORE CPU MANUAL EPSON Glossary-3 Halt mode One of two debugging modes. When de bugging is performed in halt mode, the core stops when it encounters a watchpoint or breakpoint, and is isolated from the rest of the system. See also Monitor mode . ICE See In-circuit emulator . Idempotent A mathematical quantity that when applied to it[...]

Glossary Glossary-4 EPSON ARM720T CORE C PU MANUAL Monitor mode One of two debugging modes. When debugging is performed in monitor mode, the core does not stop when it encounters a watchpoint or breakpoint, but enters an abort exception routine. See also Halt mode . PC See Program Counter . Privileged mode Any processor mode other than User mode. M[...]

Glossary ARM720T CORE CPU MANUAL EPSON Glossary-5 Saved Program St atus Register The Saved Program Status Register wh ich is associated with the current processor mode and is undefined if ther e is no such Saved Program Status Register , as in User mode or System mode. See also Program Status Register . SBO See Should Be One fields. SBZ See Should [...]

Glossary Glossary-6 EPSON ARM720T CORE C PU MANUAL T est Acce ss Port The collection of four mandatory and one optional terminals that form the input/output and control interface to a JT AG boundary-scan architecture. The mandatory terminals are TDI , TDO , TMS , and TCK . The optional terminal is nTRST . Thumb instruction A halfword which specifie[...]

Index[...]

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Index ARM DDI 0229B EPSON Index-1 Index The items in this index are listed in alphabeti cal order , with symbols and numerics appearing at the end. T he references given are to page numbers. A Abort Data 9-6, 9-31 handler 9-6 mode 2-4 Prefetch 9-32 vector 9-31 Abort status register 9-38 Aborted watchpoint 9-31 Aborts Data 2-12 indexed addressing 2-[...]

Index Index-2 EPSON ARM DDI 0229B level two 7-10 section 7-8 Device identifica tion code 9-2 1, 9-22 Disabling EmbeddedICE-RT 9-11 Disabling the ETM interface 10-1 Domain 7-2 access control 7-17 faults 7-15, 7-20 E Early termination definition 2-17 EmbeddedICE- RT 1-3, 9-3 breakpoints coupling with watchpoints 9-43 hardware 9-36 softwar e 9-37 comm[...]

Index ARM DDI 0229B EPSON Index-3 test registers 11-8 Modes, privileged 8-10 Monitor mode 9-4, 9-12, 9-13 Multi-ICE 9-8 O Operating modes Abort mode 2-4 changing 2-4 FIQ 2-4 IRQ mode 2-4 Supervisor mode 2-4 System mode 2-4 Undefined mode 2-4 User mode 2-4 Operating state ARM 2-1 switching 2-1 to ARM 2-1 to THUMB 2-1 THUMB 2-1 P Page tables 7-5 Perm[...]

Index Index-4 EPSON ARM DDI 0229B SWI 2-13 System mode 2-4 System speed instruction 9-28, 9- 31 System state determining 9- 28 T T bit (in CPS R) 2-8 TAP controller 9-3, 9-10, 9- 19 controller state transitions 9-19 instruction 9-23 state 9-24 Test registers 11-1 state register 11-3 Test Access Port, See TAP Test data registers 9-22 Thumb instructi[...]

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ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU MANUAL EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION http://www.epsondevice.com Issue April, 2004 Printed in Japan C A Document code: 405003400 CORE CPU MANUAL ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU MANUAL ARM720T Revision 4 (AMBA AHB Bus Int[...]