Texas Instruments MSP50C614 manual

MSP50C614 Mixed-Signal Processor User ’ s Guide SPSU014 January 2000 Printed on Recycled Paper[...]

IMPORT ANT NOTICE T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify , before placing orders, that information being relied on is current and complete. All product[...]

iii Read This First Preface Read This First About This Manual This user ’s guide gives information for the MSP50C61 mixed-signal proces- sor . This information includes a functional overview , a detailed architectural description, device peripheral functional description, assembly language instruction listing, code development tools, applications[...]

Notational Conventions iv version of the special typeface for emphasis; interactive displays use a bold version of the special typeface to distinguish commands that you enter from items that the system displays (such as prompts, command output, error messages, etc.). Here is a sample program listing: 0011 0005 0001 .field 1, 2 0012 0005 0003 .field[...]

Information About Cautions and W arnings v Read This First Unless the list is enclosed in square brackets, you must choose one item from the list. Some directives can have a varying number of parameters. For example, the .byte directive can have up to 100 parameters. The syntax for this di- rective is: .byte value 1 [, ... , value n ] This syntax s[...]

vi[...]

Contents vii Contents 1 Introduction to the MSP50C614 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features of the C614 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Applications 1-3 . . . . . . . . . . . . . . [...]

Contents viii 3.1.1 General-Purpose I/O Ports 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Dedicated Input Port F 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 Dedicated Output Port G 3-5 . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

Contents ix Contents 4.4.8 Class 8 Instructions: Logic and Bit 4-41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.9 Class 9 Instructions: Miscellaneous 4-42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Bit, Byte, Word and String Addressing 4-44 . . . . . . . . . . . . . . . . . . . . . . . [...]

Contents x 5.9.10 String Functions 5-45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.1 1 Constant Functions 5-47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Implementation Details 5-48 . . . . . . . . . . . . . . . . . . . . . .[...]

Contents xi Contents B.3.5 Host Write Sequence B-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.6 Host Read Sequence B-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.7 Interrupts B-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

Figures xii Figures 1–1 Functional Block Diagram for the C614 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Oscillator and PLL Connection 1-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 RESET Circuit 1-9 . . . . . . . . . . . . . . . . . [...]

Figures xiii Contents 5–9 Select Program Folder Dialog 5-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10 Copying Files 5-1 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 1 Setup Complete Dialog 5-1[...]

T ables xiv T ables 1–1 Signal and Pad Descriptions for the C614 1-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 MSP50C614 100-Pin PJM Plastic Package Pinout Description 1-1 1 . . . . . . . . . . . . . . . . . . . . . 2–1 Signed and Unsigned Integer Representation 2-5 . . . . . . . . . . . . . . . . . . [...]

T ables xv Contents 4–25 Class 4d Instruction Description 4-35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26 Class 5 Instruction Encoding 4-36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27 Class 5 Instruction Description 4-36 . . [...]

Notes, Cautions, and Warnings xvi Notes, Cautions, and W arnings MSP50C605 and MSP50C604 1-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGA Package 1-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

1-1 Introduction to the MSP50C614 The MSP50C614 (C614) is a low cost, mixed signal controller , that combines a speech synthesizer , general-purpose I/O, onboard ROM, and direct speaker-drive in a single package. The computational unit utilizes a powerful new DSP which gives the C614 unprecedented speed and computational flexibility compared with p[...]

Features of the C614 1-2 1.1 Features of the C614 Advanced, integrated speech synthesizer for high quality sound Operates up to 8 MHz (performs up to 8 MIPS) V ery low-power operation, ideal for hand-held devices Low voltage operation, sustainable by three batteries Reduced power stand-by modes, less than 10 µ A in deep-sleep mode Supports high-qu[...]

Applications 1-3 Introduction to the MSP50C614 1.2 Applications Due to its low cost, low-power needs, and high programmability , the C614 is suitable for a wide variety of applications incorporating I/O control and high- quality speech: T alking T oys T alking Books Electronic Learning Aids T alking Dictionaries Games W arning Systems T alking Cloc[...]

Development Device: MSP50P614 1-4 1.3 Development Device: MSP50P614 The MSP50P614 is an EPROM based version of the MSP50C614, and is available in 120 pin windowed ceramic pin grid array . This EPROM based version of the device is only available in limited quantities to support software development. Since the MSP50P614 program memory is EPROM, each [...]

Functional Description 1-5 Introduction to the MSP50C614 1.4 Functional Description The device consists of a micro-DSP core, embedded program and data memory , and a self-contained clock generation system. General-purpose pe- riphery is comprised of 64 bits of partially configurable I/O. The core processor is a general-purpose 16 bit micro-controll[...]

C605 and C604 (Preliminary Information) 1-6 built in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive capability . The block diagram appearing in Figure 1–1 gives an overview of the C614 functionality . IMPORT ANT : a one bit comparator is not currently supported. T ypical connections to implement reset function[...]

C605 and C604 (Preliminary Information) 1-7 Introduction to the MSP50C614 Figure 1–1. Functional Block Diagram for the C614 SCAN IN SYNC PLL OSC OUT OSC IN RESET DAC M DAC P PGM PULSE TEST SCAN CLK SCAN OUT Serial Comm. OTP Program Emulation Break Point (C614 only) (P614 only) DAC 0x30 32 Ohm PDM Initialization Logic OSC Reference Resistor T rimm[...]

C605 and C604 (Preliminary Information) 1-8 Figure 1–2. Oscillator and PLL Connection MSP50P614 MSP50C614 OSC IN OSCOUT PLL C (PLL) = 3300 pF † 22 pF † 22 pF † 10 M Ω † 10 M Ω † 32.768 kHz † † Keep these components as close as possible to the OSC IN , OSC OUT , and PLL pins. a) Crystal Oscillator Operation Connections b) Resisto[...]

C605 and C604 (Preliminary Information) 1-9 Introduction to the MSP50C614 Figure 1–3. RESET Circuit Reset Switch 1 µ F (20%) Inside the MSP50P614 MSP50C614 V DD V SS 100 k Ω IN914 5 V V PP T o Pin 1 of Optional (Scanport) Connector RESET 1 k Ω † T o Pin 2 of optional (scan port) connector † IN914 ‡ (MSP50P614 only) † If it is necessa[...]

T erminal Assignments and Signal Descriptions 1-10 1.6 T erminal Assignments and Signal Descriptions T able 1–1. Signal and Pad Descriptions for the C614 SIGNAL P AD NUMBER I/O DESCRIPTION Input/Output Ports PA 0 – P A 7 75 → 68 I/O Port A general-purpose I/O (1 Byte) PB 0 – PB 7 85 → 78 I/O Port B general-purpose I/O (1 Byte) PC 0 – PC[...]

T erminal Assignments and Signal Descriptions 1-1 1 Introduction to the MSP50C614 The C614 is sold in die form for its volume production. Contact you local TI sales office for mount and bond information. MSP50C614 is also available in 100 pin plastic QFP package. The pinout is shown in Figure 1–4 and T able 1–2. T able 1–2. MSP50C614 100-Pin [...]

T erminal Assignments and Signal Descriptions 1-12 Figure 1–4. MSP50C614 100 Pin PJM PLastic Package Pinout (Preliminary Information) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 50 49 48 47 [...]

T erminal Assignments and Signal Descriptions 1-13 Introduction to the MSP50C614 For software development and prototyping, a windowed ceramic 120-pin grid array packaged P614 is available. The P614’s PGA package is shown in Figure 1–5 and T able 1–3: Figure 1–5. 120 Pin Grid Array Package for the Development Device, P614 12 13 10 1 1 89 67 [...]

T erminal Assignments and Signal Descriptions 1-14 The pin assignments for the 120-pin PGA package (P614 device only) are out- lined in the following table. Refer to Section 1.6 for more information on the signal functions. N nc nc V DD † PF 7 PF 5 PF 2 V PP PG 15 PG 12 PG 10 V SS V DD nc M nc nc DAC M DAC P PF 6 PF 3 PF 1 PG 14 PG 11 PG 8 nc nc [...]

2-1 MSP50C614 Architecture A detailed description of MSP50C614 architecture is included in this chapter . After reading this chapter , the reader will have in-depth knowledge of internal blocks, memory organization, interrupt system, timers, clock control mecha- nism, and various low power modes. T opic Page 2.1 Architecture Overview 2–2 . . . . [...]

2-2 2.1 Architecture Overview The core processor in the C614 is a medium performance mixed signal pro- cessor with enhanced microcontroller features and a limited DSP instruction set. In addition to its basic multiply/accumulate structure for DSP routines, the core provides for a very efficient handling of string and bit manipulation. A unique accu[...]

2-3 MSP50C614 Architecture Figure 2–1. MSP50C614 Core Processor Block Diagram Multiplier (MR)† Shift V alue (SV)† 17 x 17 Multiplier Product High (PH)† 16 bit ALU MUX 32 Accumulators (AC0–AC31)† Column Exchange Loop (R4) Index (R5) Page (R6) Stack (R7) R0 R1 R2 R3 Arithmetic Unit MUX MUX Data Memory 640 x 17 bit Interrupt Flag Register [...]

2-4 Figure 2–2. Computational Unit Block Diagram (The shaded boxes represent internal programmable registers.) Accumulators 5 16 AC3 AC2 AC1 AC0 Read/W rite AC7 AC6 AC5 AC4 AC1 1 AC10 AC9 AC8 AC15 AC14 AC13 AC12 AC19 AC18 AC17 AC16 AC23 AC22 AC21 AC20 AC27 AC26 AC25 AC24 AC31 AC30 AC29 AC28 AP3 AP2 AP1 AP0 5 Internal Databus – 16 bit Shift V al[...]

Computation Unit 2-5 MSP50C614 Architecture 2.2 Computation Unit The computational unit (CU) is comprised of a (17-bit by 17-bit) Booth’s algorithm multiplier and a 16-bit arithmetic logic unit (ALU). The block diagram of the CU is shown in Figure 2–2. The multiplier block is served by 4 system registers: a 16-bit multiplier register (MR), a 16[...]

Computation Unit 2-6 The multiplicand source can be either data memory , an accumulator , or an accumulator offset. The multiplier source can be either the 16-bit multiplier register (MR) or the 4-bit shift value (SV) register . For all multiply operations, the MR register stores the multiplier operand. For barrel shift instructions, the multiplier[...]

Computation Unit 2-7 MSP50C614 Architecture Figure 2–3. Overview of the Multiplier Unit Operation MUL TIPLIER UNIT INPUTS Multiplicand 16-bit - latched in a write-only register from one of the following sources ... Data Memory Accumulator Offset Accumulator X Multiplier - writeable and readable by Data Memory as one of the following ... Multiplie[...]

Computation Unit 2-8 The all-zero values are necessary for data transfers and unitary operations. All-zeros also serve as default values for the registers, which helps to minimize residual power consumption. The databus path through ALU-A is used to input memory values (RAM) and constant values (program memory) to the ALU. The PH and PL inputs are [...]

Computation Unit 2-9 MSP50C614 Architecture Figure 2–4. Overview of the Arithmetic Logic Unit ALU INPUTS ALU-A 16-bit - selects between ... all 0’ s Offset Accumulator Register Data Memory ALU-B 16-bit - selects between ... (PH) (PL) ARITHMETIC LOGIC UNIT performs arithmetic, comparison, and logic ALU OUTPUTS THE ACCUMULA TOR BLOCK Accumulator [...]

Computation Unit 2-10 When writing an accumulator-referenced instruction, therefore, the working accumulator address is stored in one of AP0 to AP3. The C614 instruction set provides a two-bit field for all accumulator referenced instructions. The two-bit field serves as a reference to the accumulator pointer which, in turn, stores the address of t[...]

Data Memory Address Unit 2-1 1 MSP50C614 Architecture For some instructions, the 5-bit string processor can also preincrement or predecrement the AP pointer-value by +1 or –1, before being used by the accumulator register block. This utility can be effectively used to minimize software overhead in manipulating the accumulator address. The premodi[...]

Data Memory Address Unit 2-12 Figure 2–6. Data Memory Address Unit R3 R2 R1 R0 R7 R6 R5 R4 Internal Databus Arithmetic Block RAM Address Internal Program Bus Register Addressing Mode ST ACK P AGE INDEX LOOP 2.3.1 RAM Configuration The data memory block (RAM) is physically organized into 17-bit parallel words. Within each word, the extra bit (bit [...]

Data Memory Address Unit 2-13 MSP50C614 Architecture There are two-byte instructions, for example MOVB, which cause the proces- sor to read or write data in a byte (8-bit) format. (The B appearing at the end of MOVB designates it as an instruction, which uses byte-addressable argu- ments.) The byte-addressable mode causes the hardware to read/write[...]

Program Counter Unit 2-14 2.4 Program Counter Unit The program counter unit provides addressing for program memory (onboard ROM). It includes a 16-bit arithmetic block for incrementing and loading addresses. It also consists of the program counter (PC), the data pointer (DP), a buffer register , a code protection write-only register , and a hardwar[...]

Memory Organization: RAM and ROM 2-15 MSP50C614 Architecture 2.6 Memory Organization: RAM and ROM Data memory (RAM) and program memory (ROM) are each restricted to internal blocks on the C614. The program memory is read-only and limited to 32K, 17-bit words. The lower 2048 of these words is reserved for an internal test code and is not available to[...]

Memory Organization: RAM and ROM 2-16 Figure 2–7. C614 Memory Map (not drawn to scale) 0x00 Program Memory 0x0000 Internal T est Code 2048 x 17 bit 0x07FF 0x0800 0x7F00 0x7FF0 0x7FF7 (reserved) User ROM 30704 x 17 bit (C614 : read-only) (P614 : EPROM) Usable Interrupt V ectors† 8 x 17 bit Macro Call V ectors 255 x 17 bit (overlaps interrupt vec[...]

Memory Organization: RAM and ROM 2-17 MSP50C614 Architecture When writing to any of the locations in the I/O address map, therefore, the bit-masking need only extend as far as width of location. Within a 16-bit accumulator , the desired bits (width of location) should be right-justified. The write operation is accomplished using the OUT instruction[...]

Memory Organization: RAM and ROM 2-18 T able 2–2. Summary of C614’s Peripheral Communications Ports (Continued) I/O Map Address Width of Location Allowable Access Control Register Name Abbreviation State after RESET LOW Section for Reference 0x3A 16 bits read & write TIMER1 period PRD1 0x0000 28 0x3B 16 bits read & write TIMER1 count-do[...]

Memory Organization: RAM and ROM 2-19 MSP50C614 Architecture 3.1.5, Internal and External Interrupts , for more information regarding the specific conditions for each interrupt-trigger event. The branch operation, however , is also contingent on whether the interrupt service has been enabled. This is done individually for each interrupt, using the [...]

Memory Organization: RAM and ROM 2-20 The protection modes are implemented on the C614 as follows. Within the ROM is a dedicated storage for the block protection word (address 0x7FFE). The block protection word is divided into two 6-bit fields and two single-bit fields. The remainder of the 17-bit word is broken into three single-bit fields which a[...]

Memory Organization: RAM and ROM 2-21 MSP50C614 Architecture [(N TM + 1) * 512 – 1] = highest ROM address within the block to be protected (N TM + 1) * 512 = lowest ROM address which is left unprotected N TM = the value programmed at TM5 … TM0 (true protection marker) N FM ≡ the binary complement of N TM N FM = the value programmed at FM5 …[...]

Interrupt Logic 2-22 When the device is powered up, the hardware initialization circuit reads the value stored in the block protection word. The value is then loaded to an inter- nal register and the security state of the ROM is identified. Until this occurs, execution of any instructions is suspended. The same initialization sequence is executed b[...]

Interrupt Logic 2-23 MSP50C614 Architecture the RESET low , assuming there is no interruption in power . For a full description of the interrupt-trigger events, refer to Section 3.1.5, Internal and External Interrupts . (8-bit wide location) 07 06 05 04 03 02 01 00 ← INT number IFR Interrupt Flag register address 0x39 D5 D4 PF D3 D2 T2 T1 DA low [...]

Interrupt Logic 2-24 Note: Setting a Bit in the IFR Using the OUT Instruction Setting a bit within the IFR using the OUT instruction is a valid way of obtain- ing a software interrupt. An IFR bit may also be cleared, using OUT , at any time. Assuming the global interrupt enable is set and the specific bit within the IMR is set, then, at the time of[...]

Interrupt Logic 2-25 MSP50C614 Architecture Figure 2–8 provides an overview of the interrupt control sequence. INT0 is the highest priority interrupt, and INT7 is the lowest priority interrupt. Figure 2–8. Interrupt Initialization Sequence INTD instruction CLEAR INTE instruction SET Global Interrupt Enable CLEAR • Internal T imer Underflow ?[...]

Timer Registers 2-26 In addition to being individually enabled, all interrupts must be GLOBALL Y enabled before any one can be serviced. Whenever interrupts are globally disabled, the interrupt flag register may still receive updates on pending trigger events. Those trigger events, however , are not serviced until the next INTE instruction is encou[...]

Timer Registers 2-27 MSP50C614 Architecture (16-bit wide location) 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PRD1 register † address 0x3A PP PP P PP P PP P P P P P P TIMER1 Period TIM1 register † address 0x3B TT TT T TT T TT T T T T T T TIMER1 Count-Down T riggers INT1 on underflow PRD2 register address 0x3E PP PP P PP P PP P P P P P P TI[...]

Timer Registers 2-28 Selection between the timer-source options is made using two control bits in the interrupt/general control register (IntGenCtrl). The IntGenCtrl is a 16-bit port-addressed register at 0x38. Clearing bit 8 selects 1/2 MC as the source for TIMER1. Setting bit 8 selects the reference oscillator as the source for TIM- ER1. Similarl[...]

Clock Control 2-29 MSP50C614 Architecture 2.9 Clock Control 2.9.1 Oscillator Options The C614 has two oscillator options available. Either option may be enabled using the appropriate control bits in the clock speed control register (ClkSpdCtrl). The ClkSpdCtrl is described in Section 2.9.3, Clock Speed Con- trol Register . The first oscillator opti[...]

Clock Control 2-30 The maximum required CPU clock frequency for the C614 is 8 MHz over the entire V DD range. This rate applies to the speed of the core processor . Higher CPU clock frequencies may be achieved, but these are not qualified over the complete range of supply voltages in the guaranteed specification. Figure 2–9. PLL Performance Oscil[...]

Clock Control 2-31 MSP50C614 Architecture Note: ClkSpdCtrl Bits 8 and 9 When bit 8 is set in the ClkSpdCtrl register , the crystal oscillator bit (bit 9) be- comes the least significant bit of the 6-bit resistor trim value. Thus, bits 15–1 1 and 9 make up the 6-bit resistor trim value. For example, if the ClkSpdCtrl register is 00010 X 1 1XXXXXXX[...]

Clock Control 2-32 Bit 10 in the ClkSpdCtrl is idle state clock control. The level of deep-sleep generated by the IDLE instruction is partially controlled by this bit. When this bit is cleared (default setting), the CPU Clock is stopped during the sleep, but the MC remains running. When the idle state clock control bit is set, both the CPU clock an[...]

Execution Timing 2-33 MSP50C614 Architecture However , the general specification of the adjustment can be useful in certain circumstances. For example, the adjustment can be used to obtain a program- matic increase or decrease in the speed of the RT O reference. The default val- ue for the adjustment, after RESET low , is all zeros. The zero value [...]

Reduced Power Modes 2-34 Figure 2–10. Instruction Execution and Timing N N+1 N+2 N+3 N+4 N+5 N+6 N+7 FETCH CLOCK N–1 N N+1 N+2 N+3 N+4 N+5 DECODE N–2 N–1 N N+1 N+2 N+3 N+4 N+5 EXEC N–1 N N+1 N+2 N+3 N+4 N+5 DA T A ADD N N+1 N+2 N+3 N+4 N+5 N+6 N+7 PC ADD 2.1 1 Reduced Power Modes The power consumption of the C614 is greatest when the DAC [...]

Reduced Power Modes 2-35 MSP50C614 Architecture The deepest sleep achievable on the C614, for example, is a mode where all of the previously listed subsytems are stopped. In this state, the device draws less than 10 µ A of current and obtains the greatest power savings. It may be awakened from this state using an external interrupt (input port). A[...]

Reduced Power Modes 2-36 The power consumed during sleep when the RT O oscillator is left running is greater than the power consumed during sleep when the CRO oscillator is left running. If the idle state clock control is clear , then the PLL circuitry , active during sleep, will attempt to regulate the MC to whatever frequency is programmed in the[...]

Reduced Power Modes 2-37 MSP50C614 Architecture T able 2–3. Programmable Bits Needed to Control Reduced Power Modes → deeper sleep … relatively less power → Control Bit Label for Control Bit LIGHT MID DEEP Idle state clock control bit 10 ClkSpdCtrl register (0x3D) A 0 1 1 Enable reference oscillator bit 09 : CRO or bit 08 : RTO ClkSpd[...]

Reduced Power Modes 2-38 T able 2–4. Status of Circuitry When in Reduced Power Modes (Refer to T able 2–3) → deeper sleep … relatively less power → Component Determined by Controls LIGHT MID DEEP CPU clock (processor core) E stopped stopped stopped PLL clock circuitry A, E running stopped stopped Master clock (MC) status (C614 perip[...]

Reduced Power Modes 2-39 MSP50C614 Architecture The interrupt-trigger event associated with each of the two internal TIMERs is the underflow condition of the TIMER. In order for a TIMER underflow to occur during sleep, the TIMER must be left running before going to sleep. In certain cases, however , the act of going to sleep can bring a TIMER to st[...]

Reduced Power Modes 2-40 In order to wake the device using a programmable interrupt, the interrupt mask register must have the respective bit set to enable interrupt service (see Sec- tion 2.7, Interrupt Logic ). In some cases, the ARM bit must also be set, in order for the interrupts to be visible during sleep T able 2–3. After the C614 wakes fr[...]

3-1 Peripheral Functions This chapter describes in detail the MSP50C614 peripheral function, i.e., I/O control ports, general purpose I/O ports, interrupt control registers, compara- tor and digital-to-analog (DAC) control mechanisms. T opic Page 3.1 I/O . . . 3–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

I/O 3-2 3.1 I/O The C614 has 64 input-output pins. Forty of these are software configurable as either inputs or outputs. Eight are dedicated inputs, and the remaining sixteen are dedicated outputs. 3.1.1 General-Purpose I/O Ports The forty configurable input/output pins are organized in 5 ports, A,B,C,D, and E. Each port is one byte wide. The pins [...]

I/O 3-3 Peripheral Functions is 0x00 (all inputs). The state of the data registers after RESET low is unknown (input state provided by external hardware). The 8-bit width is the true size of the mapped location. This is independent of the address spacing, which is greater than 8-bits. When writing to any of the locations in the I/O address map, the[...]

I/O 3-4 3.1.2 Dedicated Input Port F Port F is an 8-bit wide input-only port. The data presented to the input pin can be read by referring to the appropriate bit in the F port data register , address 0x28. This is done using the IN instruction, with the 0x28 address as an argument. The state of the F port data registers after RESET low is unknown ([...]

I/O 3-5 Peripheral Functions 3.1.3 Dedicated Output Port G Port G is a 16-bit wide output-only port. The output drivers have a T otem-Pole configuration. The data driven by the output pin can be controlled by setting or clearing the appropriate bit in the G port Data register , address 0x2C. This is done using the OUT instruction, with the 0x2C add[...]

I/O 3-6 3.1.4 Branch on D Port Instructions exist to branch conditionally depending upon the state of ports D 0 and D 1 . These conditionals are COND1 and COND2, respectively . The condi- tionals are supported whether the D 0 and D 1 ports are configured as inputs or as outputs. The following table lists the four possible logical states for D 0 and[...]

I/O 3-7 Peripheral Functions Registers ). INT1 and INT2 are high-priority , internal interrupts triggered by the underflow conditions on TIMER1 and TIMER2, respectively . Please refer to Section 2.8, Timer Registers , for a full description of the TIMER controls and their underflow conditions. When properly enabled, any of these interrupts may be u[...]

Digital-to-Analog Converter (DAC) 3-8 3.2 Digital-to-Analog Converter (DAC) The C614 incorporates a two-pin pulse-density-modulated DAC which is capable of driving a 32 Ω loudspeaker directly . T o drive loud speakers other than 32 Ω , an external impedance-matching circuit is required. 3.2.1 Pulse-Density Modulation Rate The rate of the master[...]

Digital-to-Analog Converter (DAC) 3-9 Peripheral Functions DAC Control register Address 0x34 (4-bit wide location) 03 02 01 00 Set DAC resolution to 8 bits: Set DAC resolution to 9 bits: Set DAC resolution to 10 bits: DM E 0 0 DM E 0 1 DM E 1 0 DM : Drive Mode selection (0 = C3x style : 1 = C5x style) E : pulse-density-modulation Enable (overall DA[...]

Digital-to-Analog Converter (DAC) 3-10 style . Their selection is made at bit 3 of the DAC control register (0x34). The C3x style is selected by clearing bit 3, and the C5x style is selected by setting bit 3. The default value of the selection is zero which yields the C3x style . The overflow bits appear in the DAC data register (14 and 13) to the [...]

Digital-to-Analog Converter (DAC) 3-1 1 Peripheral Functions For a given sampling rate and DAC resolution, the CPU clock rate may be increased, if necessary , through the use of over-sampling. In the previous example, an original sampling rate of 8 kHz and a PDM rate of 4 MHz was used. A 2-times over-sampling, therefore, would require the PDM rate [...]

Digital-to-Analog Converter (DAC) 3-12 8 kHz Nominal Synthesis Rate 32.768 kHz Oscillator Reference DAC Precision IntGenCtrl PDMCD Bit Over- Sampling Factor ClkSpdCtrl PLLM Register V alue (hex) Master Clock Rate (MHz) PDM Rate (MHz) CPU Clock Rate (MHz) Output Sampling Rate (kHz) Number of Instructs Between DAC Interrupts Number of Instructs Betwe[...]

Digital-to-Analog Converter (DAC) 3-13 Peripheral Functions 10 kHz Nominal Synthesis Rate 32.768 kHz Oscillator Reference DAC Precision IntGenCtrl PDMCD Bit Over- Sampling Factor ClkSpdCtrl PLLM Register V alue (hex) Master Clock Rate (MHz) PDM RA TE (MHZ) CPU Clock Rate (MHz) Output Sampling Rate (kHz) Number of Instructs Between DAC Interrupts Nu[...]

Comparator 3-14 3.3 Comparator The C614 provides a simple comparator that is enabled by a control register option. The inputs of the comparator are shared with pins PD 4 and PD 5 . PD 5 is the noninverting input to the comparator , and PD 4 is the inverting input. When the comparator is enabled, the conditional operation COND2 (normally associated [...]

Comparator 3-15 Peripheral Functions bit is automatically CLEARed again if an INT6 event occurs at the same time that the associated mask bit is SET (IntGenCtrl, address 0x38, bit 6). The latter indicates that the program vectoring associated with INT6 is enabled. (The flag bit is SET when the INT event occurs. Only if the mask bit is set, does the[...]

Comparator 3-16 The comparator , along with all of its associated functions, is enabled by setting bit 15 of the interrupt/general control register (IntGenCtrl, address 0x38). The default value of the register is zero: comparator disabled. Note: IntGenCtrl Register Bit 15 At the time that bit 15 in the IntGenCtrl is set, PD 4 and PD 5 become the co[...]

Interrupt/General Control Register 3-17 Peripheral Functions 3.4 Interrupt/General Control Register The interrupt/general control (IntGenCtrl) is a 16-bit wide port-mapped register located at address 0x38. The primary component in the IntGenCtrl is the 8-bit interrupt mask register (IMR). The service branch enable status for each of the eight inter[...]

Interrupt/General Control Register 3-18 The upper four bits in the IntGenCtrl have independent functions. Bit 12 is the enable bit for the pull-up resistors on input port F . Setting this bit engages all 8 F-port pins with at least 100-k Ω pull-ups (see Section 3.1.2, Dedicated Input Port F ) Bit 13 is the PDMCD bit for the pulse-density modulati[...]

Hardware Initialization States 3-19 Peripheral Functions 3.5 Hardware Initialization States The RESET pin is configured at all times as an external interrupt. It provides for a hardware initialization of the C614. When the RESET pin is held low , the device assumes a deep sleep state and various control registers are initialized. After the RESET pi[...]

Hardware Initialization States 3-20 Note: Internal RAM State after Reset The RESET low will not change the state of the internal RAM, assuming there is no interruption in power . This applies also to the interrupt flag register . The same applies to the states of the accumulators in the computational unit. When RESET is brought back high again, man[...]

Hardware Initialization States 3-21 Peripheral Functions Note: Stack Pointer Initialization The software stack pointer (R7) must be initialized by the programmer , so that it points to some legitimate address in data memory (RAM). This must be done prior to any CALL or C CC instruction. If this is not done, then the first push/pop operation perform[...]

3-22[...]

4-1 Assembly Language Instructions This chapter describes in detail about MSP50P614/MSP50C614 assembly language. Instruction classes, addressing modes, instruction encoding and explanation of each instruction is described. T opic Page 4.1 Introduction 4–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

Introduction 4-2 4.1 Introduction In this chapter each MSP50P614/MSP50C614 class of instructions is explained in detail with examples and restrictions. Most instructions can individually address bits, bytes, words or strings of words or bytes. Usable program memory is 30K by 17-bit wide and the entire 17-bits are used for instruction set encoding. [...]

System Registers 4-3 Assembly Language Instructions or by 2 for double word instructions) each execution cycle and points to the next program memory location to fetch. During a maskable interrupt, the next PC address is stored in the TOS register and is reloaded from T OS after the interrupt encounters an IRET instruction. Call and jump instruction[...]

System Registers 4-4 It is recommended to avoid using the TOS register altogether in applications and leave its operation to development tools only . 4.2.6 Product High Register (PH) This register holds the upper 16 bits of the 32 bit result of a multiplication, multiply-accumulate, or shift operation. The lower 16 bits of the result are stored in [...]

System Registers 4-5 Assembly Language Instructions During accumulator read operations, both A n and offset A n ~ are fetched. Depending on the instruction, either or both registers may be used. In addition, some write operations allow either register to be selected. The accumulator block can also be used in string operations. The selected accumula[...]

System Registers 4-6 value of the ST ACK register should be stored before use and restored after use. This register must point to the beginning of the stack in the RESET initialization routine before any CALL instruction or maskable interrupts can be used. CALL instructions increment R7 by 2., RET instructions decrement R7 by 2. The stack in MSP50P[...]

System Registers 4-7 Assembly Language Instructions T able 4–1. Status Register (ST A T) Bit Name Function 0 XM Sign extended mode bit. This bit is one, if sign extension mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6. 1 UM Unsigned multiplier mode. This bit is one if unsigned multiplier mode is enabled. See MSP50P614/M[...]

Instruction Syntax and Addressing Modes 4-8 4.3 Instruction Syntax and Addressing Modes MSP50P614/MSP50C614 instructions can perform multiple operations per instruction. Many instructions may have multiple source arguments. They can premodify register values and can have only one destination. The addressing mode is part of the source and destinatio[...]

Instruction Syntax and Addressing Modes 4-9 Assembly Language Instructions 4.3.2 Addressing Modes The addressing modes on the MSP50P614/MSP50C614 are immediate, di- rect, indirect with post modification, and three relative modes. The relative modes are: Relative to the INDEX or R5 register . The effective address is (indirect reg- ister + INDEX). S[...]

Instruction Syntax and Addressing Modes 4-10 T able 4–3. Rx Bit Description R x Operation 0 0 0 R0 0 0 1 R1 0 1 0 R2 0 1 1 R3 1 0 0 R4 or LOOP 1 0 1 R5 or INDEX 1 1 0 R6 or P AGE 1 1 1 R7 or ST ACK T able 4–4. Addressing Mode Bits and {adrs} Field Description Relative Repeat addressing mode encoding, adrs Relative Addressing Modes Clocks clk Wo[...]

Instruction Syntax and Addressing Modes 4-1 1 Assembly Language Instructions T able 4–5. MSP50P614/MSP50C614 Addressing Modes Summary ADDRESSING SYNT AX OPERA TION Direct name [dest,] [src,] *dma16 [*2] [, next A] name * dma16 [*2] [,src] [, next A] Second word operand ( dma16 ) used directly as memory address. Long Relative name [dest] [,src] , [...]

Instruction Syntax and Addressing Modes 4-12 For any particular addressing mode, replace the { adrs } with the syntax shown in T able 4–4. T o encode the instruction, replace the am , R x and pm bits with the bits required by the addressing mode (T able 4–4). For example, the instruction MOV A n [~] , { adrs } [, next A ] indicates all of the f[...]

Instruction Syntax and Addressing Modes 4-13 Assembly Language Instructions 4.3.3 Immediate Addressing The address of the memory location is encoded in the instruction word or the word following the opcode is the immediate value. Single word instructions take one clock cycle and double word instructions take two clock cycles. Syntax: name dest , [ [...]

Instruction Syntax and Addressing Modes 4-14 4.3.4 Direct Addressing Direct addressing always requires two instruction words. The second word operand is used directly as the memory address. The memory operand may be a label or an expression. Syntax: name [ dest , ] [ src , ] * dma16 [* 2] [ , next A ] name * dma16 [* 2] [ , src ] [ , next A ] Memor[...]

Instruction Syntax and Addressing Modes 4-15 Assembly Language Instructions 4.3.5 Indirect Addressing Indirect addressing uses one of 8 registers (R0...R7) to point memory addresses. The selected register can be post-modified. Modifications include increments, decrements, or increments by the value in the index register (R5). For post-modifications[...]

Instruction Syntax and Addressing Modes 4-16 Example 4.3.12 MOV *R5++R5, A0~, ++A Refer to the initial processor state in T able 4–8 before execution of this instruction. Preincrement AP0. After preincrement, A0 is AC3 and A0~ is AC19. The contents of AC19 are stored in the data memory location in R5. R5 is then incremented by R5. Final result, A[...]

Instruction Syntax and Addressing Modes 4-17 Assembly Language Instructions Address + Rx (x = 0 – 7) Index Register (R5) Operand Example 4.3.17 AND A0, *R3+R5 Refer to the initial processor state in T able 4–8 before execution of this instruc- tion. A0 is accumulator AC2. The contents of the data memory byte location pointed to by R3+R5 is ANDe[...]

Instruction Syntax and Addressing Modes 4-18 Example 4.3.20 MOV A3, *R6+0x10 Refer to the initial processor state in T able 4–8 before execution of this instruc- tion. Load A3 (AC29) with the contents of byte address, R6+0x10. The value of R6 is unchanged. Final result, AC29=0x01 12. Example 4.3.21 ADD A0~, A0, *R6+0x10, ++A Refer to the initial [...]

Instruction Syntax and Addressing Modes 4-19 Assembly Language Instructions 4.3.7 Flag Addressing This addressing mode addresses only the 17 th bit (the flag/tag bit) located in data memory . This addressing applies to Class 8a instructions as explained in section 4.4. Using flag addressing, the flag bit can be loaded or saved. In addition, various[...]

Instruction Syntax and Addressing Modes 4-20 4.3.8 T ag/Flag Bits The words T AG and flag may be used interchangeably in this manual. The T AG bit is the 17 th bit of a word of data memory . There are 640 words of RAM, each 17 bits wide, on the C614. Therefore, there are 640 T AG bits on the C614. When an instruction of the format, MOV accumulator,[...]

Instruction Syntax and Addressing Modes 4-21 Assembly Language Instructions However , xFLAG instructions use {flagadrs} addressing modes. This includes global (dma6) and relative (R6 + 6–bit offset). Both take only one clock cycle. Possible sources of confusion: Consider the following code, ram0 equ 0x0000 *2 ;RAM word zero ram1 equ 0x0001 *2 ;RA[...]

Instruction Classification 4-22 4.4 Instruction Classification The machine level instruction set is divided into a number of classes. The classes are primarily divided according to field references associated with memory , hardware registers, and control fields. The following descriptions give class-encode bit assignments, the OP code value within [...]

Instruction Classification 4-23 Assembly Language Instructions T able 4–1 1. Symbols and Explanation (Continued) Symbol Explanation next A Accumulator control bits as described in T able 4–6. [ next A ] The preincrement (++A) or predecrement (– –A) operation on accumulator pointers A n or A n ~. Not NOT condition on conditional jumps, condi[...]

Instruction Classification 4-24 T able 4–1 1. Instruction Classification (Continued) Class Sub- Class Description 4 Register and memory reference A Memory references that use R x ; all addressing modes available B Memory references with short constant fields operating on R x C Memory references with long constant fields operating on R x and other[...]

Instruction Classification 4-25 Assembly Language Instructions T able 4–12. Classes and Opcode Definition Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Class 1a 0 0 C1a ~A~ next A A n am R x pm Class 1b 0 1 C1b s A n am R x pm Class 2a 1 0 1 0 C2a A n imm8 Class 2b 1 1 1 0 0 next A A n C2b 0 0 1 A~ ~A Class 3 1 1 1 0 0 next A A n C3 0 A~ † ~A Cl[...]

Instruction Classification 4-26 Class 1a provides the four basic instructions of load, store, add, and subtract between accumulator and data memory . Either the accumulator or the offset accumulator (A~ bit dependent) can be stored in memory with the MOV instruction. The MOV instruction can load the accumulator (or its offset) depending on the ~A b[...]

Instruction Classification 4-27 Assembly Language Instructions T able 4–15. Class 1b Instruction Description C1b Mnemonic Description 0 0 0 0 OR A n , { adrs } ORS A n , { adrs } Logical OR the contents of the data memory location in { adrs } and the selected accumulator . Result(s) stored in accumulator(s). ALU status is modified 0 0 0 1 AND A n[...]

Instruction Classification 4-28 T able 4–15. Class 1b Instruction Description (Continued) C1b Mnemonic Description 1 0 1 1 MULAPL A n , { adrs } MULAPLS A n , { adrs } Multiply the MR register by the addressing mode { adrs } and add the lower 16 bits of the product to the accumulator . Latch the upper 16 bits into the PH register . ALU status is [...]

Instruction Classification 4-29 Assembly Language Instructions constants. Long constants (16 bits) and long string constants differ in that ref- erences are made to constants in the second word of the two-word instruction word. References made to a single 16 bit integer constant are immediate. That is, the actual constant value follows the first wo[...]

Instruction Classification 4-30 T able 4–18. Class 2b Instruction Description C2b Mnemonic Description 0 0 0 ADD A n [~], A n [~], imm16 [, next A] ADDS A n [~], A n [~], pma16 Add long constant to accumulator (or offset accumulator if A~=1) and store result to accumulator (~A=0) or offset accumulator (~A=1). ALU status modified. 0 0 1 MOV A n [~[...]

Instruction Classification 4-31 Assembly Language Instructions between the accumulator and the MR, SV , or PH register . As with all accumula- tor referenced instructions, string operations are possible as well as premodi- fication of one of 4 indirectly referenced accumulator pointer registers (AP). T able 4–19. Class 3 Instruction Encoding Bit [...]

Instruction Classification 4-32 T able 4–20. Class 3 Instruction Description (Continued) C3 Mnemonic Description 0 1 0 0 0 XOR A n [~], A n ~, A n [, next A ] XORS A n [~], A n ~, A n Logically exclusive OR accumulator with of fset accumulator and store the results in accumulator (~A=0 or 1). ALU status is modified. 0 1 0 0 1 OR A n [~], A n ~, A[...]

Instruction Classification 4-33 Assembly Language Instructions T able 4–20. Class 3 Instruction Description (Continued) C3 Mnemonic Description 1 0 1 0 0 MOV SV , A n [~] [, next A ] MOVS SV , A n [~] T ransfer accumulator(A~=0) or offset accumulator (A~=1) to SV register . Transfer status is modified. 1 0 1 0 1 MOV PH, A n [~] [, next A ] MOVS P[...]

Instruction Classification 4-34 T able 4–20. Class 3 Instruction Description (Continued) C3 Mnemonic Description 1 1 1 1 0 MUL A n [~] [, next A ] MULS A n [~] Multiply MR register by accumulator (A~=1) or of fset accumulator (A~=0) and latch the rounded upper 16 bits of the resulting product into the PH register . 1 1 1 1 1 SHL A n [~] [, next A[...]

Instruction Classification 4-35 Assembly Language Instructions T able 4–22. Class 4a Instruction Description C4a Mnemonic Description 0 MOV { adrs }, R x Store R x register to data memory referred by addressing mode {adrs}. Modify transfer status. 1 MOV R x , { adrs } Load R x with the value in data memory referred by addressing mode {adrs}. Modi[...]

Instruction Classification 4-36 4.4.5 Class 5 Instructions: Memory Reference Class 5 instructions provide transfer to and from data memory and all registers except accumulators and R x which are included in classes 1 and 4. The registers referenced for both read and write operations are the multiplier register (MR), the product high register (PH), [...]

Instruction Classification 4-37 Assembly Language Instructions T able 4–27. Class 5 Instruction Description (Continued) C5 Mnemonic Description 0 1 0 1 1 MOV { adrs }, TOS Store the contents of the top of stack (TOS) register to the data memory location referred by addressing mode { adrs }. T ransfer status is modified. 0 1 1 0 0 ST AG { adrs } S[...]

Instruction Classification 4-38 T able 4–27. Class 5 Instruction Description (Continued) C5 Mnemonic Description 1 1 1 1 0 RPT { adrs } 8 Load repeat counter with lower 8 bits of data memory location referred by addressing mode { adrs }. Interrupts are queued during execution. 1 1 1 1 1 MOV ST A T , { adrs } Load status (ST A T) register with eff[...]

Instruction Classification 4-39 Assembly Language Instructions T able 4–30. Class 6b Instruction Description C6b Mnemonic Description 0 IN A n [~], port6 INS A n [~], port6 T ransfer the port’s 16 bit value to an accumulator . Port addresses 0–63 are valid. ALU status is modified. 1 OUT port6 , A n [~] OUTS port6 , A n [~] T ransfer a 16 bit [...]

Instruction Classification 4-40 T able 4–31. Class 7 Instruction Encoding and Description Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VCALL vector8 1 11111101 vector8 J cc 1 0 0 0 0 0 Not cc R x pm JMP *A n 1 0 0 0 1 0 x A n x C cc 1 0 0 0 0 1 Not cc x CALL *An 1 0 0 0 1 1 x A n x cc cc names Description cc cc name Not cc name 0 0 0 0 0 Z NZ Con[...]

Instruction Classification 4-41 Assembly Language Instructions T able 4–31. Class 7 Instruction Encoding and Description (Continued) cc cc names Description cc cc name Not cc name 1 0 1 0 1 Unconditional 1 0 1 1 0 Not assigned 1 0 1 1 1 Not assigned 1 1 0 0 0 XZ XNZ Conditional on XSF 1 1 0 0 1 XS XNS Conditional on XZF 1 1 0 1 0 XG XNG Condition[...]

Instruction Classification 4-42 T able 4–33. Class 8a Instruction Description C8a Mnemonic Description 0 0 0 MOV TF n , { flagadrs } Load flag bit (17 th bit) from data memory referred by flag addressing mode { flagadrs } to either TF1 or TF2 in status register . Load with inverted value if Not =1. 0 1 0 OR TF n , { flagadrs } Logically OR either[...]

Instruction Classification 4-43 Assembly Language Instructions T able 4–35. Class 9a Instruction Encoding Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Class 9a 1 1 1 0 1 0 0 A n C9a 0 R x 1 1 Class 9b 1 1 1 1 1 1 0 C9a imm8 Class 9c 1 1 1 1 1 0 1 AP n 0 C9c x imm5 Class 9d 1 1 1 1 1 1 1 1 0 C9d 0 0 0 0 ENDLOOP n 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 n [...]

Bit, Byte, Word and String Addressing 4-44 T able 4–38. Class 9c Instruction Description C9c Mnemonic Description 0 MOV AP n , imm6 Load the accumulator pointer ( AP ) with a five bit constant. 1 ADD AP n , imm5 Add a five bit constant imm5 to the referenced accumulator pointer( AP ). T able 4–39. Class 9d Instruction Description C9d Mnemonic D[...]

Bit, Byte, Word and String Addressing 4-45 Assembly Language Instructions is a string of bytes. The length of the byte string is stored in the string register (STR). T o define the length of a string, the STR register should hold the length of the string minus 2. For example, if the length of a byte string is 10, then STR should be 8. A byte string[...]

Bit, Byte, Word and String Addressing 4-46 Flag address: The flag (or T AG) address uses linear addressing from 0 to the size of data memory in 17 bit wide words (0 to 639 for MSP50P614/ MSP50C614). Only the 17 th bit is accessible. When a word memory location is read, the corresponding flag for that location is always loaded into the T AG bit of t[...]

Bit, Byte, Word and String Addressing 4-47 Assembly Language Instructions Figure 4–4. Data Memory Example Absolute Word Memory Location Data Memory Location (even) = 2 * (Absolute word memory location) MS Byte LS Byte Data Memory Location (odd) 0x0000 0x0000 0x12 0x34 0x0001 0x0001 0x0002 0x56 0x78 0x0003 0x0002 0x0004 0x9a 0xbc 0x0005 0x0003 0x0[...]

Bit, Byte, Word and String Addressing 4-48 Example 4.5.7 MOV STR, 4–2 MOV AP0, 2 MOV R0, 0x0001 * 2 MOVBS A0, *R0++ Refer to Figure 4–4 for this example. The word-string length is 4. AP0 points to AC2 accumulator . R0 is loaded with 0x0002. The fourth instruction loads the value of the word-string at the RAM address in R0, 0x0002. R0 autoincrem[...]

MSP50P614/MSP50C614 Computational Modes 4-49 Assembly Language Instructions Example 4.5.10 MOV STR, 0 SFLAG *0x00032 MOVS A0, *0x0031 * 2 RFLAG *0x00032 MOVS A0, *0x0031 * 2 Refer to Figure 4–4 for this example. This example is to illustrate the effect of the tag/flag bit when used with a string instruction. The string register (STR) is loaded wi[...]

MSP50P614/MSP50C614 Computational Modes 4-50 T able 4–41. MSP50P614/MSP50C614 Computational Modes Computational Mode Setting Instruction Resetting Instruction Function Sign extension SXM RXM ST A T .XM = 1 produces sign extension on data as it is passed into accumulators. This mode copies the 16 th bit of the data in the multiplier/multiplicand t[...]

MSP50P614/MSP50C614 Computational Modes 4-51 Assembly Language Instructions Example 4.6.2 SXM MOV STR, 2–2 ; string length=2 MOV MR, 0x8000 MOV A0, 0x8000, ++A ; load MS Byte MOV A0, 0x0000, ––A ; load LS Byte MULTPLS A0, A0 This example illustrates the sign extension mode on a string during multiplication. Here, two negative numbers 0x800000[...]

MSP50P614/MSP50C614 Computational Modes 4-52 Example 4.6.1 SOVM MOV A0, 0x7FFE ADD A0, 5 In this example, we set the overflow mode (OM = 1 of ST A T). Adding 0x7FFE with 5 causes an overflow (OF = 1 of ST A T). Since the expected result is a positive value, the accumulator saturates to the largest representable value, 0x7FFF . If overflow mode was [...]

Hardware Loop Instructions 4-53 Assembly Language Instructions high word of the result is stored in the PH register and is 0x3FFF . The low word is stored in A0~ as 0x0001. If the two numbers are considered as Q15 fraction- al numbers (all bits are to the right of the decimal point), then the result will be a Q30 number . T o translate a Q30 number[...]

Hardware Loop Instructions 4-54 the execution of a string instruction, interrupts are queued. Queued interrupts are serviced according to their priority after the string operation is complete. In addition to repeat and string instructions, the combination of repeated string instructions has a very useful function. Since there is only one counter to[...]

String Instructions 4-55 Assembly Language Instructions 4.8 String Instructions Class 1, 2, 3, and 6 instructions can have string modes. During the execution of string instruction, STR register value plus 2 is assumed as string length. An accumulator string is a group of consecutive accumulators spanning from A n to the next N consecutive accumulat[...]

String Instructions 4-56 A1 string is 0x233EFBCA1223 and *0x200 = 0x9086EE3412AC. STR = 3–2=1, defines a string length of 3. Final result, A1~ string = 0x233EFBCA1223 + 0x9086EE3412AC = 0xB3C5E9FE24CF , AC5=0x24CF , AC6=0xE9FE, AC7=0xB3C5, STR=2 (unchanged). Notice that this instruction has accumulated a carry . Special String Sequences: There ar[...]

Lookup Instructions 4-57 Assembly Language Instructions 4.9 Lookup Instructions T able lookup instructions transfer data from program memory (ROM) to data memory or accumulators. These instructions are useful for reading permanent ROM data into the user program for manipulation. For example, lookup tables can store initial filter coefficients, char[...]

Lookup Instructions 4-58 Lookup instructions make use of the data pointer (DP) internally . The DP stores the address of the program memory location, loads the value to the destination, and increments it automatically after every load. Thus, the value of the DP is always the last used program memory address plus one. The content of DP changes after[...]

Input/Output Instructions 4-59 Assembly Language Instructions 4.10 Input/Output Instructions The MSP50P614/MSP50C614 processor communicates with other on-chip logic as well as external hardware through a parallel I/O interface. Up to 40 I/O ports are addressable with instructions that provide bidirectional data transfer between the I/O ports and th[...]

Special Filter Instructions 4-60 N tap filters ideally require 2N multiply–accumulates. Four instructions are provided to compute this equation: FIR, FIRK, COR and CORK. All filter instructions require overflow modes to be reset since these instructions have built in overflow hardware. In addition, these instructions must be used with a RPT instr[...]

Special Filter Instructions 4-61 Assembly Language Instructions theory requires). The second to last RAM location in the circular buffer is tagged using an ST AG instruction. Below is an example of how to set up circu- lar buffering with FIR or COR. When using the FIR or COR instruction with circular buffering, RAM needs to be allocated for the cir[...]

Special Filter Instructions 4-62 After the FIR or COR instruction executes, the new startOfBuff will be the last location in the circular buffer . After another FIR/COR instruction, the new startOfBuff will be the second to last location in the circular buffer , and so on. The second detail is the ST A T register . The ST A T register must be saved[...]

Special Filter Instructions 4-63 Assembly Language Instructions mov A0,*nextSample ;Replace last sample with newest sample mov *R0,A0 ; and update the start of the mov *startOfBuff,R0 ; circular buffer to here (R0) First, the overflow mode must be reset. Next, R5 must be loaded with the wrap around value of the circular buffer . Wrap around happens[...]

Special Filter Instructions 4-64 Any combination of registers different from the above will yield incorrect results with the FIR/COR instruction. Use R5 to wrap around R0 0x010 0x0100 0x0106 0x0102 x[k] x[k–1] x[k–2] x[k–3] tag After FIR/COR execution The ST A T register is saved in the filterST A T_tag location. The output of the fil- tering[...]

Special Filter Instructions 4-65 Assembly Language Instructions Important note about setting the ST A T register It is very important to consider the initial value of the filterST A T_tag variable. Failure to set up the filterST A T_tag variable can cause incorrect results in FIR/ COR operations. Overflow mode must always be reset. The overflow bit[...]

Special Filter Instructions 4-66 mov STAT,*filterSTAT_tag ;load STAT with last filter tag status rpt N–2 firk A0,*R0++ ;Do one sample ––> 32 bit result mov *filterSTAT_tag,STAT ;save STAT with last filter tag status ;R0 now points to the last sample movs *ySampleOut,A0 ;FIR outputs bits 0–15 in AC0, 16–32 in AC1 mov A0,*nextSample ;Rep[...]

Special Filter Instructions 4-67 Assembly Language Instructions Figure 4–6. Setup and Execution of MSP50P614/MSP50C614 Filter Instructions, N+1 T aps Accumulators 0–15 th bits of y 16–31 st bits of y 32–47 th bits of y AC r AC r +1 AC r +2 y[k] = Σ m =0..N h[ m ] x [k– m ] + Multiplier PH MR Past N samples, x [ k ] Coefficients, h[ k ] k[...]

Special Filter Instructions 4-68 Figure 4–7. Filter Instruction and Circular Buffering for N+1 T ap Filter 16 Bits TA G AC n+1 AC n+2 AC n y if T AG = 1 Rx even coeff_array DP coeff_array Rx even +1 CORK/FIRK only COR/FIR only h[0] h[1] h[2] 0 0 0 h[3] h[4] 0 0 0 h[N–1] 0 0 0 h[N] 0 0 16 Bits 17 th Bit coeff_array coeff_array is stored in progr[...]

Conditionals 4-69 Assembly Language Instructions 4.12 Conditionals The condition bits in the status register (ST A T) are used to modify program control through conditional branches and calls. V arious combinations of bits are available to provide a rich set of conditional operations. These condition bits can also be used in Boolean operations to s[...]

Legend 4-70 4.13 Legend All instructions of the MSP50P614/MSP50C614 use the following syntax: name [ dest ] [ , src ] [ , src1 ] [ , mod ] name Name of the instruction. Instruction names are shown in bold letter through out the text. dest Destination of the data to be stored after the execution of the instruction. Optional for some instructions or [...]

Legend 4-71 Assembly Language Instructions Symbol Meaning A~ Select offset accumulator as the source if this bit is 1. Used in opcode encoding only . ~A Select offset accumulator as the destination accumulator if this bit is 1. Used in opcode encod- ing only . A~ Select offset accumulator as the source if this bit is 0. Used in opcode encoding only[...]

Legend 4-72 Symbol Meaning n R V alue in repeat counter loaded by RPT instructions n s V alue in string register STR OF Overflow flag offset [ n ] n bit offset from a reference register . OM Overflow mode PC Program counter , 16 bits pma [ n ] n bit program memory address. For example, pma8 means 8-bit program memory address. If n is not specified,[...]

Legend 4-73 Assembly Language Instructions T able 4–45. Auto Increment and Decrement Operation next A b9 b8 No modification 0 0 Auto increment ++A 0 1 Auto Decrement –– A 1 0 T able 4–46. Addressing Mode Bits and adrs Field Description Strin g† Addressing Mode Encoding Relative Addressing Clocks Words String† Repeat Operation { adrs } 7[...]

Individual Instruction Descriptions 4-74 4.14 Individual Instruction Descriptions In this section, individual instructions are discussed in detail. Use the conditionals in Section 4.12 and the legend in Section 4.13 to help with individual instruction descriptions. Each instruction is discussed in detail and provides the following information: Asse[...]

Individual Instruction Descriptions 4-75 Assembly Language Instructions 4.14.1 ADD Add word Syntax [ label ] name dest , src [, src1 ] [, mod ] Clock , clk Words , w With RPT , clk Class ADD A n [~] , A n , { adrs } [ , next A ] T able 4–46 T able 4–46 T able 4–46 1a ADD A n [~] , A n [~] , imm16 [ , next A ] 2 2 N/R 2b ADD A n [ ~ ] , A n [ [...]

Individual Instruction Descriptions 4-76 Description Syntax Description ADD dest , src ADD src with dest and store the result to dest . ADD dest , src , src1 [, mod ] ADD src1 with src and store the result to dest . Premodify the mod before execution. (if provided) See Also ADDB, ADDS, SUB, SUBB, SUBS Example 4.14.1.1 ADD A2, A2~, *R2++R5, ––A [...]

Individual Instruction Descriptions 4-77 Assembly Language Instructions 4.14.2 ADDB ADD BYTE Syntax [ label ] name dest, src Clock , clk Words , w With RPT , clk Class ADDB A n , imm8 1 1 N/R 2a ADDB R x , imm8 1 1 N/R 4b Execution dest ⇐ dest + src PC ⇐ PC + 1 Flags Affected dest is A n :O F , SF , ZF , CF are set accordingly dest is R x : RCF[...]

Individual Instruction Descriptions 4-78 4.14.3 ADDS Add String Syntax [ label ] name dest, src, src1 Clock , clk Words , w With RPT , clk Class ADDS A n [ ~ ], A n , { adrs } T able 4–46 T able 4–46 T able 4–46 1a ADDS A n [ ~ ], A n [ ~ ], pma16 n S +4 2 N/R 2b ADDS A n [ ~ ], A n ~ , A n n S +2 1 n R +2 3 ADDS † A n [ ~ ], A n [ ~ ], PH [...]

Individual Instruction Descriptions 4-79 Assembly Language Instructions Example 4.14.3.3 ADDS A1, A1~, A1 Add accumulator string A1 to accumulator string A1 ~ , put result in accumulator string A1. Example 4.14.3.4 MULAPL A0, A0~ ADDS A0, A0~, PH The first instruction multiplies MR and A0~, adds PL to A0, and stores the result in A0. The second ins[...]

Individual Instruction Descriptions 4-80 4.14.4 AND Bitwise AND Syntax [label] name dest, src [ , src1 ] [ , mod ] Clock , clk Word , w With RPT , clk Class AND A n , { adrs } T able 4–46 T able 4–46 1b AND A n [~] , A n [~], imm16 [, next A ] 2 2 N/R 2b AND A n [~], A n ~, A n [, next A ] 1 1 n R +3 3 AND TF n , [!]{ flagadrs } 1 1 N/R 8a AND [...]

Individual Instruction Descriptions 4-81 Assembly Language Instructions See Also ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XORS Example 4.14.4.1 AND A3, *R4— – And word at address in R4 to A3, store result in A3. Decrement value in R4 by 2 (word mode) after the AND operation. Example 4.14.4.2 AND A0~, A0, 0xff0f, – –A Predecrement accumulator po[...]

Individual Instruction Descriptions 4-82 4.14.5 ANDB Bitwise AND Byte Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class ANDB A n , imm8 1 1 N/R 2a Execution dest ⇐ dest AND src byte PC ⇐ PC + 1 Flags Affected OF , SF , ZF , CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ANDB A n , imm8 [...]

Individual Instruction Descriptions 4-83 Assembly Language Instructions 4.14.6 ANDS Bitwise AND String Syntax [label] name dest, src [ , src1 ] Clock , clk Word , w With RPT , clk Class ANDS A n , { adrs } T able 4–46 T able 4–46 1b ANDS A n [ ~ ], A n [ ~ ] , pma16 n R +4 1 N/R 2b ANDS A n [ ~ ], A n ~ , A n n R +3 1 n R +3 3 Execution dest st[...]

Individual Instruction Descriptions 4-84 4.14.7 BEGLOOP Begin Loop Syntax [label] name Clock , clk Word , w With RPT , clk Class BEGLOOP † 1 1 N/R 9d † Loop must end with ENDLOOP . Execution Save next instruction address (PC + 1) ( mask interrupts ) PC ⇐ PC + 1 Flags Affected none Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B[...]

Individual Instruction Descriptions 4-85 Assembly Language Instructions 4.14.8 CALL Unconditional Subroutine Call Syntax [label] name address Clock , clk Word , w With RPT , clk Class CALL pma16 2 2 N/R 7c CALL * A n 2 1 N/R 7c Execution *R7 ⇐ TOS TOS ⇐ PC + 2 PC ⇐ pma16 or * A n R7 ⇐ R7 + 2 Flags Affected None Opcode Instructions 16 15 14 [...]

Individual Instruction Descriptions 4-86 4.14.9 C cc Conditional Subroutine Call Syntax [label] name address Clock , clk Word , w With RPT , clk Class C cc † pma16 2 2 N/R 7c † Cannot immediately follow a CALL instruction with a return instruction. If true If Not true [ label ] [ label ] [ label ] [ label ] [ label ] [ label ] [ label ] [ label[...]

Individual Instruction Descriptions 4-87 Assembly Language Instructions T able 4–48. Names for cc cc cc names Description cc cc name Not cc name p T rue condition ( Not true condition) 0 0 0 0 0 Z NZ Conditional on ZF=1 ( Not condition ZF=0) 0 0 0 0 1 S NS Conditional on SF=1 ( Not condition SF=0) 0 0 0 1 0 C NC Conditional on CF=1 ( Not conditio[...]

Individual Instruction Descriptions 4-88 Description If cc condition in T able 4–48 is true, PC + 2 is pushed onto the stack and the second word operand is loaded into the PC. If the condition is false, execution defaults to a NOP . A C cc instruction cannot be followed by a return (RET) instruction. No restriction applies if IRET is used instead[...]

Individual Instruction Descriptions 4-89 Assembly Language Instructions Syntax Description Alternate Syntax CRC pma16 CRNC pma16 Conditional call on RCF = 1 Conditional call on RCF = 0 CRE pma16 CRNE pma16 CRZ pma16 CRNZ pma16 Conditional call on RZF = 1 (equal) † Conditional call on RZF = 0 (not equal) † CXG pma16 CXNG pma16 CXNLE pma16 CXLE p[...]

Individual Instruction Descriptions 4-90 4.14.10 CMP Compare T wo Words [label] name src, src1 [ , mod ] Clock , clk Word , w With RPT , clk Class CMP A n , { adrs } T able 4–46 T able 4–46 1b CMP A n [ ~ ] , imm16 [ , next A ] 2 2 N/R 2b CMP CMP A n , A n ~ [ , next A ] A n ~ , A n [ , next A ] 1 1 n R +3 3 CMP † R x , imm16 2 2 N/R 4c CMP ?[...]

Individual Instruction Descriptions 4-91 Assembly Language Instructions Example 4.14.10.3 CMP R2, 0xfe20 Compare value at R2 to immediate value 0xfe20 and change the ST A T flags accordingly . Example 4.14.10.4 CMP R0, R5 Compare value at R0 to R5 and change the ST A T flags accordingly .[...]

Individual Instruction Descriptions 4-92 4.14.1 1 CMPB Compare T wo Bytes Syntax [label] name src, src1 Clock , clk Word , w With RPT , clk Class CMPB A n , imm8 1 1 N/R 2a CMPB R x , imm8 1 1 N/R 4b Execution status flags set by src – src1 byte PC ⇐ PC + 1 Flags Affected src is A n :O F , SF , ZF , CF are set accordingly src is R x : RCF , RZF[...]

Individual Instruction Descriptions 4-93 Assembly Language Instructions 4.14.12 CMPS Compare T wo Strings Syntax [ label ] name src, src1 Clock , clk Word , w With RPT , clk Class CMPS A n , { adrs } T able 4–46 T able 4–46 1b CMPS A n [~] , pma16 n S +4 2 N/R 2b CMPS CMPS A n , A n ~ A n ~ , A n n S +3 1 n R +3 3 Execution status flags set by [...]

Individual Instruction Descriptions 4-94 4.14.13 COR Correlation Filter Function Syntax [ label ] name dest, src Clock , clk Word , w With RPT , clk Class COR A n , *R x 3 1 3(n R +2) 9a Execution With RPT N–2: ( mask interrupts ) RPT counter = N–2 MR = h [0] = first filter coefficient x = sample data pointed by R x even h [1] = second filter c[...]

Individual Instruction Descriptions 4-95 Assembly Language Instructions 4.14.14 CORK Correlation Filter Function Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class CORK A n , *R x 3 1 3(n R +2) 9a Execution With RPT N–2: ( mask interrupts ) RPT counter = N–2 MR = h [0] = first filter coefficient x = sample data pointed at b[...]

Individual Instruction Descriptions 4-96 4.14.15 ENDLOOP End Loop Syntax [label] name # Clock , clk Word , w With RPT , clk Class ENDLOOP [ n ] 1 1 N/R 9d Execution If ( R4 ≥ 0) decrement R4 by n (1 or 2) PC ⇐ first address after BEGLOOP else NOP PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENDL[...]

Individual Instruction Descriptions 4-97 Assembly Language Instructions 4.14.16 EXTSGN Sign Extend W ord Syntax [label] name dest [ , mod ] Clock , clk Word , w With RPT , clk Class EXTSGN A n [~] [ , next A ] 1 1 n R +3 3 Execution [premodify AP if mod specified] new most significant word of dest ⇐ ST A T . SF PC ⇐ PC + 1 Flags Affected None O[...]

Individual Instruction Descriptions 4-98 4.14.17 EXTSGNS Sign Extend String Syntax [label] name dest Clock , clk Word , w With RPT , clk Class EXTSGNS A n [ ~ ] n R +3 1 n R +3 3 Execution new most significant word of dest ⇐ ST A T . SF PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTSGNS A n [ ~ [...]

Individual Instruction Descriptions 4-99 Assembly Language Instructions MOV AP1, 3 ; Point to loc corresponding to ; extended word in acc MOVS A0, *R0 ; R0 POINTS TO VALUE IN MEMORY EXTSGN A1 ; not string version as above Alternatively , the following code can do the same thing but requires more code: MOV AP0, 0 ; POINT TO LSW OF ACCUM STRING MOV A[...]

Individual Instruction Descriptions 4-100 4.14.18 FIR FIR Filter Function (Coefficients in RAM) Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class FIR A n , *R x 2 1 2(n R +2) 9a Execution With RPT N–2: ( mask interrupts ) RPT counter = N–2 MR = h [0] = first filter coefficient x = sample data pointed at by R x even h [1] =[...]

Individual Instruction Descriptions 4-101 Assembly Language Instructions See Also RPT , FIRK, COR, CORK Example 4.14.18.1 RPT 0 FIR A0, *R0 Computes the calculation for 2 tap FIR filter with 32-bit accumulation. See section 4.1 1 for more detail on the setup of coefficients and sample data.[...]

Individual Instruction Descriptions 4-102 4.14.19 FIRK FIR Filter Function (Coefficients in ROM) Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class FIRK A n , *R x 2 1 2(n R +2) 9a Execution With RPT N–2: ( mask interrupts ) RPT counter = N–2 MR = h [0] = first filter coefficient x = sample data pointed by R x even h [1] = [...]

Individual Instruction Descriptions 4-103 Assembly Language Instructions 4.14.20 IDLE Halt Processor Syntax [label] name Clock , clk Word , w With RPT , clk Class IDLE 1 1 N/R 9d Execution Stop processor clocks PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 987654 32 1 0 IDLE 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 Description[...]

Individual Instruction Descriptions 4-104 4.14.21 IN Input From Port Into Word Syntax [label] name dest, src1 Clock , clk Word , w With RPT , clk Class IN { adrs }, port4 T able 4–46 T able 4–46 6a IN A n [ ~ ] , port6 1 1 n R +3 6b Execution dest ⇐ content of port6 or port4 PC ⇐ PC + w Flags Affected dest is A n : OF , SF , ZF , CF are set[...]

Individual Instruction Descriptions 4-105 Assembly Language Instructions 4.14.22 INS Input From Port Into String Syntax [label] name src, src1 Clock , clk Word , w With RPT , clk Class INS A n [ ~ ] , port6 n S +2 1 n R +2 6b Execution dest ⇐ content of port6 PC ⇐ PC + 1 Flags Affected dest is A n: OF , SF , ZF , CF are set accordingly Opcode I[...]

Individual Instruction Descriptions 4-106 4.14.23 INTD Interrupt Disable Syntax [label] name Clock , clk Word , w With RPT , clk Class INTD 1 1 N/R 9d Execution ST A T . IM ⇐ 0 ( IM is ST A T bit 4) PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTD 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 Description Dis[...]

Individual Instruction Descriptions 4-107 Assembly Language Instructions 4.14.24 INTE Interrupt Enable Syntax [label] name Clock , clk Word , w With RPT , clk Class INTE 1 1 N/R 9d Execution ST A T . IM ⇐ 1 ( IM is ST A T bit 4) PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 987654 32 1 0 INTE 1 1 1 1 1 1 1 1 0 1 0 0 0[...]

Individual Instruction Descriptions 4-108 4.14.25 IRET Return From Interrupt Syntax [label] name Clock , clk Word , w With RPT , clk Class IRET 2 1 N/R 5 Execution PC ⇐ TOS R7 ⇐ R7 – 2 TOS ⇐ *R7 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRET 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 0 See Also RET , CALL, C cc ,[...]

Individual Instruction Descriptions 4-109 Assembly Language Instructions 4.14.26 J cc Conditional Jumps Syntax [label] name pma16 [, Rmod ] Clock , clk Word , w With RPT , clk Class J cc pma16 [, Rmod ] 2 2 N/R 7b If true If N ot true [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [la[...]

Individual Instruction Descriptions 4-1 10 Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 J cc pma16 1 0 0 0 0 0 Not cc 0 0 0 0 0 x pma16 J cc pma16 , R x ++ 1 0 0 0 0 0 Not cc R x 0 1 x pma16 J cc pma16 , R x –– 1 0 0 0 0 0 Not cc R x 1 0 x pma16 J cc pma16 , R x ++R5 1 0 0 0 0 0 Not cc R x 1 1 x pma16 cc names Descri p tion cc c[...]

Individual Instruction Descriptions 4-1 1 1 Assembly Language Instructions cc names Descri p tion cc cc name Not cc name Description T rue condition ( Not true condition) 1 1 1 0 0 reserved 1 1 1 0 1 reserved 1 1 1 1 0 reserved 1 1 1 1 1 reserved Description PC is replaced with second word operand if condition is true (or unconditional). If test co[...]

Individual Instruction Descriptions 4-1 12 Syntax Description Alternate Instruction JRNLZP pma16 [, Rmod ] Conditional jump on R x ≥ 0 after post-mod JRZP pma16 [, Rmod ] Conditional jump on R x = 0 after post-mod JRNZP pma16 [, Rmod ] Conditional jump on R x ≠ 0 after post-mod JS pma16 [, Rmod ] Conditional jump on SF = 1 JNS pma16 [, Rmod ] C[...]

Individual Instruction Descriptions 4-1 13 Assembly Language Instructions 4.14.27 JMP Unconditional Jump Syntax [label] name dest [, mod ] Clock , clk Word , w With RPT , clk Class JMP pma16 2 2 N/R 7b JMP pma16 , R x ++ 2 2 N/R 7b JMP pma16, R x –– 2 2 N/R 7b JMP pma16, R x ++R5 2 2 N/R 7b JMP * A n 2 1 N/R 7b Execution PC ⇐ dest [Post–mod[...]

Individual Instruction Descriptions 4-1 14 4.14.28 MOV Move Data Word From Source to Destination Syntax [label] name dest, src, [, next A ] Clock , clk Word , w With RPT , clk Class MOV { adrs } , A n [ ~ ] [, next A ] T able 4–46 T able 4–46 1a MOV A n [ ~ ] , { adrs } [, next A ] T able 4–46 T able 4–46 1a MOV { adrs } , *A n T able 4–4[...]

Individual Instruction Descriptions 4-1 15 Assembly Language Instructions [label] Class With RPT , clk Word , w Clock , clk dest, src, [, next A ] name MOV TF n , { cc } [ , R x ] 1 1 N/R 8b MOV STR, imm8 1 1 N/R 9b MOV SV , imm4 1 1 N/R 9b MOV AP n , imm5 1 1 N/R 9c Execution [premodify AP if mod specified] dest ⇐ src PC ⇐ PC + w Flags Affecte[...]

Individual Instruction Descriptions 4-1 16 Instructions 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MOV R x , R5 1 1 1 1 1 1 1 0 0 1 1 0 R x 0 0 MOV SV , imm4 1 1 1 1 1 1 0 1 0 0 0 0 0 imm4 MOV SV , { adrs } 4 1 1 0 1 1 0 0 0 0 adrs x dma16 (for direct) or offset16 (long relative) [see section 4.13] MOV PH , { adrs } 1 1 0 1 1 0 0 0 1 adrs x dma16 (fo[...]

Individual Instruction Descriptions 4-1 17 Assembly Language Instructions Description Copy value of src to dest . Premodification of accumulator pointers is allowed with some operand types. Syntax Description MOV A n [ ~ ], { adrs } [, next A ] Move data memory word to A n [ ~ ] † MOV { adrs }, A n [ ~ ] [, next A ] Move A n [ ~ ] word to data me[...]

Individual Instruction Descriptions 4-1 18 Syntax Description MOV STR , imm8 Move immediate byte to String Register ( STR ) MOV AP n , imm5 Move immediate 5-bit value to AP n register † Accumulator condition flags are modified to reflect the value loaded into either A n or A n ~ . ‡ Signed multiplier mode resets UM (bit 1 in status register) to[...]

Individual Instruction Descriptions 4-1 19 Assembly Language Instructions Example 4.14.28.13 MOV R1, 0x0200 * 2 Load immediate word memory address 0x0200 to R1 . Example 4.14.28.14 MOV R7, (0x0280 – 32) * 2 Load R7 (stack register) with the starting value of stack, i.e., 0x0260. Example 4.14.28.15 MOV *0x0200 * 2, R0 Store R0 to data memory word [...]

Individual Instruction Descriptions 4-120 4.14.29 MOV APH Move With Adding PH Syntax [label] name dest, src, src1 Clock , clk Word , w With RPT , clk Class MOV APH A n , MR, { adrs } T able 4–46 T able 4–46 1b Execution A n ⇐ A n + PH MR ⇐ contents of { adrs } PC ⇐ PC + w Flags Affected T AG, OF , SF , ZF , CF are set accordingly Opcode I[...]

Individual Instruction Descriptions 4-121 Assembly Language Instructions 4.14.30 MOV APHS Move With Adding PH Syntax [label] name dest, src, src1 Clock , clk Word , w With RPT , clk Class MOV APHS A n , MR, { adrs } T able 4–46 T able 4–46 1b Execution A n ⇐ A n + PH MR ⇐ contents of { adrs } PC ⇐ PC + w Flags Affected T AG, OF , SF , ZF [...]

Individual Instruction Descriptions 4-122 4.14.31 MOVB Move Byte From Source to Destination Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class MOVB A n , { adrs } T able 4–46 T able 4–46 1b MOVB { adrs } , A n T able 4–46 T able 4–46 1b MOVB A n , imm8 1 1 N/R 2a MOVB MR, imm8 1 1 N/R 2a MOVB R x , imm8 1 1 N/R 2b Execu[...]

Individual Instruction Descriptions 4-123 Assembly Language Instructions Example 4.14.29.2 MOVB *R2, A0 Copy lower 8 bits of accumulator A0 to the data memory byte pointed by R2 . Example 4.14.29.3 MOVB A0, 0xf2 Load accumulator A0 with value of 0xf2. Example 4.14.29.4 MOVB MR, 34 Load MR register with immidiate value of 34 (decimal). Example 4.14.[...]

Individual Instruction Descriptions 4-124 4.14.32 MOVBS Move Byte String from Source to Destination Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class MOVBS A n , { adrs } 8 T able 4–46 T able 4–46 1b MOVBS { adrs } , A n T able 4–46 T able 4–46 1b Execution dest ⇐ src PC ⇐ PC + w Flags Affected dest is A n : OF , S[...]

Individual Instruction Descriptions 4-125 Assembly Language Instructions 4.14.33 MOVS Move String from Source to Destination Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class MOVS A n [ ~ ] , { adrs } T able 4–46 T able 4–46 1a MOVS { adrs } , A n [ ~ ] T able 4–46 T able 4–46 1a MOVS { adrs } , *A n T able 4–46 T ab[...]

Individual Instruction Descriptions 4-126 Description Copy value of src string to dest string. Premodification of accumulator pointers is allowed with some operand types. Syntax Description MOVS A n [ ~ ] , { adrs } Move data memory word string to A n [ ~ ] string MOVS { adrs } , A n [ ~ ] Move A n [ ~ ] string to data memory MOVS { adrs } , *A n M[...]

Individual Instruction Descriptions 4-127 Assembly Language Instructions 4.14.34 MOVSPH Move With Subtract from PH Syntax [label] name dest, src, src1 Clock , clk Word , w With RPT , clk Class MOVSPH A n , MR, { adrs } T able 4–46 T able 4–46 1b Execution A n ⇐ A n – PH MR ⇐ contents of { adrs } PC ⇐ PC + w Flags Affected T AG, OF , SF [...]

Individual Instruction Descriptions 4-128 4.14.35 MOVSPHS Move String With Subtract From PH Syntax [label] name dest, src, src1 Clock , clk Word , w With RPT , clk Class MOVSPHS A n , MR, { adrs } T able 4–46 T able 4–46 1b Execution A n ⇐ A n (second word) – PH MR ⇐ contents of { adrs} PC ⇐ PC + w Flags Affected T AG, OF , SF , ZF , CF[...]

Individual Instruction Descriptions 4-129 Assembly Language Instructions 4.14.36 MOVT Move T ag From Source to Destination Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class MOVT { adrs }, TF n T able 4–46 T able 4–46 5 Execution dest ⇐ src PC ⇐ PC + w Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6[...]

Individual Instruction Descriptions 4-130 4.14.37 MOVU Move Data Unsigned Syntax [label] name dest, src [, mod ] Clock , clk Word , w With RPT , clk Class MOVU MR, A n [ ~ ] [ , next A ] 1 1 n R +3 3 MOVU MR, { adrs } T able 4–46 T able 4–46 5 Execution [premodify AP if mod specified] dest ⇐ src PC ⇐ PC + w Flags Affected src is { adrs } T [...]

Individual Instruction Descriptions 4-131 Assembly Language Instructions Figure 4–8. V alid Moves/T ransfer in MSP50P614/MSP50C614 Instruction Set PH An Rx APn STR MR/SV Immediate B B B S B S S B ROM RAM S I/O xxxxxx xxxx00 ST A T TOS B Flag Bit NOTE: B = Byte move possible. S = String move possible. R5 can be moved to Rx, An[–] to An[–][...]

Individual Instruction Descriptions 4-132 4.14.38 MUL Multiply (Rounded) Syntax [label] name src [, mod ] Clock , clk Word , w With RPT , clk Class MUL A n [ ~ ] [ , next A ] 1 1 n R +3 3 MUL { adrs } T able 4–46 T able 4–46 5 Execution [premodify AP if mod specified] PH , PL ⇐ MR * src PC ⇐ PC + w Flags Affected src is A n : OF , SF , ZF ,[...]

Individual Instruction Descriptions 4-133 Assembly Language Instructions 4.14.39 MULS Multiply String With No Data T ransfer Syntax [label] name src Clock , clk Word , w With RPT , clk Class MULS A n [~] n S +3 1 n R +3 3 Execution PH , PL ⇐ MR * src string PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2[...]

Individual Instruction Descriptions 4-134 4.14.40 MULAPL Multiply and Accumulate Result Syntax [label] name dest, src [ , mod ] Clock , clk Word , w With RPT , clk Class MULAPL A n , { adrs } T able 4–46 T able 4–46 1b MULAPL A n [ ~ ] , A n [ ~ ] [ , next A ] 1 1 n R +3 3 Execution [premodify AP if mod specified] PH , PL ⇐ MR * src dest ⇐ [...]

Individual Instruction Descriptions 4-135 Assembly Language Instructions 4.14.41 MULAPLS Multiply String and Accumulate Result Syntax [label] name dest, src [ , mod ] Clock , clk Word , w With RPT , clk Class MULAPLS A n , { adrs } T able 4–46 T able 4–46 1b MULAPLS A n [ ~ ] , A n [ ~ ] n S +3 1 n R +3 3 Execution PH , PL ⇐ MR * src dest ⇐[...]

Individual Instruction Descriptions 4-136 4.14.42 MULSPL Multiply and Subtract PL From Accumulator Syntax [label] name dest, src [ , mod ] Clock , clk Word , w With RPT , clk Class MULSPL A n , { adrs } T able 4–46 T able 4–46 1b MULSPL A n [ ~ ] , A n [ ~ ] [, next A ] 1 1 n R +3 3 Execution [premodify AP if mod specified] PH , PL ⇐ MR * src[...]

Individual Instruction Descriptions 4-137 Assembly Language Instructions 4.14.43 MULSPLS Multiply String and Subtract PL From Accumulator Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class MULSPLS A n , { adrs } T able 4–46 T able 4–46 1b MULSPLS A n [ ~ ] , A n [ ~ ] n S +3 1 n R +3 3 Execution PH , PL ⇐ MR * src dest ?[...]

Individual Instruction Descriptions 4-138 4.14.44 MUL TPL Multiply and T ransfer PL to Accumulator Syntax [label] name dest, src [ , mod ] Clock , clk Word , w With RPT , clk Class MUL TPL A n , { adrs } T able 4–46 T able 4–46 1b MUL TPL A n [ ~ ] , A n [ ~ ] [, next A ] 1 1 n R +3 3 Execution [premodify AP if mod specified] PH , PL ⇐ MR * s[...]

Individual Instruction Descriptions 4-139 Assembly Language Instructions 4.14.45 MUL TPLS Multiply String and T ransfer PL to Acumulator Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class MUL TPLS A n , { adrs } T able 4–46 T able 4–46 1b MUL TPLS A n [ ~ ] , A n [ ~ ] n S +3 1 n R +3 3 Execution PH , PL ⇐ MR * src A n ?[...]

Individual Instruction Descriptions 4-140 4.14.46 NEGAC T wo’ s Complement Negation of Accumulator Syntax [label] name dest, src [,mod] Clock , clk Word , w With RPT , clk Class NEGAC A n [ ~ ] , A n [ ~ ] [, next A ] n S +3 1 n R +3 3 Execution [premodify AP if mod specified] dest ⇐ – src PC ⇐ PC + 1 Flags Affected OF , SF , ZF , CF are se[...]

Individual Instruction Descriptions 4-141 Assembly Language Instructions 4.14.47 NEGACS T wo’ s Complement Negation of Accumulator String Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class NEGACS A n [ ~ ] , A n [ ~ ] n S +3 1 n R +3 3 Execution dest ⇐ – src PC ⇐ PC + 1 Flags Affected OF , SF , ZF , CF are set according[...]

Individual Instruction Descriptions 4-142 4.14.48 NOP No Operation Syntax [label] name Clock , clk Word , w With RPT , clk Class NOP 1 1 n R +3 9d Execution PC ⇐ PC + 1 (No operation) Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Description This instruction performs no oper[...]

Individual Instruction Descriptions 4-143 Assembly Language Instructions 4.14.49 NOT AC One’ s Complement Negation of Accumulator Syntax [label] name dest, src [ , mod ] Clock , clk Word , w With RPT , clk Class NOT AC A n [ ~ ] , A n [ ~ ] [, next A ] 1 1 n R +3 3 Execution [premodify AP if mod specified] dest ⇐ NOT src PC ⇐ PC + 1 Flags Aff[...]

Individual Instruction Descriptions 4-144 4.14.50 NOT ACS One’ s Complement Negation of Accumulator String Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class NOT ACS A n [ ~ ] , A n [ ~ ] n S +2 1 n R +2 3 Execution dest ⇐ NOT src PC ⇐ PC + 1 Flags Affected OF , SF , ZF , CF are set accordingly Opcode Instructions 16 15 1[...]

Individual Instruction Descriptions 4-145 Assembly Language Instructions 4.14.51 OR Bitwise Logical OR Syntax [label] name dest, src [, src1] [, mod] Clock , clk Word , w With RPT , clk Class OR A n , { adrs } T able 4–46 T able 4–46 1b OR A n [ ~ ] , A n [ ~ ] , imm16 [, next A ] 2 2 N/R 2b OR A n [ ~ ] , A n ~, A n [ , next A ] 1 1 n R +3 3 O[...]

Individual Instruction Descriptions 4-146 See Also ORB, ORS, AND, ANDS, XOR, XORS, NOT AC, NOT ACS Example 4.14.51.1 OR A0, *R0++R5 OR accumulator A0 with the value in data memory address stored in R0 and store result in accumulator A0 , Add R5 to R0 after execution. Example 4.14.51.2 OR A1, A1, 0xF0FF, ++A Preincrement pointer AP1 . OR immediate 0[...]

Individual Instruction Descriptions 4-147 Assembly Language Instructions 4.14.52 ORB Bitwise OR Byte Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class ORB A n , imm8 1 1 N/R 2a Execution dest ⇐ dest OR src PC ⇐ PC + 1 Flags Affected OF , SF , ZF , CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 [...]

Individual Instruction Descriptions 4-148 4.14.53 ORS Bitwise OR String Syntax [label] name dest, src [, src1 ] Clock , clk Word , w With RPT , clk Class ORS A n , { adrs } T able 4–46 T able 4–46 1b ORS A n [ ~ ] , A n [ ~ ] , pma16 n S +4 2 N/R 2b ORS A n [ ~ ] , A n ~, A n n S +2 1 n R +2 3 Execution dest ⇐ dest OR src (for two operands) d[...]

Individual Instruction Descriptions 4-149 Assembly Language Instructions 4.14.54 OUT Output to Port Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class OUT port4 , { adrs } T able 4–46 n R +3 6a OUT port6 , A n [ ~ ] T able 4–46 n R +3 6a Execution port4 or port6 ⇐ src PC ⇐ PC + w Flags Affected XSF , XZF are set accordi[...]

Individual Instruction Descriptions 4-150 4.14.55 OUTS Output String to Port Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class OUTS port6 , A n [ ~ ] n R +2 1 n R +2 6b Execution port6 ⇐ src PC ⇐ PC + 1 Flags Affected XSF , XZF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OUTS port6 , A [...]

Individual Instruction Descriptions 4-151 Assembly Language Instructions 4.14.56 RET Return From Subroutine (CALL, C cc ) Syntax [label] name Clock , clk Word , w With RPT , clk Class RET 1 1 N/R 5 Execution PC ⇐ TOS R7 ⇐ R7 – 2 TOS ⇐ *R7 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RET 1 1 0 1 1 1 1 0 0 [...]

Individual Instruction Descriptions 4-152 4.14.57 RFLAG Reset Memory Flag Syntax [label] name src Clock , clk Word , w With RPT , clk Class RFLAG { flagadrs } 1 1 N/R 8a Execution memory flag bit at { flagadrs } data memory location ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFLAG {flagadrs}[...]

Individual Instruction Descriptions 4-153 Assembly Language Instructions 4.14.58 RFM Reset Fractional Mode Syntax [label] name Clock , clk Word , w With RPT , clk Class RFM 1 1 N/R 9d Execution ST A T . FM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Descr[...]

Individual Instruction Descriptions 4-154 4.14.59 ROVM Reset Overflow Mode Syntax [label] name Clock , clk Word , w With RPT , clk Class ROVM 1 1 N/R 9d Execution ST A T . OM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Description Resets overflow mode in [...]

Individual Instruction Descriptions 4-155 Assembly Language Instructions 4.14.60 RPT Repeat Next Instruction Syntax [label] name src Clock , clk Word , w With RPT , clk Class RPT { adrs } 8 T able 4–46 N/R 5 RPT imm8 1 1 N/R 9b Execution IF RPT { adrs } 8 load src to repeat counter . ELSE load imm8 to repeat counter . ( mask interrupt ) repeat ne[...]

Individual Instruction Descriptions 4-156 4.14.61 RT AG Reset T ag Syntax [label] name dest Clock , clk Word , w With RPT , clk Class RT AG { adrs } T able 4–46 T able 4–46 5 Execution memory tag bit at { adrs } data memory location ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RT AG { adrs[...]

Individual Instruction Descriptions 4-157 Assembly Language Instructions 4.14.62 RXM Reset Extended Sign Mode Syntax [label] name Clock , clk Word , w With RPT , clk Class RXM 1 1 N/R 9d Execution ST A T . XM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXM 1 1 1 1 1 1 1 1 0 1 0 1 1 0 0 0 0 De[...]

Individual Instruction Descriptions 4-158 4.14.63 SFLAG Set Memory Flag Syntax [label] name dest Clock , clk Word , w With RPT , clk Class SFLAG { flagadrs } 1 1 N/R 8a Execution memory flag bit at { flagadrs } data memory location ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SFLAG {flagadrs} [...]

Individual Instruction Descriptions 4-159 Assembly Language Instructions 4.14.64 SFM Set Fractional Mode Syntax [label] name Clock , clk Word , w With RPT , clk Class SFM 1 1 N/R 9d Execution ST A T . FM ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXM 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 Descrip[...]

Individual Instruction Descriptions 4-160 4.14.65 SHL Shift Left Syntax [label] name dest [, mod] Clock , clk Word , w With RPT , clk Class SHL A n [ ~ ] [ , next A ] 1 1 n R +3 3 Execution [premodify AP if mod specified] PH , PL ⇐ src << SV PC ⇐ PC + 1 Flags Affected OF , SF , ZF , CF are set accordingly Opcode Instructions 16 15 14 13 1[...]

Individual Instruction Descriptions 4-161 Assembly Language Instructions 4.14.66 SHLAC Shift Left Accumulator Syntax [label] name dest, src [, mod ] Clock , clk Word , w With RPT , clk Class SHLAC A n [ ~ ] , A n [ ~ ] [ , next A ] 1 1 n R +3 3 Execution [premodify AP if mod specified] dest ⇐ src << 1 PC ⇐ PC + 1 Flags Affected OF , SF , [...]

Individual Instruction Descriptions 4-162 4.14.67 SHLACS Shift Left Accumulator String Individually Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class SHLACS A n [ ~ ] , A n [ ~ ] n S +2 1 n R +2 3 Execution dest ⇐ src << 1 PC ⇐ PC + 1 Flags Affected OF , SF , ZF , CF are set accordingly Opcode Instructions 16 15 14 1[...]

Individual Instruction Descriptions 4-163 Assembly Language Instructions 4.14.68 SHLAPL Shift Left with Accumulate Syntax [label] name dest , src [, mod ] Clock , clk Word , w With RPT , clk Class SHLAPL A n , { adrs } T able 4–46 T able 4–46 1b SHLAPL A n [ ~ ] , A n [ ~ ] [ , next A ] 1 1 n R +3 3 Execution [premodify AP if mod specified] PH [...]

Individual Instruction Descriptions 4-164 4.14.69 SHLAPLS Shift Left String With Accumulate Syntax [label] name dest , src Clock , clk Word , w With RPT , clk Class SHLAPLS A n , { adrs } T able 4–46 T able 4–46 1b SHLAPLS A n [ ~ ] , A n [ ~ ] n S +3 1 n R +3 3 Execution PH , PL ⇐ src << SV dest ⇐ dest + PL PC ⇐ PC + 1 Flags Affect[...]

Individual Instruction Descriptions 4-165 Assembly Language Instructions 4.14.70 SHLS Shift Left Accumulator String to Product Syntax [label] name dest Clock , clk Word , w With RPT , clk Class SHLS A n [ ~ ] n S +3 1 n R +3 3 Execution PH , PL ⇐ src << SV PC ⇐ PC + 1 Flags Affected OF , SF , ZF , CF are set accordingly Opcode Instruction[...]

Individual Instruction Descriptions 4-166 4.14.71 SHLSPL Shift Left With Subtract PL Syntax [label] name dest , src [, mod ] Clock , clk Word , w With RPT , clk Class SHLSPL A n , { adrs } T able 4–46 T able 4–46 1b SHLSPL A n [ ~ ] , A n [ ~ ] [ , next A ] 1 1 n R +3 3 Execution [premodify AP if mod specified] PH , PL ⇐ src << SV dest [...]

Individual Instruction Descriptions 4-167 Assembly Language Instructions 4.14.72 SHLSPLS Shift Left String With Subtract PL Syntax [label] name dest , src Clock , clk Word , w With RPT , clk Class SHLSPLS A n , { adrs } T able 4–46 T able 4–46 1b SHLSPLS A n [ ~ ] , A n [ ~ ] n S +3 1 n R +3 3 Execution PH , PL ⇐ src << SV dest ⇐ dest[...]

Individual Instruction Descriptions 4-168 4.14.73 SHL TPL Shift Left and T ransfer PL to Accumulator Syntax [label] name dest , src [, mod ] Clock , clk Word , w With RPT , clk Class SHL TPL A n , { adrs } T able 4–46 T able 4–46 1b SHL TPL A n [ ~ ] , A n [ ~ ] [ , next A ] 1 1 n R +3 3 Execution [premodify AP if mod specified] PH , PL ⇐ src[...]

Individual Instruction Descriptions 4-169 Assembly Language Instructions 4.14.74 SHL TPLS Shift Left String and T ransfer PL to Accumulator Syntax [label] name dest , src Clock , clk Word , w With RPT , clk Class SHL TPLS A n , { adrs } T able 4–46 T able 4–46 1b SHL TPLS A n [ ~ ] , A n [ ~ ] n S +3 1 n R +3 3 Execution PH , PL ⇐ src <<[...]

Individual Instruction Descriptions 4-170 4.14.75 SHRAC Shift Accumulator Right Syntax [label] name dest, src, [, mod ] Clock , clk Word , w With RPT , clk Class SHRAC A n [ ~ ] , A n [ ~ ] [ , next A ] 1 1 n R +3 3 Execution [premodify AP if mod specified] dest ⇐ src >> 1 PC ⇐ PC + 1 Flags Affected OF , SF , ZF , CF are set accordingly O[...]

Individual Instruction Descriptions 4-171 Assembly Language Instructions 4.14.76 SHRACS Shift Accumulator String Right Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class SHRACS A n [ ~ ] , A n [ ~ ] n S +3 1 n R +3 3 Execution dest ⇐ src >> 1 PC ⇐ PC + 1 Flags Affected OF , SF , ZF , CF are set accordingly Opcode Inst[...]

Individual Instruction Descriptions 4-172 4.14.77 SOVM Set Overflow Mode Syntax [label] name Clock , clk Word , w With RPT , clk Class SOVM 1 1 N/R 9d Execution ST A T .OM ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOVM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Description Sets overflow mode in stat[...]

Individual Instruction Descriptions 4-173 Assembly Language Instructions 4.14.78 ST AG Set T ag Syntax [label] name dest Clock , clk Word , w With RPT , clk Class ST AG { adrs } T able 4–46 T able 4–46 5 Execution memory tag bit at address adrs ⇐ 1 PC ⇐ PC + w Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [...]

Individual Instruction Descriptions 4-174 4.14.79 SUB Subtract Syntax [label] name dest, src , src1 , [ next A ]] Clock , clk Word , w With RPT , clk Class SUB A n [ ~ ] , A n , { adrs } [ , next A ] T able 4–46 T able 4–46 1a SUB A n [ ~ ] , A n [ ~ ] , imm16 [, next A ] 2 2 N/R 2b SUB A n [ ~ ] , A n [ ~ ] , PH [, next A ] 1 1 n R +3 3 SUB A [...]

Individual Instruction Descriptions 4-175 Assembly Language Instructions Syntax Description SUB A n [ ~ ] , A n , { adrs } [, next A ] Subtract effective data memory word from A n [ ~ ], store result in A n SUB A n [ ~ ] , A n [ ~ ] , imm16 [, next A ] Subtract immediate word from A n [ ~ ], store result in A n [ ~ ] SUB A n [ ~ ] , A n [ ~ ] , PH [...]

Individual Instruction Descriptions 4-176 4.14.80 SUBB Subtract Byte Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class SUBB A n , imm8 1 1 N/R 2a SUBB R x , imm8 1 1 N/R 4b Execution dest ⇐ dest – imm8 PC ⇐ PC + 1 Flags Affected dest is A n : OF , SF , ZF , CF are set accordingly dest is R x : RCF , RZF are set according[...]

Individual Instruction Descriptions 4-177 Assembly Language Instructions 4.14.81 SUBS Subtract Accumulataor String Syntax [label] name dest, src, src1 Clock , clk Word , w With RPT , clk Class SUBS A n [ ~ ] , A n , { adrs } T able 4–46 T able 4–46 1a SUBS A n [ ~ ] , A n [ ~ ] , pma16 n s +4 2 N/R 32b SUBS A n [ ~ ] , A n , A n ~ n s +2 1 n R [...]

Individual Instruction Descriptions 4-178 Syntax Description SUBS A n [ ~ ] , A n , { adrs } Subtract data memory string from A n string, store result in A n [ ~ ] string SUBS A n [ ~ ] , A n [ ~ ] , pma16 Subtract program memory string from A n [ ~ ] string, store result in A n [ ~ ] string SUBS A n [ ~ ] , A n , A n ~ Subtract A n ~ string from A[...]

Individual Instruction Descriptions 4-179 Assembly Language Instructions 4.14.82 SXM Set Extended Sign Mode Syntax [label] name Clock , clk Word , w With RPT , clk Class SXM 1 1 N/R 9d Execution ST A T .XM ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SXM 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 0 Descr[...]

Individual Instruction Descriptions 4-180 4.14.83 VCALL V ectored Call Syntax [label] name dest Clock , clk Word , w With RPT , clk Class VCALL vector8 2 1 N/R 7a Execution Push PC + 1 PC ⇐ *(0x7F00 + vector8 ) R7 ⇐ R7 + 2 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VCALL vector8 1 1 1 1 1 1 1 0 1 vector8 De[...]

Individual Instruction Descriptions 4-181 Assembly Language Instructions 4.14.84 XOR Logical XOR Syntax [label] name dest, src, src1 [, mod ] Clock , clk Word , w With RPT , clk Class XOR A n , { adrs } T able 4–46 T able 4–46 1a XOR A n [ ~ ] , A n [ ~ ] , imm16 [ , next A ] 2 2 N/R 2b XOR A n [ ~ ] , A n ~, A n [ , next A ] 1 1 n R +3 3 XOR T[...]

Individual Instruction Descriptions 4-182 See Also XORB, XORS, AND, ANDS, OR, ORS, ORB, NOT AC, NOT ACS Example 4.14.84.1 XOR A1, A1, 0x13FF XOR immediate value 0x13FF to A1 and store result in A1 . Example 4.14.84.2 XOR A0, A0, 2, ++A Pre–increment pointer AP0 , then XOR immediate value 2 to new A0 and store result in A0 . Example 4.14.84.3 XOR [...]

Individual Instruction Descriptions 4-183 Assembly Language Instructions 4.14.85 XORB Logical XOR Byte Syntax [label] name dest, src Clock , clk Word , w With RPT , clk Class XORB A n , imm8 1 1 N/R 2a Execution A n ⇐ A n XOR imm8 (for two operands) PC ⇐ PC + 1 Flags Affected dest is A n : OF , SF , ZF , CF are set accordingly Opcode Instructio[...]

Individual Instruction Descriptions 4-184 4.14.86 XORS Logical XOR String Syntax [label] name dest, src [ , src1 ] Clock , clk Word , w With RPT , clk Class XORS A n , { adrs } T able 4–46 T able 4–46 1b XORS A n [ ~ ] , A n [ ~ ] , pma16 n S +4 2 N/R 2b XORS A n [ ~ ] , A n ~, A n n S +3 1 n R +3 3 Execution dest ⇐ dest XOR src (for two oper[...]

Individual Instruction Descriptions 4-185 Assembly Language Instructions 4.14.87 ZAC Zero Accumulator Syntax [label] name dest [ , mod ] Clock , clk Word , w With RPT , clk Class ZAC A n [ ~ ] [ , next A ] 1 1 n R +3 3 Execution [premodify AP if mod specified] dest ⇐ 0 PC ⇐ PC + 1 Flags Affected ZF = 1 Instructions 16 15 14 13 12 11 10 9 8 7 6 [...]

Individual Instruction Descriptions 4-186 4.14.88 ZACS Zero Accumulator String Syntax [label] name dest Clock , clk Word , w With RPT , clk Class ZAC A n n S +3 1 n R +3 3 Execution dest ⇐ 0 PC ⇐ PC + 1 Flags Affected ZF = 1 Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ZACS A n [ ~ ] 1 1 1 0 0 1 1 A n 0 0 0 1 1 0 0 ~A Description Zero [...]

Instruction Set Encoding 4-187 Assembly Language Instructions 4.15 Instruction Set Encoding Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADD A n [~], A n , { adrs } [, next A ] 1 1 1 0 ~A next A A n adrs x dma16 (for direct) or offset16 (long relative) [see section 4.13] ADD A n [~], A n [~], imm16 [, next A ] 1 1 1 0 0 next A A n 0 0 0 0 [...]

Instruction Set Encoding 4-188 Instructions 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CMP A n , { adrs } 0 1 0 1 1 0 0 A n adrs x dma16 (for direct) or offset16 (long relative) [see section 4.13] CMP A n [~], imm16 [, next A ] 1 1 1 0 0 next A A n 0 1 1 0 0 1 A~ ~A x imm16 CMP A n , A n ~ [, next A ] 1 1 1 0 0 next A A n 1 0 0 0 0 0 0 0 CMP A n ~, A[...]

Instruction Set Encoding 4-189 Assembly Language Instructions Instructions 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 JMP pma16 , R x –– 1 0 0 0 0 0 0 1 0 1 0 1 R x 1 0 x pma16 JMP pma16 , R x ++R5 1 0 0 0 0 0 0 1 0 1 0 1 R x 1 1 x pma16 JMP *A n 1 0 0 0 1 0 0 A n 0 0 0 0 0 0 0 0 J cc pma16 1 0 0 0 0 0 Not cc 0 0 0 0 0 x pma16 J cc pma16 , R x ++[...]

Instruction Set Encoding 4-190 Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOV PH , { adrs } 1 1 0 1 1 0 0 0 1 adrs x dma16 (for direct) or offset16 (long relative) [see section 4.13] MOV MR , { adrs } 1 1 0 1 1 1 0 0 0 adrs x dma16 (for direct) or offset16 (long relative) [see section 4.13] MOV AP n , { adrs } 1 1 0 1 1 0 1 AP n adrs x d[...]

Instruction Set Encoding 4-191 Assembly Language Instructions Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOVB { adrs }, A n x dma16 (for direct) or offset16 (long relative) [see section 4.13] MOVB A n , imm8 1 0 1 0 0 0 1 A n imm8 MOVB MR , imm8 1 0 1 0 1 1 1 A n imm8 MOVB R x , imm8 1 0 1 1 1 0 k4 k3 k2 k7 k6 k5 R x k1 k0 MOVBS A n , { [...]

Instruction Set Encoding 4-192 Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MUL { adrs } 1 1 0 1 1 1 0 1 1 adrs x dma16 (for direct) or offset16 (long relative) [see section 4.13] MULR { adrs } 1 1 0 1 1 1 0 1 0 adrs x dma16 (for direct) or offset16 (long relative) [see section 4.13] MULS A n [~] 1 1 1 0 0 1 1 A n 1 1 1 1 0 0 A~ 0 MULAPL A[...]

Instruction Set Encoding 4-193 Assembly Language Instructions Instructions 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ORS A n [~], A n [~], pma16 1 1 1 0 0 1 1 A n 1 0 0 0 0 1 A~ ~A ORS A n [~], A n ~, A n 1 1 1 0 0 1 1 A n 0 1 0 0 1 0 A~ ~A OUT port4 , { adrs } 1 1 0 0 1 port4 adrs x dma16 (for direct) or offset16 (long relative) [see section 4.13] [...]

Instruction Set Encoding 4-194 Instructions 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SHL TPLS A n [~], A n [~] 1 1 1 0 0 1 1 A n 1 1 0 1 0 0 A~ ~A SHLAC A n [~], A n [~] [, next A ] 1 1 1 0 0 next A A n 0 0 1 1 0 0 A~ ~A SHLACS A n [~], A n [~] 1 1 1 0 0 1 1 A n 0 0 1 1 0 0 A~ ~A SHRAC A n [~], A n [~] [, next A ] 1 1 1 0 0 next A A n 0 1 0 1 1 0 A[...]

Instruction Set Encoding 4-195 Assembly Language Instructions Instructions 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ZAC A n [~] [, next A ] 1 1 1 0 0 next A A n 0 0 0 1 1 0 0 ~A ZACS A n [~] 1 1 1 0 0 1 1 A n 0 0 0 1 1 0 0 ~A cc names Description T r e condition ( Nt tr e condition) cc cc name Not cc name T rue con di t i on ( N ot true con di t i [...]

Instruction Set Summary 4-196 4.16 Instruction Set Summary Use the legend in Section 4.13 and the following table to obtain a summary of each instruction and its format. For detail about the instruction refer to the detail description of the instruction. name dest [, src] [, src1] [,mod] Clock , clk Words , w With RPT , clk Class ADD A n [~], A n ,[...]

Instruction Set Summary 4-197 Assembly Language Instructions name Class With RPT , clk Words , w Clock , clk dest [, src] [, src1] [,mod] CMP R x , imm16 2 2 N/R 2b CMP A n [~], A n [~] [, next A ] 1 1 N/R 3 CMP A n [~], imm16 [, next A ] 2 2 N/R 4c CMP R x , R5 1 1 N/R 4d CMPB A n , imm8 1 1 N/R 2a CMPB R x , imm8 1 1 N/R 4b CMPS A n , { adrs } T [...]

Instruction Set Summary 4-198 name Class With RPT , clk Words , w Clock , clk dest [, src] [, src1] [,mod] MOV { adrs }, A n [~] [, next A ] T able 4–46 T able 4–46 1a MOV A n [~], { adrs } [, next A ] T able 4–46 T able 4–46 1a MOV { adrs }, *A n T able 4–46 T able 4–46 1b MOV A n [~], imm16 [, next A ] 2 2 N/R 2b MOV MR , imm16 [, nex[...]

Instruction Set Summary 4-199 Assembly Language Instructions name dest [, src] [, src1] [,mod] Clock , clk Words , w With RPT , clk Class MOV { adrs }, SV T able 4–46 T able 4–46 5 MOV { adrs }, AP n T able 4–46 T able 4–46 5 MOV { adrs }, TOS T able 4–46 T able 4–46 5 MOV STR , { adrs } T able 4–46 T able 4–46 5 MOV { flagadrs } ?[...]

Instruction Set Summary 4-200 name dest [, src] [, src1] [,mod] Clock , clk Words , w With RPT , clk Class MOVU MR , { adrs } T able 4–46 T able 4–46 5 MOV APH A n , MR , { adrs } T able 4–46 T able 4–46 1b MOV APHS A n , MR , { adrs } T able 4–46 T able 4–46 1b MOVSPH A n , MR , { adrs } T able 4–46 T able 4–46 1b MOVSPHS A n , MR [...]

Instruction Set Summary 4-201 Assembly Language Instructions name Class With RPT , clk Words , w Clock , clk dest [, src] [, src1] [,mod] OR TF n , { flagadrs } 1 1 n R +3 8a OR TF n , { cc } [, R x ] 1 1 N/R 8b ORB A n , imm8 1 1 N/R 2a ORS A n , { adrs } T able 4–46 T able 4–46 1b ORS A n [~], A n [~], pma16 n S +4 2 N/R 2b ORS A n [~], A n ~[...]

Instruction Set Summary 4-202 name Class With RPT , clk Words , w Clock , clk dest [, src] [, src1] [,mod] SHL TPLS A n , { adrs } T able 4–46 T able 4–46 1b SHL TPLS A n [~], A n [~] n S +3 1 n R +3 3 SHLAC A n [~], A n [~] [, next A ] 1 1 n R +3 3 SHLACS A n [~], A n [~] n S +3 1 n R +3 3 SHRAC A n [~], A n [~] [, next A ] 1 1 n R +3 3 SHRACS[...]

Instruction Set Summary 4-203 Assembly Language Instructions name Class With RPT , clk Words , w Clock , clk dest [, src] [, src1] [,mod] XORS A n , { adrs } T able 4–46 T able 4–46 1b XORS A n [~], A n [~], pma16 n S +4 2 N/R 2b XORS A n [~], A n ~, A n n S +3 1 n R +3 3 ZAC A n [~] [, next A ] 1 1 n R +3 3 ZACS A n [~] n S +3 1 n R +3 3 cc na[...]

Instruction Set Summay 4-204 Assembly Language Instructions MSP50C614 (MSP50P614) IO Port Description Address Bits Name R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 After RESET 0x00 8 Port A Data (bidi i l) R/W A7 A6 A5 A4 A3 A2 A1 A0 external i (bidirectional) bit A x = 0 ⇒ PA x low bit A x = 1 ⇒ PA x high input states 0x04 8 Port A Control R/W C[...]

Instruction Set Summay 4-205 Assembly Language Instructions MSP50C614 (MSP50P614) IO Port Description Address Bits Name R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 After RESET 0x34 4 DAC Control R/W DM E P1 P0 0x0 DM Drive Mode E Function P1 P0 DAC bits 0 3x Style DAC 0 Disable DAC 0 0 8 bit 1 y 5x Style DAC 1 Enable DAC 11 0 9 bits 10 bi 0 10 bits 0[...]

Instruction Set Summay 4-206 Assembly Language Instructions Interrupt V ector Source T rigger Event Priority Comment INT0 0x7FF0 DAC T imer timer underflow highest used to synch. speech data INT1 0x7FF1 TIMER1 timer underflow 2 nd INT2 0x7FF2 TIMER2 timer underflow 3 rd INT3 0x7FF3 port PD2 rising edge 4 th port PD2 goes HIGH INT4 0x7FF4 port PD3 f[...]

Instruction Set Summay 4-207 Assembly Language Instructions 10 kHz Nominal Synthesis Rate (32.768 kHz oscillator reference) ClkSpdCtrl Master CPU Output Number of Number of IntGenCtrl ClkSpdCtrl PLLM Master Clock PDM CPU Clock O u tp u t Sam p lin g N u mber of Instructs N u mber of Instructs DAC IntGenCtrl PDMCD Over-Sampling PLLM Register Clock R[...]

Instruction Set Summay 4-208 Assembly Language Instructions[...]

5-1 Code Development T ools For code development purposes, the programmable MSP50P614 is used. The MSP50C6xx code development tool is used to compile, link, and debug assembly language programs. This tool can also be used to program an MSP50P614. A reduced function C compiler , (called C– –) is also available. T opic Page 5.1 Introduction 5–2[...]

Introduction 5-2 5.1 Introduction The MSP50C6xx development tools gain access to the core controller via a serial scan interface called the Scanport. The basic elements needed to do de- velopment with the MSP50C6xx devices are listed below in Section 5.3. The MSP50C6xx software development tool is included with the MSP scanport in- terface (TI part[...]

MSP50C6xx Software Development T ool 5-3 Code Development T ools the reset circuit and the reset pin, and connecting the scanport reset signal directly to the reset pin. See the recommended reset circuit shown in Figure 1–3. It is also recommended that all production boards be built with the scanport interface connector footprint connected to the[...]

Requirements 5-4 5.3 Requirements The requirements for a complete MSP50C6xx development system are as follows: PC Requirements: Intel i486  or Pentium  class processor Microsoft Windows  3.1 1, Windows 95  , or Windows 98  operating system 16-MB memory 8-MB hard disk space Parallel port interface Development Requirements: MSP50C6xx S[...]

Hardware Installation 5-5 Code Development T ools 5.4 Hardware Installation The following steps are used to set up the hardware (see Figure 5–2): 1) Connect the 18 V power supply to the MSPSI and connect the mains pins to a 120 V , 60 Hz ac source. 2) Connect one end of the IEEE1284 parallel cable to the MSPSI board and the other end to the PC pa[...]

Software Installation 5-6 Figure 5–3. 10-Pin IDC Connector (top view looking at the board) IDC2X5M RESET V PP SCANCLK PGMPULSE SYNC GND N/C SCANIN V DD SCANOUT 1 3 5 7 9 2 4 6 8 10 PINOUT DET AILS 10-PIN HEADER (3M P ART# 2510–60024B) LA YOUT DET AILS 0.1 0.800 0.1 IDC2X5M HOLE DIA 0.038 P AD DIA 0.060 0.35 5.5 Software Installation Install the[...]

Software Installation 5-7 Code Development T ools Figure 5–5. Setup Window Step 2: After setup runs the InstallShield (see Figure 5–4), the setup window pops up (see Figure 5–5). Step 3: Press the Next > button to continue with installation or press Cancel to exit installation.[...]

Software Installation 5-8 Figure 5–6. Exit Setup Dialog Step 4: If you press Cancel , you can return to setup by pressing Resume but- ton. Y ou can exit setup by pressing Exit Setup button (Figure 5–6). Figure 5–7. User Information Dialog[...]

Software Installation 5-9 Code Development T ools Step 5: If you continue with setup, you will be brought to User Information dialog. Enter your Name and Company Name in the two respective fields. T o get into this screen, you must press yes to the license screen and press next to the Information dialog. Step 6: T ype any alphanumeric value as Seri[...]

Software Installation 5-10 Figure 5–9. Select Program Folder Dialog Step 9: Enter a new folder name in Select Program Folder dialog. Step 10: Press Next > to continue with installation.[...]

Software Installation 5-1 1 Code Development T ools Figure 5–10. Copying Files Step 1 1: The program starts installation. When the installation is complete, an icon is also created on the desktop.[...]

Software Installation 5-12 Figure 5–1 1. Setup Complete Dialog Step 12: The Setup Complete dialog message is displayed when setup is completed. Press the Finish button to complete the installation.[...]

Software Emulator 5-13 Code Development T ools 5.6 Software Emulator Run the EMUC6xx.exe program which will be in the installation directory or on your desktop (icon). Y our scanport interface and the target board must be connected and turned on before the emulator can be successfully used. If the opening window comes up without any messages, the s[...]

Software Emulator 5-14 Figure 5–13. Project Menu Figure 5–14. Project Open Dialog[...]

Software Emulator 5-15 Code Development T ools Figure 5–15. File Menu Options 5.6.2 Projects The emulator can only work from project files created within the emulator itself. These files have the extension .rpj , and are not compatible with the .rpj files used in the old simulator . In other words, even to assemble a single as- sembly program, th[...]

Software Emulator 5-16 ( pfe32.exe ) and an error dialog. The user can modify the source code and save the changes, before restarting the building action. 5.6.3 Description of Windows Once a new project is created or an old project is opened, the following seven windows pops open (Figure 5–16). Figure 5–16. MSP50P614/MSP50C614 Code Development [...]

Software Emulator 5-17 Code Development T ools Figure 5–17. RAM Window RAM Window : Displays 16-bit data memory hex values. The left most column is the address. Data memory is always addressable as bytes by MSP50C614 instructions. Each value displayed in this window is actually two consecutive byte data. Data memory values consist of the usual 16[...]

Software Emulator 5-18 W atch Window : W atch window displays the data memory location and data to be watched. It mirrors the value displayed in the RAM window . The W atch window is provided as a help to display locations that may not be visible in the RAM window without scrolling. See Ram Window above to know more about how to use W atch window .[...]

Software Emulator 5-19 Code Development T ools being run in emulation mode. STK field is the depth of the stack. The emulator keeps track of number of calls and returns and changes this variable accordingly . CUR field is the current subroutine name. In C–– programs it becomes very handy to display local variables of a subroutine. C– – Figu[...]

Software Emulator 5-20 background is the line reached by a search command (by PC, line number or label). Search position can also be set by double clicking on it in the program window . The line (if any) contain the hardware breakpoint is displayed in green background. T o set a hardware breakpoint, just click the right mouse button over the line y[...]

Software Emulator 5-21 Code Development T ools variable value and its address in RAM are then displayed (Figure 5–21). V ariables appearing on a gray background either are not defined, or are not active at this time. The user can also use the Inspect option in the Debug menu to insert a variable in the Inspect window . Figure 5–21. Inspect Dial[...]

Software Emulator 5-22 modified (i.e, by double clicking on a value and typing its new hexadecimal value over the existing value). V alues of read only registers cannot be modified. Figure 5–23. I/O Ports Window Project Window : All source files making up the project are displayed in this window . Only assembly language files (.asm) and C– – [...]

Software Emulator 5-23 Code Development T ools Step Over : This menu option, (key equivalent: F8), allows the user to step over a call instruction in the program window . Note that the program window does not need to have the focus to execute a Step instruction. If the Step Over instruction leads into a gray area , i.e., a program line, or group of[...]

Software Emulator 5-24 Fast Run : This menu option, (key equivalent: CTRL+F9), allows the user to execute a portion of the program window , until a breakpoint is encountered. The windows are not refreshed until the program stops, so that the execution speed is maximized. If no breakpoint is encountered, the user can stop the program by hitting the [...]

Software Emulator 5-25 Code Development T ools Figure 5–25. EPROM Programming Dialog[...]

Software Emulator 5-26 T race Mode : This menu option launches the Trace Mode Dialog (Figure 5–25), that allows that user to run the chip in trace mode , i.e., running an internal program on the chip while monitoring its execution on the scanport. Figure 5–26. T race Mode Optional T race Mode start program memory location (hex). If this value i[...]

Software Emulator 5-27 Code Development T ools Stop Internal : This menu option halts execution of an internal program. It provides an internal picture of the chip at the time the internal program execution was halted. Note that due to the asynchronous nature of this halt, one erroneous instruction may be executed before the chip actually stops. Fo[...]

Software Emulator 5-28 Init RAM : Initializes the data memory values to zero including tag bits. Init Registers : Initializes all the system registers (excluding accumulators) to zero except PC which is initialized to start vector . Init Accumulators : Initializes all the accumulators to zero. Init All : This menu option initializes all internal re[...]

Software Emulator 5-29 Code Development T ools Figure 5–28. Options Menu Figure 5–29. Miscellaneous Dialog List of directories separated by semicolons that the C–– compiler will search for include files enclosed in angle brackets (<>) before searching current directory . Heap start address for C–– compiler . Beginning of Stack for[...]

Software Emulator 5-30 Figure 5–30. Windows Menu Options 5.6.7 Emulator Online Help System The emulator has an online help which is launched when the Help menu option is left clicked with a mouse. The help window (Figure 5–30) is context sensitive and graphical in nature. Any topic selected by pointing the mouse to the topic and clicking the le[...]

Software Emulator 5-31 Code Development T ools Figure 5–31. Context Sensitive Help System[...]

Software Emulator 5-32 5.6.8 Known Differences, Incompatibilities, Restrictions Include statements in assembly language files must enclose the file name in double quotes. REF/DEF statements in assembly language files should be replaced with EXTERNAL/GLOBAL statements, but the old REF/DEF are still supported. There is no default type for variables i[...]

Assembler 5-33 Code Development T ools 5.7 Assembler The MSP50P614/MSP50C614 assembler is implemented as a Windows DLL (Dynamic Linked Library). 5.7.1 Assembler DLL The current name of the DLL file is asm6xx.dll . It can be invoked from any Windows program, provided that the user included the file called asm6xx.lib in the Windows project. The synta[...]

Assembler 5-34 5.7.2 Assembler Directives Assembler directives are texts which have special meaning to the assembler . Some of these directives are extremely helpful during conditional compiling, debugging, adding additional features to existing codes, multiple hardware development, code release etc. Other directives are an essential part of the as[...]

Assembler 5-35 Code Development T ools symbol is any alphanumeric text starting with an alphabetic character , a number , or an expression. Examples: SYM1 EQU (12 * 256) SYM2 EQU SYM1 * (32 / 4) SYM3 EQU SYM1 * SYM2 – *0x200 From the above example SYM1, SYM2 and SYM3 are symbols for some ex- pression. The grammar for Symbol is as follows: symbol:[...]

Assembler 5-36 Example: #IF expression ; do something here #ELSE ; do other things here #ENDIF #IFDEF symbol: Start of a conditional assembly structure. If symbol has been defined (either with a #DEFINE directive or an EQU directive) then the lines following this directive are assembled until a #ELSE or a #ENDIF directive are encountered. If symbol[...]

Assembler 5-37 Code Development T ools BYTE expression[,expression]: Introduces one or more data items, of BYTE size (8 bits) . The bytes are placed in the program memory in the order in which they are declared. CHIP_TYPE chip_name: This directive is here for compatibility with future chips in the same family . It defines some chip parameters (like[...]

Linker 5-38 should be declared there as EXTERNAL (or REF). Note that this technique can also be used to make constants defined with the EQU statement available to other files. INCLUDE filename : This directive is used to insert another file in the current assembly file. The name of the file to be included must be enclosed in double quotes. If the f[...]

C– – Compiler 5-39 Code Development T ools The syntax of the call is: extern int FAR PASCAL LINK_MAIN (LPSTR source_file,LPSTR exe_file); ..... ierr=LINK_MAIN (source_file,exe_file); Where: source_file is the project file name, which contains the names of the files to be linked. exe_file is the name of the linked executable file. ierr is the to[...]

C– – Compiler 5-40 short ram_size; /* ram size for the chip */ short verbose; /* refers to assembly code output */ short c_code; /* if non zero, c code is included as */ /* assembly language comments */ short optimize; /* should always be non zero */ char dir_list; /* string of include directories searched */ /* for C– – include directive *[...]

C– – Compiler 5-41 Code Development T ools 5.9.2 V ariable T ypes T ype Name Mnemonic Range Size in Bytes Example Integer int [–32768,32767] 2 int i,j; Character char [0,255] 1 char c,d; Array of integer int Not Applicable Not Applicable int array[12]; Array of characters char Not Applicable forced to even char text[20] Pointer to integer int[...]

C– – Compiler 5-42 5.9.4 C– – Directives C– – has a limited number of directives and some additional directives not found in ANSI C compilers. The following directives are recognized by the compiler . 5.9.4.1 #define This directive is used to introduce 2 types of macros, in typical C fashion: Without Arguments: defines a replacement str[...]

C– – Compiler 5-43 Code Development T ools 5.9.4.3 #include As in regular C, this directive allows for the insertion of a file into the current file. If the file name that follows is enclosed in < >, the system searches the include directories for the file, otherwise, if it is enclosed in “ ”, the current directory is searched. Exampl[...]

C– – Compiler 5-44 5.9.5 Include Files There are currently two include files supplied with C– –, cmm_func.h , which contains function prototypes for the C– –functions and cmm_macr.h which contains some predefined macros. Both files are listed below: /********************************/ /* Prototypes for C– –functions */ /*************[...]

C– – Compiler 5-45 Code Development T ools 5.9.6 Function Prototypes and Declarations As mentioned above, C– – function prototypes and declarations MUST be preceded with the keyword cmm_func . Also, since all functions return through accumulator A0, all functions are of type integer , so that the function type can be omitted in the function[...]

C– – Compiler 5-46 T able 5–1. String Functions add_string(int *result,int *str1,int *str2,int lg) adds strings str1 and str2, of length lg (+2), and puts the result in string result sub_string(int *result,int *str1,int *str2,int lg) subtracts strings str2 from str1, of length lg (+2), and puts the result in string result. mul_string(int *res[...]

C– – Compiler 5-47 Code Development T ools Also note that the user has to supply the length of the input string and the length of the output string in the string multiply operations: the result of multiplying a string by an integer can be one word longer than the input string. Unpredictable results may occur if parameter lgr is not at least equ[...]

Implementation Details 5-48 5.10 Implementation Details This section is C– – specific. 5.10.1 Comparisons We use the CMP instruction for both signed and unsigned comparisons. The two integers a and b to be compared are in A0 and A0~ . CMP A0,A0~ : A0 contains a, A0~ contains b A0 A0~ ACO AZ ANEG 5 0 1 0 0 51100 05001 15001 00110 55110 FFFF 0 1 [...]

Implementation Details 5-49 Code Development T ools Unsigned comparison of a and b. (a is in A0, b is in A0~) Assembly T est Condition _ult a < b AUL T _ule a <= b !AUGT _uge a >= b !AUL T _ugt a > b AUGT The small number of comparisons was an invitation to use them as vector calls. We return a 1 or 0 in A0 as the result of the comparis[...]

Implementation Details 5-50 5.10.2 Division The integer division currently requires the use of several accumulator pointers. We divide a 16 bit integer located in A0 by a 16 bit integer located in A0~ . We return the quotient in A0~ , and the remainder in A0 . We make use of A3~ and A3 for scratch pads. We also set flag 1 if a division by zero is a[...]

Implementation Details 5-51 Code Development T ools Function declarations ( or function prototypes) are introduced by the mnemonic cmm_func . We only allow the new style of function declarations /prototypes, where the type of the arguments is declared within the function’s parentheses. For example: cmm_func bidon(int i1,char *i2) is valid, but: c[...]

Implementation Details 5-52 constant int M1[4]={0x04CB,0x71FB,0x011F,0x0}; constant int M2[4]={0x85EB,0x8FD9,0x08FB,0x0}; cmm_func string_multiply(int *p,int lgp,int *m1,int lgm1,int *m2,int lgm2) { /* note: length of p,(lgp+2) must be at least (lgm1+2) + (lgm2+2) +1 */ /* this function string multiplies string m1 of length lgm1+2 by string m2 of l[...]

Implementation Details 5-53 Code Development T ools free(mm2); free(pp); } cmm_func main(int argc,char *argv) { int m1[4],m2[4],product[9]; xfer_const(m1,M1,STR_LENGTH(4)); xfer_const(m2,M2,STR_LENGTH(4)); string_multiply(product,STR_LENGTH(9),m1,STR_LENGTH(4),m2,STR_LENGTH(4)); } 5.10.5 Programming Example, C – – With Assembly Routines There a[...]

Implementation Details 5-54 find the correct size for bogus. Bogus can be made larger for extra safety as long as enough memory is left over for the C– – variables and the stack. If space allows, it is a good idea to add a few extra words to bogus in case assembly variables are added to the project without modifying bogus. It is also important [...]

Implementation Details 5-55 Code Development T ools || || || |––––––––––––––| |––––––––––––––| |––––––––––––––| | |R7 | |R5,R7 | | |––––––––––––––| |––––––––––––––| |––––––––––––––| [...]

Implementation Details 5-56 C to C function return (in cmm_return). || || || || || || |––––––––––––––| |––––––––––––––| |––––––––––––––| R 5 || || || |––––––––––––––| |––––––––––––––| |––––––––?[...]

Implementation Details 5-57 Code Development T ools |––––––––––––––| || |––––––––––––––| || |––––––––––––––| || |––––––––––––––| |(old)R5 | |––––––––––––––| |(old)R5 | |–––––––––––––?[...]

Implementation Details 5-58 C to ASM function call. The stack is shown after the operation on the bottom is performed. || || || |––––––––––––––| |––––––––––––––| |––––––––––––––| || | | | | |––––––––––––––| |––––––––––[...]

Implementation Details 5-59 Code Development T ools || |––––––––––––––| || |––––––––––––––| || || |––––––––––––––| || |––––––––––––––| R7 |Return Addr | |––––––––––––––| |Return Addr | |––––––––[...]

Implementation Details 5-60 T o call an assembly routine from C– –, the routine must be defined as GLOBAL in the assembly file and as a CMM_FUNC in the C– – file. The following contains C– – callable assembly routines for accessing the I/O ports, and a wait routine. A C– – program which calls the assembly routines is also provided. [...]

Implementation Details 5-61 Code Development T ools ;––––––––––––––––––––––––––––––––––––––––––––––––––––– ; called from C–– ; void oport(char Port, int Data) ; Writes Data to the I/O port specified by the letter Port. ; Example: ; oport(?[...]

Implementation Details 5-62 _iprtc in a0, 0x10 ; read from PortC ret _iprtd in a0, 0x18 ; read from PortD ret _iprte in a0, 0x20 ; read from PortE ret _iprtf in a0, 0x28 ; read from PortF ret _in_port_access ; table for table lookup DATA _iprta DATA _iprtb DATA _iprtc DATA _iprtd DATA _iprte DATA _iprtf ;––––––––––––––?[...]

Implementation Details 5-63 Code Development T ools DATA _cprte ;––––––––––––––––––––––––––––––––––––––––––––––––––––– ;–––––––––––––––––––––––––––––––––––––––––?[...]

Implementation Details 5-64 nop ret ;**************************************************************** ; Dummy interrupt routines ;**************************************************************** DAC_ISR TIMER2_ISR TIMER1_ISR PORTD2_ISR PORTD3_ISR PORTF_ISR PORTD4_ISR PORTD5_ISR DUMMY_ISR nop INTE iret Here is a sample C–– file that accesses the[...]

Implementation Details 5-65 Code Development T ools cmm_func iport(int x); // read a port int i,j,k,l; // various temp and loop variables int x[4]; // array holding the correct key sequence int locked=1; //variable returned by lock() cmm_func lock(){ x[0]= 0xEF; //MS7 x[1]= 0xBF; //MS9 x[2]= 0xEF; //MS7 x[3]= 0x7F; //MS10 locked=0; cport(’B’, 0[...]

Implementation Details 5-66 wait(100); oport(’B’, 0x00); wait(100); oport(’B’, 0xFF); wait(100); oport(’B’, 0x00); wait(100); oport(’B’, 0xFF); wait(100); } else{ // If the correct inputs were given. oport(’B’,0x00); // Light all LED’s wait(5000); // Keep lit for 5 seconds ( unlock the door ) } } // end for return; }[...]

Beware of Stack Corruption 5-67 Code Development T ools 5.1 1 Beware of Stack Corruption MSP50C614/MSP50P614 stack (pointed by R7 register) can easily get cor- rupted if care is not taken. Notice the following table read code: SUBB R7, 4 MOV A0, *R7–– ADD A0, address MOV A0, *A0 ADD A0, *R7–– MOV A0, *A0 RET This code will work perfectly we[...]

5-68[...]

6-1 Applications This chapter contains application information on application circuits, proces- sor initialization sequence, resistor trim setting, synthesis code, memory over- lays, and ROM usage. T opic Page 6.1 Application Circuits 6–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 MSP50C614/MSP50P614[...]

Application Circuits 6-2 6.1 Application Circuits T o pin 2 of Scan Port Connector † MSP50C614/ MSP50P614 T o pin 1 of Scan Port Connector † (optional ) 5 V 0.1 µ F (5) R REFERENCE 470 k Ω (1%) 3300 pF OSC IN OSC OUT PLL DAC P DAC M V PP V DD 1N914 † 32 Ω RESET V SS 5 5 1 µ F 20% 1 k Ω † 100 k Ω 5 V 1N914 Reset Switch † The diod[...]

Application Circuits 6-3 Applications It is of particular importance to provide a separate decoupling capacitor for the V DD , V SS pair which services the DAC. These pins are pad numbers 21 and 19, respectively . The relatively high current demands of the digital-to-analog circuitry make this a requirement. An alternate circuit, for better clock-p[...]

MSP50C614/MSP50P614 Initialization Codes 6-4 In any C614 application, it is important for certain components to be located as close as possible to the C614 die or package. These include any of the decoupling capacitors at V DD (0.1 µ F). It also includes all of the components in the crystal-reference network between OSC IN and OSC OUT (22 pF , 10 [...]

MSP50C614/MSP50P614 Initialization Codes 6-5 Applications 6.2.1 File init.asm ;**************************************************************** ; INIT.ASM ; ; ; Copyright: 1998 Texas Instruments, Inc. All rights reserved. ; ; –––––––––––––––––––––––––––––––––––––––––?[...]

MSP50C614/MSP50P614 Initialization Codes 6-6 out IntGenCtrl,a0 ;clear all interrupt mask bits, disable timers mov r0,0x000 ;point to beginning of RAM mov r4,RAM_SIZE – 2 ;do a loop RAM_SIZE times BEGLOOP rtag *r0 ;reset tag mov *r0++,a0 ;clear the RAM ENDLOOP mov STR,0 ;clear string register mov ap0,0 ;clear accum pointer 0 mov ap1,0 ;clear accum[...]

MSP50C614/MSP50P614 Initialization Codes 6-7 Applications mov *save_clkspdctrl,a0 ;save the ClkSpdCtrl value for later, when ;waking up from mid or deep sleep mov 0~,TIM2REFOSC + TIM2IMR ;disable TIMER 2 out IntGenCtrl,a0~ mov a0~,6553 ;setup a 200 ms period out TIM2,a0~ ;load TIM2 and PRD2 in one fell swoop mov a0~,TIM2ENABLE + TIM2REFOSC + TIM2IM[...]

T exas Instruments C614 Synthesis Code 6-8 6.3 T exas Instruments C614 Synthesis Code Some sample codes are supplied with the development tools. These samples are in the .Examples subdirectory where the tool is installed. In this manual only one example code is explained. This description applies to all the code development. The following example [...]

T exas Instruments C614 Synthesis Code 6-9 Applications T o continue, click on the Run Internal icon again. The LEDs should flash during MELP synthesis ( Extra, extra, read all about it ) and should flash in a different pattern after MELP synthesis. Running the Program The MELP1 program can run on either the demo box or the code development board. [...]

T exas Instruments C614 Synthesis Code 6-10 | spk_ram.irx | | –––––––– melp | melp.obj | melp.irx | –––––––– modules | –––––––– 605 | 605.asm | 605.irx | | –––––––– general | init.asm | sleep.asm | io_ports.irx | | –––––––– isr | dac_isr.asm | tim1_isr.asm | tim2_isr.as[...]

T exas Instruments C614 Synthesis Code 6-1 1 Applications File Description Util.obj Maths functions and tables used by the vocoders. Dsputil.asm Oversampling and miscellaneous functions. Getbits.asm Routine to get data from ROM. Speak.asm Routines to speak a phrase or sentence. Dsp_var.irx Various vocoder constants. Speak.irx Speech header constant[...]

T exas Instruments C614 Synthesis Code 6-12 RAM Usage The file MAIN.LST contains the variable RAM assignments. Do a search for BEGIN_RAM to find the start of the RAM locations. Adding Another Module There are three steps to adding a new module to a project. First, the project file ( .RPJ ) must be updated to include the ASM file (click on File – [...]

T exas Instruments C614 Synthesis Code 6-13 Applications These files may be edited for special purpose code INIT.ASM and SPEAK.ASM These files should never be edited SLEEP.ASM, RAM.IRX and SPK_RAM.IRX A good rule of thumb to follow is that files under the DSP directory should be left alone, and all custom code should be added either to MAIN.ASM or [...]

ROM Usage With Respect to V arious Synthesis Algorithms 6-14 6.4 ROM Usage With Respect to V arious Synthesis Algorithms The following table lists some possible synthesis options and their ROM requirements. The models assume that just enough program space, as necessary for storage of the synthesis algorithm, is used. The remainder of the ROM is ded[...]

7-1 Customer Information Customer information regarding package configurations, development cycle, and ordering forms are included in this chapter . T opic Page 7.1 Mechanical Information 7–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Customer Information Fields in the ROM 7–7 . . . . . . . . . . . . . .[...]

Mechanical Information 7-2 7.1 Mechanical Information The C614 is normally sold in die form but is also available in 100-pin PJM packages. The P614 is available in a windowed ceramic package, 120-pin PGA. NOTE: Scan Port Bond Out The Scan Port Interface on the MSP50C6xx devices has five dedicated pins and one shared pin that need to be used by the [...]

Mechanical Information 7-3 Customer Information 7.1.2 Package Information The MSP50C614 will be available in the 100-pin PJM package (see Figure 7–1 and T able 7–1). Contact your local TI sales office for more informa- tion. T able 7–1. MSP50C614 100-Pin PJM Plastic Package Pinout Description Description Pin # Description Pin # Description Pi[...]

Mechanical Information 7-4 Figure 7–1. 100-Pin PJM Mechanical Information 4040022 / B 03/95 0,16 NOM 14,20 17,45 13,80 16,95 50 51 31 30 12,35 TYP 1,03 0,73 0,25 Seating Plane 0,25 MIN Gage Plane 0,38 0,22 80 1 81 100 22,95 23,45 20,20 19,80 2,50 2,90 3,40 MAX 18,85 TYP 0 ° –7 ° M 0,13 0,65 0,10 NOTES: A. All linear dimensions are in millimet[...]

Mechanical Information 7-5 Customer Information The C614 is sold in die form for its volume production. For software develop- ment and prototyping, a windowed ceramic 120 pin grid array packaged P614 is available. The P614’s PGA package is shown in Figure 7–2. Figure 7–2. 120-Pin Grid Array Package for the Development Device, P614 extra pin 1[...]

Mechanical Information 7-6 The pin assignments for the 120-pin PGA are outlined in the following table. (Refer to Section 1.6 for more information on the signal functions.) Figure 7–3 provides a cross-reference between the C614 (die) pad numbers and the P614’s PGA package leads. Figure 7–3. 120 Pin Grid Array (PGA) Package Leads, P614 N nc nc[...]

Customer Information Fields in the ROM 7-7 Customer Information 7.2 Customer Information Fields in the ROM In those cases where the customer code is programmed by T exas Instruments, some registration of the code-release is provided within the ROM. This information appears as 7 distinct fields within the ROM test-area. The ROM test-area extends fro[...]

Speech Development Cycle 7-8 7.3 Speech Development Cycle Figure 7–4. Speech Development Cycle Speech Specification Speaker Selection Recording Script Preparation Software Design Hardware Design Software Writing Prototype Construction Software Debugging System Evaluation Speech Recording Speech Analysis Speech Editing Speech Evaluation A sample s[...]

Device Production Sequence 7-9 Customer Information All prototype devices are shipped with the following disclaimer: It is understood that, for expediency purposes, the initial 25 prototype devices (and any additional prototype devices purchased) were assembled on a prototype (i.e., not production-qualified) manufacturing line, whose reliability ha[...]

Ordering Information 7-10 7.5 Ordering Information Because the MSP50C614 is a custom device, it receives a distinct identifica- tion, as follows: CSM Gate Code CSM: Custom Synthesizer With Memory 614 XXX X X Family Member ROM Code Revision Letter Package or Die PJM: Loopin QFP (Preliminary) Y : Die 7.6 New Product Release Forms The new product rele[...]

New Product Release Forms 7-1 1 Customer Information NEW PRODUCT RELEASE FORM FOR MSP50C614 (DIE ONLY) SECTION 1. ORDER INFORMATION Division:____________________________ Company:___________________________ Project Name:________________________ Purchase Order #:_____________________ Management Contact: ___________________________ Phone:(___) _______[...]

7-12[...]

A-1 Appendix A MSP50C605 Preliminary Data This Appendix contains preliminary data for the MSP50C605 device. Note: MSP50C605 MSP50C605 is in the Product Preview stage of development. For more in- formation contact your local TI sales office. T opic Page A.1 Introduction A–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

Introduction A-2 A.1 Introduction MSP50C605 is a spin of f of the core processor MSP50C614. It uses three IO ports of MSP50C614 and maps a 1.835 Mbits of internal ROM. Using a 1 kbps MELP algorithm, the C605 can provide over 30 minutes of uninterrupted speech. There is no Port A and Port B control register in MSP50C605. Port DRD is read only , and [...]

Architecture A-3 MSP50C605 Preliminary Data A.3.1 RAM The MSP50C605 (like MSP50C614) has 640 17-bit words of internal data memory (static RAM). This RAM occupies a space extending from 0 to 0x27F in the address space. A.3.2 ROM The MSP50C605 contains 32K by 17-bit words of internal program ROM and 229,376 bytes by 8 bits (i.e., 1,835,008 bits) of s[...]

Architecture A-4 Figure A–1. MSP50C605 Architecture Data ROM access Core CU Computational Unit PCU Prog. Counter Unit Instr . Decoder TIMER1 PRD1 TIM1 0x3A 0x3B Clock Control 0x3D Gen. Control 0x38 RAM 640 x 17 bit (data) 0x0000 to 0x027F Power V PP V DD V SS F port INPUT DA T A 0x28 8 PF 0..7 Data ROM 229,376 x 8 bit DRA 0x2C DRD 0x00 DRP 0x08 C[...]

Architecture A-5 MSP50C605 Preliminary Data Figure A–2. MSP50C605 Memory Organization 0x0000 0x0800 0x07FF 0x7FF0 0x7FF7 User ROM 30704 x 17 bit (C605 : read–only) (P614 : EPROM) Internal T est Code 2048 x 17 bit (reserved ) Program Memory Peripheral Ports 0x 027F 0x 0000 Data Memory RAM 640 x 17 bit 0x 00 DRD 0–7 Macro Call V ectors 255 x 17[...]

Architecture A-6 Figure A–3. MSP50C605 100-Pin PJM Package MSP50C605 100 PIN PJM PLASTIC P ACKAGE 1 80 81 100 30 31 50 51[...]

Architecture A-7 MSP50C605 Preliminary Data T able A–1. MSP50C605 100-Pin PJM Plastic Package Pinout Description Description Pin# Description Pin# Description Pin# Description Pin# NC 1 NC 26 NC 51 NC 76 NC 2 NC 27 NC 52 NC 77 NC 3 NC 28 NC 53 NC 78 NC 4 NC 29 NC 54 NC 79 DACM 5 NC 30 NC 55 NC 80 VCC3 6 VCC 31 NC 56 NC 81 DACP 7 VCC1 32 NC 57 PC7[...]

A-8[...]

B-1 Appendix A MSP50C604 Preliminary Data This Appendix contains preliminary data for the MSP50C604 device. Note: MSP50C604 MSP50C604 is in the Product Preview stage of development. For more in- formation contact your local TI sales office. T opic Page B.1 Introduction B–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

Introduction B-2 B.1 Introduction MSP50C604 is a spin of f of the core processor MSP50C614. It is targeted as a slave device. An external microprocessor is needed to interface with MSP50C604 in slave mode. It can also be used a stand alone device if desired. B.2 Features 30k word ROM customer program memory 8 MHz uDSP core 2 IO pins can be used as [...]

Architecture B-3 MSP50C604 Preliminary Data B.3.1 RAM The MSP50C604 (like MSP50C614) has 640 17–bit words of internal data memory (static RAM). This RAM occupies a space extending from 0 to 0x27F in the address space. B.3.2 ROM The MSP50C604 contains 32K by 17-bit words of internal program ROM. The program ROM space is divided into two areas: 1) [...]

Architecture B-4 Figure B–1. MSP50C604 Block Diagram Core CU Computational Unit PCU Prog. Counter Unit Instr . Decoder TIMER1 PRD1 TIM1 0x3A 0x3B Clock Control 0x3D Gen. Control 0x38 RAM 640 x 17 bit (data) 0x0000 to 0x027F Power V PP V DD V SS C port I/0 Control 0x14 DA T A 0x10 / 8 PC 0..7 Initialization Logic RESET DAC 0x30 32 Ohm PDM DAC M DA[...]

Architecture B-5 MSP50C604 Preliminary Data B.3.4 Slave Mode Operation The MSP50C604 is used as a peripheral device in slave mode. A microproces- sor/microcontroller controls the R/WZ , STROBE , INRDY , OUTRDY pins of MSP50C604 to use it as a slave processor . No special programming is re- quired to switchthe ’C604 to slave mode. Slave mode is ex[...]

Architecture B-6 Figure B–2. MSP50C604 Memory Organization and I/O ports 0x0000 0x0800 0x07FF 0x7FF0 0x7FF7 User ROM 30704 x 17 bit (C604 : read–only) (P614 : EPROM) Internal T est Code 2048 x 17 bit (reserved ) Program Memory Peripheral Ports 0x 027F 0x 0000 Data Memory RAM 640 x 17 bit Macro Call V ectors 255 x 17 bit (overlaps interrupt vect[...]

Architecture B-7 MSP50C604 Preliminary Data B.3.7 Interrupts Interrupts for MSP50C604 are the same as MSP50C614 in host mode except INT5 (port F interrupt) is not available. But in slave mode, INT3 and INT4 are external interrupts triggered by write sequence and read sequence as ex- plained before. A summary of the interrupts is given below: Interr[...]

Packaging B-8 B.4 Packaging The MSP50C604 is sold in die form. A 64 pin plastic package is also available. T able B–1. MSP50C604 64-Pin PJM Plastic Package Pinout Description Description Pin# Description Pin# Description Pin# Description Pin# VCC 1 NC 17 PC6 33 GND 49 VCC3 2 NC 18 PC5 34 NC 50 PD3 3 NC 19 PC4 35 NC 51 PD2 4 NC 20 PC3 36 NC 52 PD1[...]

Packaging B-9 MSP50C604 Preliminary Data Figure B–3. MSP50C604 Slave Mode Signals INRDY OUTRDY R/WZ STROBE PC 0 –PC 7 Data latched to Port A New Data V alid Data Host write sequence Host read sequence Figure B–4. MSP50C604 64-Pin PJM Package MSP50C604 64 PIN PJM PLASTIC P ACKAGE 32 48 33 49 17 16 1 64[...]

Packaging B-10[...]

C-1 Appendix A MSP50C605 Data Sheet This appendix contains the data sheet for the MSP50C605 mixed-signal pro- cessor . T opic Page C.1 MSP50C605 Data Sheet C–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix C[...]

C-2 C.1 MSP50C605 Data Sheet This appendix contains the data sheet for the MSP50C605 mixed-signal pro- cessor .[...]