AMD SC3200 manual

AMD Geode™ SC3200 Processor Data Book AMD Geode™ SC3200 Processor Data Book February 2007 Publicat ion ID: 32581C[...]

2 AMD Geode™ SC3200 Processor Data Book © 2007 Advanced Micr o De vices, Inc. All r ights reser ved. The contents of this docu ment are pr o vided in connection with Adv anced Micro Devices , Inc. (“AMD”) products. AMD make s no representations or warranties with respect to the accuracy or completeness of the contents of this publication and[...]

AMD Geode™ SC3200 Processor Data Book 3 Contents 32581C Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.0 Overview .[...]

4 AMD Geode™ SC3200 Processor Data Book Contents 32581C 6.0 Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 6.2 Module Arch itectu[...]

AMD Geode™ SC3200 Processor Data Book 5 List of Figures 32581C List of Figures Figure 1-1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3-1. Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

6 AMD Geode™ SC3200 Processor Data Book List of Figures 32581C Figure 7-6. Capture Video Mode Weave Example Using Two Vid eo Frame Buffers . . . . . . . . . . . . . . . 316 Figure 7-7. Video Block Diagr am . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 Figure 7-8. Horizontal Down s[...]

AMD Geode™ SC3200 Processor Data Book 7 List of Figures 32581C Figure 9-47. AC97 Reset Timi ng Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Figure 9-48. AC97 Sync Timin g Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 10 Fig[...]

8 AMD Geode™ SC3200 Processor Data Book List of Figures 32581C[...]

AMD Geode™ SC3200 Processor Data Book 9 List of T ables 32581C List of T ab les Table 2-1. SC3200 Memo ry Controller Register Summ ary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 2-2. SC3200 Memo ry Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 8 Table [...]

10 AMD Geode™ SC3200 Processor Data Book List of T ables 32581C Table 5-29. Banks 0 and 1 - Common Control and St atus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 5-30. Bank 1 - CEIR Wakeup Config uration and C ontrol Regist ers . . . . . . . . . . . . . . . . . . . . . . . 1 17 Table 5-31. ACB Register M ap . . . . [...]

AMD Geode™ SC3200 Processor Data Book 11 List of T ables 32581C Table 6-22. F3: PCI Heade r Registers fo r Audio Support Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1 Table 6-23. F3BAR0: Audio Support Regis ters Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Table 6-24. F5: PCI Heade r Regis[...]

12 AMD Geode™ SC3200 Processor Data Book List of T ables 32581C Table 9-19. PCI Timing Para meters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Table 9-20. Measurem ent Condition P arameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Table [...]

AMD Geode™ SC3200 Processor Data Book 13 1 Overview 32581C 1.0 Ov er vie w 1.1 General Description The AMD Geode™ SC3200 processor is a member of the AMD Geode f amily of fully integrated x86 system chips . The SC3200 processor includes: • The AMD Geode GX1 processor module combines advanced CPU perf or mance with MMX™ suppor t, fully accel[...]

14 AMD Geode™ SC3200 Processor Data Book Overview 32581C 1.2 Features General Features ■ 32-Bit x86 processor , up to 266 MHz, with MMX instruc- tion set suppor t ■ Memory controller with 64-bit SDRAM interface ■ 2D graphics accelerator ■ CCIR-656 video input por t with direct vide o f or full screen display ■ PC/A T functionality ■ P[...]

AMD Geode™ SC3200 Processor Data Book 15 Overview 32581C ■ PCI Bus Interface: — PCI v2.1 compliant with wak eup cap ability — 32-Bit data path, up to 33 MHz — Glueless interface f or an external PCI device — Fixed priori ty — 3.3V signal suppor t onl y ■ Sub-ISA Bus Interface: — Up to 16 MB addressing — Suppor ts a chip select f[...]

16 AMD Geode™ SC3200 Processor Data Book Overview 32581C[...]

AMD Geode™ SC3200 Processor Data Book 17 2 Architecture Overview 32581C 2.0 Architecture Ov er vie w As illustrated in Figure 1-1 on pa ge 13, the SC3200 pro- cessor contains the following modules in one integrated device: • GX1 Module : — Combines advanced CPU perf orma nce with MMX suppor t, fully accelerated 2D graphics, a 64-bit synchrono[...]

18 AMD Geode™ SC3200 Processor Data Book Architecture Overview 32581C T able 2-1. SC3200 Me mor y Contr oller Register Summary GX_B ASE+ Memory Offset Width (Bits) T ype Name/Function Reset V alue 8400h-8403h 32 R/W MC_MEM_CNTRL1. Memory Controller Control Register 1 248C004 0h 8404h-8407h 32 R/W MC_MEM_CNTRL2. Memory Controller Control Register [...]

AMD Geode™ SC3200 Processor Data Book 19 Architecture Overview 32581C 4 RFSHTST (T est R efresh). This bit, when set high, generates a refresh r equest. This bit is only used for testing purposes. 3 XBUSARB (X-Bus Round Robin). When round robin is enabled, processor , graphi cs pipeline, and lo w pr iority display con- troller requests are arbitr[...]

20 AMD Geode™ SC3200 Processor Data Book Architecture Overview 32581C GX_BASE+8408h-840Bh MC_BANK_CFG (R/W) Reset Value: 41104110h 31:16 RSVD (Reserved). Write as 0070h 15 RSVD (Reserved). Write as 0. 14 SODIMM_MOD_BNK (SODIMM Module Banks - Banks 0 and 1). Selects number of module banks installed per SODIMM for SODIMM: 0: 1 Module bank (Bank 0 o[...]

AMD Geode™ SC3200 Processor Data Book 21 Architecture Overview 32581C 11 RSVD (Reserved). Write as 0. 10:8 RRD (ACT(0) to A CT(1) Com mand Period, tRRD). Minimum n umber of SDRAM clocks between A CT and ACT command to two different component banks within the same module bank . The memor y controller does not perform back-to-bac k Acti- vate comma[...]

22 AMD Geode™ SC3200 Processor Data Book Architecture Overview 32581C 2.1.2 Fast-PCI Bus The GX1 module co mmunicates with the Core Logic mod- ule via a F ast-PCI bus that c an work at up to 66 MHz. The F ast-PCI bus is inter nal for the SC3200 and is connected to the General Configuration Bloc k (see Section 4.0 on page 69 f or details on the Ge[...]

AMD Geode™ SC3200 Processor Data Book 23 Architecture Overview 32581C • Sub-ISA: See Section 3.4.7 "Sub-ISA Interface Signals" on page 57, Section 6.2.5 "Sub-ISA Bus Interface" on page 145, an d Section 4.2 "Multiplexing, Interrupt Selec- tion, and Base Address Registers" on page 70 • GPIO: See Section 3.4.16 &qu[...]

24 AMD Geode™ SC3200 Processor Data Book Architecture Overview 32581C[...]

AMD Geode™ SC3200 Processor Data Book 25 3 Signal Definitions 32581C 3.0 Signal Definitions This section defines the signal s and describes th e external interf ace of the SC3200. Figure 2-1 shows the signals organized by their functional groups . Where signals are multiple x e d, the default signal name is listed first and is separated by a plus[...]

26 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C Figure 3-1. Signal Gr oups (Continued) The remaining subsectio ns of this chapter describe: • Section 3.1 "Ball Assignments": Provides a ball assign- ment diagram and tables listing the signals sor t ed according to ball number and alphabetica lly by signal name. • S[...]

AMD Geode™ SC3200 Processor Data Book 27 Signal Definitions 32581C 3.1 Ball Assignments The SC3200 is high ly configurable as illustrated in Figure 3-1 on page 25. Strap optio ns and register programming are used to set v a rious modes of operation and specific signals on specific balls. This section describes which sig- nals are availab le on wh[...]

28 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C Figure 3-2. BGU481 Ball Assignment Di agram S S S S S S S S S 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL A B C D E F G H J K L M N P R T U V W Y AA AB AC[...]

AMD Geode™ SC3200 Processor Data Book 29 Signal Definitions 32581C T able 3-2. BGU481 Ball Assignme nt - Sort ed by Ball Number Ball No. Signal Name I/O (PU/PD) Buffer 1 Ty p e Pow e r Rail Configuration A1 V SS GND --- --- --- A2 V IO PWR --- --- --- A3 AD30 I/O IN PCI , O PCI V IO Cycle Multiplex ed D6 I/O IN PCI , O PCI A4 PCICLK0 O O PCI V IO[...]

30 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C B6 AD23 I/O IN PCI , O PCI V IO Cycle Multiplex ed A23 O O PCI B7 V SS GND --- --- --- B8 RD# O O 3/5 V IO --- CLKSEL0 I (PD 100 ) IN STRP Strap (See T able 3- 4 on page 44.) B9 WR# O O 3/5 V IO B10 V SS GND --- --- --- B11 VSYNC O O 1/4 V IO --- B12 NC --- --- - -- --- B13 V IO P[...]

AMD Geode™ SC3200 Processor Data Book 31 Signal Definitions 32581C C15 V SS GND --- --- --- C16 A V SSPLL2 GND --- --- --- C17 5,2 SLCT I IN T V IO PMR[2 3] 3 = 0 and (PMR[27] = 0 and FPCI_MON = 0) TFTD15 O O 1/4 PMR[23] 3 = 1 and (PMR[27] = 0 and FPCI_MON = 0) F_C/BE3# O O 1/4 PMR[23] 3 = 0 and (PMR[27] = 1 or FPCI_MON = 1) C18 PD4 I/O IN T , O [...]

32 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C D10 GPIO1 I/ O (PU 22.5 ) IN T , O 3/5 V IO PMR[23] 3 = 0 and PMR[13] = 0 IOCS1# O (PU 22.5 ) O 3/5 V IO PMR[23] 3 = 0 and PMR[13] = 1 TFTD12 O (PU 22.5 ) O 1/4 V IO PMR[23] 3 = 1 D11 TRDE# O O 3/5 V IO PMR[12] = 0 GPIO0 I/O (PU 22.5 ) IN TS , O 3/5 V IO PMR[12] = 1 D12 V CORE PWR[...]

AMD Geode™ SC3200 Processor Data Book 33 Signal Definitions 32581C F29 TDI I (PU 22.5 ) IN PCI V IO --- F30 GTEST I (PD 22.5 ) IN T V IO --- F31 VPCKIN I IN T V IO --- G1 STOP# I/O (PU 22.5 ) IN PCI , O PCI V IO Cycle Multiplex ed D15 I/O (PU 22.5 ) IN PCI , O PCI G2 V SS GND --- --- --- G3 V IO PWR --- --- --- G4 V SS GND --- --- --- G28 V SS GN[...]

34 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C L29 GPIO35 I/O (PU 22.5 ) IN PCI , O PCI V IO PMR[14] 4 = 0 and PMR[22] 4 = 0 LAD3 I/O (PU 22.5 ) IN PCI , O PCI PMR[14] 4 = 1 and PMR[22] 4 = 1 L30 GPIO34 I/O (PU 22.5 ) IN PCI , O PCI V IO PMR[14] 4 = 0 and PMR[22] 4 = 0 LAD2 I/O (PU 22.5 ) IN PCI , O PCI PMR[14] 4 = 1 and PMR[2[...]

AMD Geode™ SC3200 Processor Data Book 35 Signal Definitions 32581C R17 V SS GND --- --- --- R18 V SS GND --- --- --- R19 V SS GND --- --- --- R28 V SS GND --- --- --- R29 V SS GND --- --- --- R30 V SS GND --- --- --- R31 V SS GND --- --- --- T1 V CORE PWR --- --- --- T2 V CORE PWR --- --- --- T3 V CORE PWR --- --- --- T4 V CORE PWR --- --- --- T1[...]

36 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C W28 5 MD57 I/O IN T , TS 2/5 V IO --- W29 SDCLK1 O O 2/5 V IO --- W30 V SS GND --- --- --- W31 V IO PWR --- --- --- Y1 IDE_DA T A10 I/O IN TS 1 , TS 1/4 V IO PMR[24] = 0 Y2 IDE_DA T A 9 I/O IN TS 1 , TS 1/4 V IO PMR[24] = 0 Y3 IDE_DA T A 8 I/O IN TS 1 , TS 1/4 V IO PMR[24] = 0 GPI[...]

AMD Geode™ SC3200 Processor Data Book 37 Signal Definitions 32581C AE31 5 MD28 I/O IN T , TS 2/5 V IO --- AF1 IRQ14 I IN TS1 V IO PMR [24] = 0 TFTD1 O O 1/4 PMR[24] = 1 AF2 IDE_CS0# O O 1/4 V IO PMR[24] = 0 TFTD5 O O 1/4 PMR[24] = 1 AF3 SOUT1 O O 8/8 V IO --- CLKSEL1 I (PD 100 ) IN STRP Strap (See T able 3- 4 on page 44.) AF4 O VER_CUR# I IN TS V[...]

38 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C AJ12 CASA# O O 2/5 V IO --- AJ13 BA0 O O 2/5 V IO --- AJ14 MA10 O O 2/5 V IO --- AJ15 5 MD32 I/O IN T , TS 2/5 V IO --- AJ16 5 MD33 I/O IN T , TS 2/5 V IO --- AJ17 5 MD36 I/O IN T , TS 2/5 V IO --- AJ18 5 MD47 I/O IN T , TS 2/5 V IO --- AJ19 5 MD45 I/O IN T , TS 2/5 V IO --- AJ20 [...]

AMD Geode™ SC3200 Processor Data Book 39 Signal Definitions 32581C AL20 5 MD44 I/O IN T , TS 2/5 V IO --- AL21 5 MD40 I/O IN T , TS 2/5 V IO --- AL22 CKEA O O 2/5 V IO --- AL23 MA7 O O 2/5 V IO --- AL24 MA4 O O 2/5 V IO --- AL25 5 MD8 I/O IN T , TS 2/5 V IO --- AL26 5 MD10 I/O IN T , TS 2/5 V IO --- AL27 5 MD9 I/O IN T , TS 2/5 V IO --- AL28 MA12[...]

40 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C T able 3-3. BGU481 Ball Assignment - Sorted Alphabetical ly by Signal Name Signal Name Ball No. A0 U1 A1 P3 A2 U3 A3 N1 A4 P1 A5 N3 A6 N2 A7 M2 A8 M4 A9 L2 A10 L3 A11 K1 A12 L4 A13 J1 A14 K4 A15 J3 A16 E1 A17 F4 A18 E3 A19 E2 A20 D3 A21 D1 A22 D2 A23 B6 AB1C N31 AB1D N30 AB2C N29 [...]

AMD Geode™ SC3200 Processor Data Book 41 Signal Definitions 32581C F_ST OP# U29 F_TRD Y# U30 FP_VDD_ON V30, AB1 FPCI_MON A4 FPCICLK B18 FRAME# D8 GNT0# C5 GNT1# C6 GPIO0 D11 GPIO1 D10, N30 GPIO6 D28 GPIO7 C30 GPIO8 C31 GPIO9 C28 GPIO10 B29 GPIO11 AJ8 GPIO12 N29 GPIO13 M29 GPIO14 D9 GPIO15 A8 GPIO16 V31 GPIO17 A10 GPIO18 A G1 GPIO19 C9 GPIO20 A9, [...]

42 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C MD33 AJ16 MD34 AH16 MD35 AK17 MD36 AJ17 MD37 AH17 MD38 AL17 MD39 AL18 MD40 AL21 MD41 AH20 MD42 AJ20 MD43 AK20 MD44 AL20 MD45 AJ19 MD46 AK18 MD47 AJ18 MD48 AH29 MD49 AF29 MD50 AF28 MD51 AH31 MD52 AD28 MD53 AF31 MD54 AF30 MD55 AG31 MD56 Y31 MD57 W28 MD58 Y28 MD59 Y29 MD60 Y30 MD61 A[...]

AMD Geode™ SC3200 Processor Data Book 43 Signal Definitions 32581C V IO (T otal of 46) A2, A12, A30, B2, B13, B16, B19, B31, C3, C7, C10, C13, C22, C25, C29, D14, D15, D18, D23, G3, G29, K2, K29, M3, M30, W1, W31, AB3, AB29, AE3, AE29, AH4, AH14, AH18, AJ7, AJ10, AJ22, AJ25, AJ29, AK1, AK13, AK16, AK19, AK31, AL2, AL30 VPCKIN F31 VPD0 J30 VPD1 J2[...]

44 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C 3.2 Strap Options Sev eral balls are read at powe r-up that set up the state of the SC3200. These balls are typical ly multiple xed with other functions that are outputs after the power-up sequence is complete. The SC 3200 must read the state of the balls at power-up and the inter[...]

AMD Geode™ SC3200 Processor Data Book 45 Signal Definitions 32581C 3.3 Multiplexing Configuration The tables that follo w l ist multiplexing options and their configurations. Cer tain multiplexing options ma y be chosen per signal; others are av ailable only for a g roup of signa ls. Where ev er a GPIO pin is mu ltipl e xed with another func- tio[...]

46 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C GPIO A CCESS.bus N29 GPIO12 PMR[19] = 0 AB2C PMR[19] = 1 M29 GPIO13 AB2D GPIO U AR T A G 1 GPIO18 PMR[16] = 0 DTR1#/BOUT1 PMR[16 ] = 1 Infrared U ART C11 IRTX PMR[6] = 0 SOUT3 PMR[6] = 1 AK8 IRRX1 SIN3 GPIO LPC M28 GPIO32 PMR[14] = 0 and PMR[22] = 0 LAD0 PMR[14] = 1 and PMR[22] = [...]

AMD Geode™ SC3200 Processor Data Book 47 Signal Definitions 32581C V31 GPIO16 PMR[0] = 0 and FPCI_MO N = 0 PC_BEEP PMR[0] = 1 = 0 and FPCI_MON = 0 F_DEVSEL FPCI_MON = 1 GPIO PCI 2 Sub-ISA C9 GPIO19 PMR[9] = 0 and PMR[4] = 0 INTC# PMR[9] = 0 and PMR[4] = 1 IOCHRD Y PMR[9] = 1 and PMR[4] = 1 Parallel P ort TFT 3 FPCI Monitoring B18 ACK# PMR[23] = 0[...]

48 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C T able 3-7. Four-Signal/Gr oup Multiplexing Ball No. Default Alternate1 Alternate2 Alternate3 Signal Confi guration Signal Configuration Signal Configuration Signal Configuration GPIO U ART2 IDE2 Internal T est C30 GPIO7 PMR[17] = 0 and PMR[8] = 0 RTS 2# PMR[17] = 1 and PMR[8] = 0[...]

AMD Geode™ SC3200 Processor Data Book 49 Signal Definitions 32581C 3.4 Signal Descriptions Information in the tables that f ollow may hav e duplica te inf or m ati on in multiple tables . Multipl e references all contain identi - cal information. 3.4.1 System Interface Signal Name Ball No. T ype Description Mux CLKSEL1 AF3 I Fast- PCI Clock Selec[...]

50 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C X32I AJ2 I/O Crystal Connections. Connected directly to a 32.768 KHz cr ystal. This clock input is required e ven if the inter- nal RT C is not being used. Some of the inter nal clocks are derived from this clock. If an e xter nal clock is used, it should be connected to X32 I, us[...]

AMD Geode™ SC3200 Processor Data Book 51 Signal Definitions 32581C DQM7 AB31 O Data Mask Control Bits. During memor y read cycles, these outputs control whether SDRAM output buff ers are driven on the MD bus or not. All DQM signals are asser ted during read cycles. During memo r y write cycles, these outputs control whether or not MD data is wr i[...]

52 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C 3.4.4 TFT Interface Signal s Signal Name Ball No. T ype Description Mux HSYNC A11 O Horizontal Sy nc --- VSYNC B11 O V er tical Sync --- TFTDCK AA1 O TFT Clock. IDE_RST# A10 GPIO17+ IOCS0# TFTDE P2 O TFT Data Enable . IDE_CS1# B18 A CK#+FPCICLK FP_VDD_ON AB1 O TFT Po w er Control.[...]

AMD Geode™ SC3200 Processor Data Book 53 Signal Definitions 32581C 3.4.6 PCI Bus Interface Sign als Signal Name BalL No. T ype Description Mux PCICLK A7 I PCI Clock. PCICLK prov ides timing f or all transacti ons on the PCI bus . All other PCI signal s are sampled on the rising edge of PCICLK, an d all timing parameters are defined with respect t[...]

54 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C FRAME# D8 I/O Frame Cycle. F rame is dr iven b y the curre nt master to indicate the begin ning and duration of an access. FRAME# is asser ted to indicate the beginn ing of a bus transaction. While FRAME# is asser ted, data transf ers continue. FRAME# is de-asser ted when the tran[...]

AMD Geode™ SC3200 Processor Data Book 55 Signal Definitions 32581C LOCK# H3 I/O Lock Operation. LOCK# i ndicates an atomic operati on that may require multiple transactions to complete. When LOCK# is asser ted, non-exclusiv e transactions ma y pro- ceed to an address that is not currently lock ed (at least 16 bytes must be lock ed). A grant to st[...]

56 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C REQ1# A5 I Request Li nes. REQ[1:0]# indicate to the arbiter that an agent requires the bus. Each master has its o wn REQ# line . REQ# priorities (in order) are: 1) VIP 2) IDE Channel 0 3) IDE Channel 1 4) A udio 5) USB 6) External REQ0# 7) External REQ1#. Each REQ# is inter nally[...]

AMD Geode™ SC3200 Processor Data Book 57 Signal Definitions 32581C 3.4.7 Sub-ISA Interface Signals Signal Name Ball No. T ype Descr iption Mux A[23:0] See T able 3-3 on page 40. O Address Lines AD[23:0] D15 See T able 3-3 on page 40. I/O Data Bus ST OP# D14 IRD Y# D13 TRD Y# D12 PA R D11 C/BE3# D10 C/BE2# D9 C/BE1# D8 C/BE0# D[7:0] AD[31:24] BHE#[...]

58 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C 3.4.8 Low Pin Count (LPC) Bus Interface Signals Signal Name Ball No. T ype Descr iption Mux LAD3 L29 I/O LPC Address-Data. Multiplex ed co mmand, address, bidirectional data, and cycle status. GPIO35 LAD2 L30 GPIO34 LAD1 L31 GPIO33 LAD0 M28 GPIO32 LDRQ# L28 I LPC DMA Request. Enco[...]

AMD Geode™ SC3200 Processor Data Book 59 Signal Definitions 32581C IDE_IORD Y0 AD1 I I/O Ready Channels 0 and 1. When de-asser ted, the se signals extend the tr an sf er cycle of any host register access if the required device is not ready to respond to the data transfer request. Note: If selected as IDE_ IORD Y0 or IDE_IORD Y1 function(s) but no[...]

60 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C 3.4.11 Seri al P o rts (U ARTs) Interfa ce Signals Signal Name Ball No. T ype Description Mux SIN1 A G2 I Serial I nputs. Receive composite serial data from the communications link (peripheral device, modem or other data transf er device). Note: If selected as SIN2 or SIN3 fu ncti[...]

AMD Geode™ SC3200 Processor Data Book 61 Signal Definitions 32581C 3.4.12 Parallel Port Interfac e Signals Signal Name Ball No. T ype Description Mux ACK# B18 I Acknowledge. Pulsed low by the printer to in dicate that it has received data from the P arallel P or t. TFTDE+FPCICLK AFD#/DSTRB# D22 O A utoma tic Feed. When low , instructs the printer[...]

62 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C STB#/WRITE# A22 O Data Strobe. Whe n low, indicates to the printer that valid data is available at the printer por t. This signal is in TRI- ST A T E after a 0 is lo aded into the co rresponding control register bit. An external 4.7 K Ω pull-up resistor should be employ ed. Write[...]

AMD Geode™ SC3200 Processor Data Book 63 Signal Definitions 32581C 3.4.14 AC97 A udio Inte rface Sign als Signal Name Ball No. T ype Description Mux BIT_CLK U30 I A u dio Bit Clock. The serial bit clock from the codec. Note: If selected as BIT_CLK function but not used, tie BIT_CLK low. F_TRD Y# SD A T A_OUT P29 O Seri al Data Outp ut. This o utp[...]

64 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C 3.4.15 Po we r Management I nterface Sign als Signal Name Ball No. T ype Description Mux CLK32 AH8 O 32.768 KHz Output Clock --- GPWIO0 AH6 I /O General Purpose W akeup I/Os. These signals each hav e an i nternal pull-up of 100 K Ω . --- GPWIO1 AK5 --- GPWIO2 AJ6 --- LED# AL 4 O [...]

AMD Geode™ SC3200 Processor Data Book 65 Signal Definitions 32581C 3.4.16 GPIO Inte rface Signals Signal Name Ball No. T ype Description Mux GPIO0 D11 I/O GPIO P or t 0. Each signal is configured independently as an input or I/O , with or without static pull-u p , and with either open-drain or to tem-pole ou tput type. A debouncer and an interr u[...]

66 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C 3.4.17 Deb ug Monitoring Interface Signals Signal Name Ball No. T ype Description Mux FPCICLK B18 O Fast-PCI Bus Monitori ng Signals. When enabled, this group of signals provides f or mo nitoring of the inter nal F ast-PCI bus f or debug pur poses. T o enable, pull up FPCI_MON (ba[...]

AMD Geode™ SC3200 Processor Data Book 67 Signal Definitions 32581C TRST# E29 I JT A G T est Reset. This signal has an inter nal weak pul l- up resistor . F or norma l JT AG operation, this signal should be active at power-up . If the JT AG interf ace is not being used, this signal can be tied low . --- 3.4.18 JT A G Interface Sig nals (Continued)[...]

68 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C 3.4.20 P ower , Ground and No Connections 1 Signal Name Ball No. T ype Description AV SSPLL2 C16 GND Analog PLL2 Gr ound Connection. AV SSPLL3 AK3 GND Analog PLL3 Gr ound Connection. V PLL2 A17 PWR 3.3V PLL2 Analog P ower Connection. Low noise power f or PLL2 and PLL5. V PLL3 AJ4 [...]

AMD Geode™ SC3200 Processor Data Book 69 4 General Configuration Block 32581C 4.0 General Configur ation Bloc k The General Configuration bloc k inclu des registers for: • Pin Multiplexing and Miscellaneous Configuration • W A TCHD OG Timer • High-Resolution Ti mer • Clock Generators A selectable interrupt is shared by all these functions[...]

70 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C 4.2 Multiplexing, Inte rrupt Selection, and Base Ad dress Registers The registers described inT able 4-2 are used to deter mine general configuration for the SC3200. These registers also indicate which multiplex ed signals are issued via balls from which more than one sig[...]

AMD Geode™ SC3200 Processor Data Book 71 General Configuration Block 32581C 25 A C 97CKEN (Enable A C97_CLK Output). This bit enables the output drive of A C97_C LK (ball P31). 0: AC97_CLK output is HiZ. 1: AC97_CLK output is enabled. 24 TFTIDE (TFT/IDE). D etermines whether cer ta in ball s are used for TFT signals or f or ID E signals. Note tha[...]

72 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C 23 TFTPP (TFT/Parallel P or t). Determines whether cer tain balls are used for TFT or PP/AC B1/FPCI. This bit is set to 1 at power-on if the TFT_PRSNT strap (ball P29) is pulled high. Ball # 0: PP/ACB1/FPCI 1: T FT Name Add’l Dependencies Name Add’l Dependencies H2 / [...]

AMD Geode™ SC3200 Processor Data Book 73 General Configuration Block 32581C 21 IOCSEL (Select I/O Commands ) . Selects ball functions. Ball # 0: I/O Comma nd Signals 1: GPIO Signals Name Add’l Dependencies Name Add’l Dependencies F1 / D9 IOR# PMR[2] = 0 GPIO14 PMR[2] = 1 DOCR# PMR[2] = 1 Undefined PMR[2] = 0 G3 / A8 IO W# PMR[2] = 0 GPIO15 PM[...]

74 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C 12 TRDESEL (Select TRDE#). Selects ball function. Ball # 0: Sub-ISA Signal 1: GPIO Signal Name Add’l Dependencies Name Add’l Dependencies H1 / D11 TRDE# None GPIO0 None 11 EIDE (Enable IDE Outputs). This bit enables IDE output signals . 0: IDE signals are HiZ. Other s[...]

AMD Geode™ SC3200 Processor Data Book 75 General Configuration Block 32581C 16 Dela y HSYNC. HSYNC dela y by two TFT clock cycles. 0: There is no delay on HSYNC. 1: HYSNC is delay ed twice by rising edge of TFT clock. Enab les delay between VSYNC and HSYNC suited f or TFT dis- pla y . 15 Reserved. Write as read. 14 IBUS16 (In ver t BUS16). This b[...]

76 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C 0 SDBE0 (Slave Disconnect Boundar y Enable). W or ks in conjunction with the GX1 module’s PCI Control Function 2 Regis- ter (Index 41h), bit 1 (SDBE1). Sets boundaries for when the GX1 module is a PCI sla ve. SDBE[1:0] 00: Read and Wr ite disconnect on boundar ies set b[...]

AMD Geode™ SC3200 Processor Data Book 77 General Configuration Block 32581C 4.3 W A TCHDOG The SC3200 includes a W A TCHDOG function to ser ve as a f ail-safe mechanism in case the system becomes hung. When tri ggered, the W A TCHDOG mechanism retur ns the system to a known state by generating an interrupt, a n SMI, or a system rese t (depending [...]

78 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C W A TCHDOG Interrupt The W A TCHDOG interrupt (if con figured and enabled) is routed to an IRQ signal. The IRQ signal is programmable via the INTSEL register (Offset 38h, d escribed in T a ble 4-2 "Multiplexing, Interrupt Selection, and Base Address Re gis- ters"[...]

AMD Geode™ SC3200 Processor Data Book 79 General Configuration Block 32581C 4.4 High-Resolution Timer The SC3200 p rovides an accur ate time v a lue that can be used as a time stamp b y system software . This time is called the High-Resoluti on Timer . The length of the timer value can be e xten ded via software. It is nor mally enabled while the[...]

80 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C T able 4-4. High-Resolutio n Timer Register s Bit Description Offset 08h-0Bh TIMER Value Register - TMV ALUE (RO) Reset V alue: xxxxxxxxh This register contains the current value of the High-Resolution Timer . 31:0 Current Timer V alue . Offset 0Ch TIMER Status Register -[...]

AMD Geode™ SC3200 Processor Data Book 81 General Configuration Block 32581C 4.5 Cloc k Generators and PLLs This section describes the r egisters f or the clocks required by the GX1 module, Core Logic module, and the Video Processor , and how these clocks are generated. See Fig- ure 4-2 f or a clock generation diagram. The clock generators are bas[...]

82 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C 4.5.1 27 MHz Cr ystal Os cillator The inter nal oscillator employs an ex ter nal cr ystal con- nected to the on-chip amplifie r . The on-chip amplifier is accessible on the X27I input and X27O output signals. See Figure 4-3 for the recommended e xter nal circuit and T abl[...]

AMD Geode™ SC3200 Processor Data Book 83 General Configuration Block 32581C 4.5.2 GX1 Module Core Cloc k The core clock is generated by an Analog Delay Loop (ADL) clock generator from the inter nal F ast-PCI clock. The clock can be any whole-n umber multiple of the input clock between 4 and 10. P ossible v alu es are listed in T able 4-6. At pow [...]

84 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C 4.5.4 SuperI/ O Clocks The SuperI/O module requires a 48 MHz input for F ast infrared (FIR), U ART , and other functions. This clock is sup- plied by PLL4 using a multiplier value of 576/(108x3) to generate 48 MHz. 4.5.5 Core Logic Module Cloc ks The Core Logic mod ule re[...]

AMD Geode™ SC3200 Processor Data Book 85 General Configuration Block 32581C 4.5.7 Clock Registe rs T able 4-8 describes the registers of the clock generator and PLL. T able 4-8. Clock Generator Con figuration Bit Description Offset 10h Maximum Core Clock Multiplier Regist er - MCCM (RO) Reset V alue: Strapped V alue This register holds the maximu[...]

86 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C Offset 1Eh-1Fh Core Clock Frequency Control Regi ster - CCFC (R/W) Reset Value: S t rapped V alue This register controls the configuration of the core clock multiplier and the ref erence clocks. 15:14 Reserved. 13 Reserved. Must be set to 0. 12 Reserved. Must be set to 0.[...]

AMD Geode™ SC3200 Processor Data Book 87 5 SuperI/O Module 32581C 5.0 SuperI/O Module The SuperI/O (SIO) module i s a PC98 and ACPI compliant SIO that offers a single-cell solution to the most co mmonly used ISA perip herals. The SIO module in corporates: two Seri al P or ts, an Infrared Communication P or t that suppor ts FIR, MIR, HP-SIR, Shar [...]

88 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.1 Features PC98 and A CPI Compliant • PnP Configuration Register str ucture • Flexib le resour ce allocation for all logical de vi ces: — Relocatable base address — 9 P arallel IRQ routi ng options — 3 optional 8-bit DMA channels (where ap plicable) P arallel Po r t • S[...]

AMD Geode™ SC3200 Processor Data Book 89 SuperI/O Module 32581C 5.2 Module Ar chitecture The SIO module comprises a collection of generic func- tional blocks . Each fun ctional block is described in de tail later in this chapter. The beginning of this chapter describes the SIO str ucture and provides all device specific inf or mation, includi ng [...]

90 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.3 Configuration St ructure / Access This section descr ibes the st r ucture of the configuration register file, and the method of ac cessing the configuration registers. 5.3.1 Index-Data Reg ister Pair The SIO configuration access is performed via an Index- Data register pair , usi[...]

AMD Geode™ SC3200 Processor Data Book 91 SuperI/O Module 32581C Write accesses to unimplemented registers (i.e., accessing the Data register while the I ndex register points to a non- ex i sting register or the LDN is 07h o r higher than 08h), are ignored and a re ad retur ns 00h on all ad dresses e xcept for 74h and 75h (DMA co nfiguration regis[...]

92 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.4 Standard Configur ation Register s As illustrated in Figure 5-4, the Standard Configuration reg- isters are broadly divided i nto two categories: SIO Co ntrol and Configuration regi sters and Logical Device Control and Configuration registers (one per logical device, some a re op[...]

AMD Geode™ SC3200 Processor Data Book 93 SuperI/O Module 32581C T able 5-3 provides the bit definitions for the Standard Con- figuration registers. • All reser ved bits return 0 on reads, except where noted otherwise. They must not be m odified as such modifica- tion may cause unpredictable results. Use rea d-modify- write to prevent the values[...]

94 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C Index 75h DMA Channel Select 1 (R/W) Indicates selected DMA channel for DMA 1 of the logical de vice (1 - the second DMA channel in case of using more than one DMA channel). 7:3 Reserved. 2:0 DMA 1 Channel Select: This bit field selects the DMA channel for DMA 1. The valid choices ar[...]

AMD Geode™ SC3200 Processor Data Book 95 SuperI/O Module 32581C 5.4.1 SIO Control and Configuration Register s T able 5-4 lists the SIO Control and Configuration regi sters and T able 5-5 provides their bit f or mats. T able 5-4. SIO Control and C onfiguration Register Map Index T ype Name P ower Rail Reset V a lue 20h RO SID. SIO ID V CORE F5h 2[...]

96 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.4.2 Logica l Device Control and Configuration As described in Section 5.3.2 "Banked Logical Device Reg- isters" on page 90, each functio nal bloc k is a ssociated with a Logical Device Number (LDN). This section provides the register descriptions for each LDN. The registe[...]

AMD Geode™ SC3200 Processor Data Book 97 SuperI/O Module 32581C T able 5-7. RTC Confi guration Register s Bit Description Index F0h RAM Lock Register - RLR (R/W) When any non-reser ved bit in this register is set to 1, it c an be cleared only by hardware reset. 7 Block Standard RAM. 0: No effect on Standard RAM access. (Def ault) 1: Read and wr i[...]

98 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.4.2.2 LDN 01h - Sy stem Wakeup Contr ol T able 5-8 lists registers that are relev ant to the configura- tion of System W a keup Control (SWC). These registers ar e descri bed earlier in T able 5-3 "Standard Configuration Reg- isters" on page 93. T able 5-8. Relev ant SWC [...]

AMD Geode™ SC3200 Processor Data Book 99 SuperI/O Module 32581C 5.4.2.3 LDN 02h - Infrared Communication P or t or Serial P or t 3 T able 5-9 lists the configurati on registers whi ch aff ect the Infrared Communication P or t or Serial P or t 3 (IRCP/SP3). Only the last register (F0h) is describ ed here (T able 5-10). See T able 5-3 "Standar[...]

100 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.4.2.4 LDN 03h and 08h - Serial P or ts 1 and 2 Serial P o r ts 1 and 2 are iden tical, e xcep t fo r their reset val- ues. Serial Port 1 is designate d as LDN 03h and Ser ial P or t 2 as LDN 08h. T able 5-11 lists the configuration registers which aff ect Serial P or ts 1 and 2. O[...]

AMD Geode™ SC3200 Processor Data Book 101 SuperI/O Module 32581C 5.4.2.5 LDN 05h and 06h - A CCESS.bus P or ts 1 and 2 A CC ESS.b us por ts 1 and 2 (ACB1 and A CB2 ) are identi- cal. Each ACB is a tw o-wi re synchronous serial interface compatible with the A CCESS.bus ph ysical lay er . A CB1 and A CB2 use a 24 MHz internal clock. Six runtime reg[...]

102 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.4.2.6 LDN 07h - P ar allel P or t The P arallel P or t suppor ts all IEEE 1284 standard co mmu- nication modes: Compatibility (known also as Standard or SPP), Bidirectional (known also as PS/2), FIFO , EPP (known also as Mode 4) and ECP (with an optional Extended ECP mode). The P [...]

AMD Geode™ SC3200 Processor Data Book 103 SuperI/O Module 32581C 5.5 Real-Time Cloc k (R TC) The RTC pro vides timekeeping and calendar management capabilities. The RTC uses a 32.768 KHz signal as the basic clock f or timekeeping. It also includes 242 bytes of batter y-back ed RAM f o r general-pur pose use. The RTC pro vides the following functi[...]

104 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C External Elements Choose C 1 and C 2 capacitors (see Figure 5-5 on page 103) to match the cr ystal’ s load capacitance. The load capacitance C L “seen” by crystal Y is compr ised of C 1 in series with C 2 and in parallel with the parasi tic capacitance of the circuit. The para[...]

AMD Geode™ SC3200 Processor Data Book 105 SuperI/O Module 32581C 5.5.2.4 Timekeeping Data Format Time is kept in BCD or binar y format, as determined by bit 2 (DM) of Control Register B (CRB), and in either 12 or 24- hour f o rmat, as deter mined by bit 1 of this register . Note: When changing the abov e formats, re-initial ize all the time regis[...]

106 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.5.2.6 P ower Supply The device is supplied from two supply voltages, as shown in Figure 5-8: • System standby pow er supply voltage , V SB • Back up voltage , from low capacity Lithium batter y A standby v oltage, V SB , from the e xter nal AC/DC po wer supply powers the R TC [...]

AMD Geode™ SC3200 Processor Data Book 107 SuperI/O Module 32581C 5.5.2.7 System P ower States The system power state ma y be No P ow er , P ower On, P ower Off or P ower F ailure. T able 5-18 indicates the power- source combinations for each state . No other power-source combinations are valid. In addition, th e power sources and distribution for[...]

108 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.5.2.9 Interrupt Handling The RTC has a single Interr upt Request line whi ch handles the following three interrupt condi tions: • P er iodic interrupt. • Alar m interrupt. • Update end interrupt. The interrupts are generated if the respective enab le bits in the CRB register[...]

AMD Geode™ SC3200 Processor Data Book 109 SuperI/O Module 32581C 5.5.3 RTC Registers The RTC registers can be acce sse d (see Section 5.4.2.1 "LDN 00h - Real-Time Clock" on page 96) at any time dur- ing nor mal operation mode (i.e.,when V SB is within the rec- ommended operation range). This access is di sabled during ba tter y-back ed [...]

110 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C Index 03h Minutes Alarm Register - MINA (R/W) Reset T ype: V PP PU R 7:0 Minutes Alarm Data. V alues can be 00 to 59 in BCD format, or 00 to 3B in binar y format. When bits 7 and 6 are both set to 1, unconditional match is selected. See Section 5.5.2.5 "Alarms" on page 105[...]

AMD Geode™ SC3200 Processor Data Book 111 SuperI/O Module 32581C 3 Reserved. This bit is defined as “Square Wa ve Enable” b y the MC146 818 and is not suppor ted by the R TC. This bit is alwa ys read as 0. 2 Data Mod e . This bit is reset at V PP power-up reset only . 0: Enab le BCD f ormat. 1: Enable Binar y format. 1 Hour Mod e. This bit is[...]

112 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C T able 5-21 . Divider Chain Contr ol / T est Selection DV 2 DV 1 DV 0 Configuration CRA6 CRA5 CRA4 0 0 X Oscillator Disabled 0 1 0 Nor mal Operation 01 1 T e s t 10 X 1 1 X Di vider Chain Reset T able 5-22. Per iodic Interrupt Ra te Encoding Rate Select 3 2 1 0 Pe riodic Interrupt R[...]

AMD Geode™ SC3200 Processor Data Book 113 SuperI/O Module 32581C 5.5.3.1 Usage Hints 1) Read bit 7 of CRD at each system pow er-up to v ali- date the contents of the RTC registers and the CMOS RAM. When this bit is 0, the contents of these re gis- ters and the CMOS RAM are questionable. This bit is reset when the backup batter y voltage is too lo[...]

114 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.6 System W akeup Control (SWC) The SWC wak es up the system by sending a pow er-up request to the ACPI controller in response to the f ollowing maskable system e vents: • Modem ring (RI2#) • A u dio Codec e vent (SD A T A_IN2) • Programmab le Consumer Electronics IR (CEIR ) [...]

AMD Geode™ SC3200 Processor Data Book 115 SuperI/O Module 32581C 5.6.2 SWC Regist ers The SWC registers are organized in two banks. The offsets are related to a base address that is deter mined by the SWC Base Address Register in the logical device configu- ration. The lo wer three registers are common to the two banks while the upper registers ([...]

116 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C T able 5-29. Banks 0 and 1 - Common Control and Status Register s Bit Description Offset 00h W akeup Events Status Regist er - WKSR (R/W1C) Reset V alu e: 00h This register is set to 00h on power-up of V PP or software reset. It indicates which wakeup e vent and/or PME occurred. (Se[...]

AMD Geode™ SC3200 Processor Data Book 117 SuperI/O Module 32581C T able 5-30. Bank 1 - CEIR W akeup Configuration and Control Register s Bit Description Bank 1, Offset 03h CEIR Wakeup Control Register - IR WCR (R/W) Reset V alue: 00h This register is set to 00h on power-up of V PP or software reset. 7:6 Reserved. 5:4 CEIR Protocol Select. 00: RC5[...]

118 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C CEIR Wakeup Range 1 Registers These two registers (IR WTR1L and IRWTR1H) define the low and high limits of time range 1 (see T able 5-26 on page 114). The valu es are represented in units of 0.1 ms. • RC-5 protocol: The pulse width defining a half-bit cell must fall within this ra[...]

AMD Geode™ SC3200 Processor Data Book 119 SuperI/O Module 32581C 5.7 A CCESS.bus Interface The SC3200 has two ACCESS .bus (ACB) controllers . A CB is a two-wire synchronous ser ial interface compatible with the ACCESS .bus physical la yer , In tel's SMBus, and Phili ps’ I 2 C™. The ACB can be configured as a bus master or slav e, and can[...]

120 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.7.3 Acknowledge (A CK) Cycle The ACK cycle consists of two signals: the A CK clock pulse sent by the master with each byte transf erred, and the ACK signal sent by the receiving device (see Figure 5-15). The master generates the ACK cloc k pulse on the ni nth clock pulse of the by[...]

AMD Geode™ SC3200 Processor Data Book 121 SuperI/O Module 32581C 5.7.4 Acknowledge After Eve ry Byte Ru le According to this rule, the master generates an acknowl- edge clock pulse after each byte transf er, and the receiver sends an acknowledge signal after e very byte received. There are two e xceptions to this rule: • When the master is the [...]

122 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C Sending the Address Byte When the device is the active master of the A CCESS.b us (A CBST[1 ] is set), it can send the address on the bus . The address sent should not be the device’ s own address, as defined by A CBADDR[6:0] if A CBADDR [7] is set, nor should it be the globa l ca[...]

AMD Geode™ SC3200 Processor Data Book 123 SuperI/O Module 32581C Master Error Detection The ACB detects illegal Star t or Stop Conditions (i.e., a Star t or Stop Condi tion within the data transfer , or the ackno wl edge cycle) and a confl ict on the data lines o f the A CC ESS.b us. If an illegal condition is detected, ACBST[5] is set, and maste[...]

124 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.7.10 ACB Registers Each functional block is associated with a Logical Device Number (LDN) (see Section 5.3 .2 "Banked Logical De vice Registers" on page 90). A CCESS.Bus P or t 1 is assigned as LDN 05h and ACCESS .bus P or t 2 as LDN 06h. In addi- tion to the registers l[...]

AMD Geode™ SC3200 Processor Data Book 125 SuperI/O Module 32581C 2 NMA TCH (Ne w Match). (R/W1C) Wr iting 0 to this bit is ignored. If ACBCTL1[2] is set, an interrupt is sent when this bit is set. 0: Software writes 1 to this bit. 1: Address byte follo ws a Star t Condition or a repeated star t, causing a match or a global-call match. 1 MASTER. ([...]

126 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 4 A C K (Acknowledge). This bit is ignored in transmit mode . When the de vice acts as a receiv er (slav e or master), this bit holds the stop transmitting instruction that is transmitted dur ing the next ac knowledge cycle. 0: Cleared after acknowledge cycle. 1: Negative ackno wled[...]

AMD Geode™ SC3200 Processor Data Book 127 SuperI/O Module 32581C 5.8 Legacy Functional Blocks This section bri efly descr ibes the follo wing blocks that pro- vide legacy device functions: • P arallel P or t. (Similar to Par allel P or t in the National Semiconductor PC87338.) • Serial P or t 1 and Seria l P or t 2 (SP1 and SP2), UAR T functi[...]

128 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C T able 5-35. P arallel P or t Bit Map f or First Leve l Offset Offset Name Bits 76543210 000h DA T AR Data Bits AFIFO Address Bits 001h DSR Pr inter Status ACK # Status PE Status SLCT Status ERR# Status RSVD EPP Timeout Status 002h DCR RSVD Direction Control Interrupt Enable PP Inpu[...]

AMD Geode™ SC3200 Processor Data Book 129 SuperI/O Module 32581C 5.8.2 U ART Functionality (SP1 and SP2) Both SP1 and SP2 provide U ART functionality . The gene ric SP1 and SP2 suppor t ser ial data communicatio n with remote periphe ral de vice or modem using a wire d inter- f ace. The functional bloc ks can function as a standa rd 16450, 16550,[...]

130 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C T able 5-38 . Bank Selection Encoding BSR Bits Bank Selected 76543210 0xxxxxxx 0 1 0xxxxxx 1 1 1xxxx 1x 1 1 1xxxxx 1 1 11100000 2 11100100 3 T able 5-39. Bank 1 Register Map Offset T ype Name 00h R/W LBGD(L). Leg acy Baud Generator Divisor P or t (Low Byte) 01h R/W LBGD(H). Legacy B[...]

AMD Geode™ SC3200 Processor Data Book 131 SuperI/O Module 32581C T able 5-42 . Bank 0 Bit Map Register Bits O f f s e t N a m e 76543210 00h RXD RXD[7:0] (Receiv er Da ta Bits) TXD TXD[7:0] (T ransmitter Data Bits) 01h IER 1 RSVD MS_IE LS_IE TXLDL_IE RXHDL_IE IER 2 RSVD TXEMP_IE RSVD 3 / DMA_IE 4 MS_IE LS_IE TXLDL_IE RXHDL_IE 02h EIR 1 FEN[1:0] R[...]

132 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C T able 5-44 . Bank 2 Bit Map Register Bits O f f s e t N a m e 7 654321 0 00h BGD(L) BGD[7:0] (Lo w Byt e) 01h BGD(H) BGD [15:8] (High Byte) 02h EXCR1 BTEST RSVD ETDLBK LOOP RSVD EXT_SL 03h BSR BKSE BSR[6:0] (Bank Select) 04h EXCR2 LOCK RSVD PRESL[1:0] RSVD 05h RSVD Reser ved 06h RX[...]

AMD Geode™ SC3200 Processor Data Book 133 SuperI/O Module 32581C 5.8.3 IR Communications P or t (IRCP) / Serial P ort 3 (SP3) Functionalit y This section describes the IRCP/SP3 suppor t registers . The IRCP/SP3 functional block pro vides advanced, v ersa- tile serial communications features with IR capabilities. The IRCP/SP3 also suppor ts two DM[...]

134 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C T able 5-47 . Bank Selection Encoding BSR Bits Bank Selected Functionality 76543210 0 xxxxxxx 0 U A R T + I R 1 0 xxxxxx 1 1 1 xxxx1 x 1 1 1 xxxxx1 1 11100000 2 11100100 3 11101000 4 I R O n l y 11101100 5 11110000 6 11110100 7 T able 5-48. Bank 1 Register Map Offset T ype Name 00h [...]

AMD Geode™ SC3200 Processor Data Book 135 SuperI/O Module 32581C T able 5-50. Bank 3 Register Map Offset T ype Name 00h RO MID. Module and Re vi sion Identification 01h RO SH_LCR. Link Control Shadow 02h RO SH_FCR. FIFO Control Shadow 03h R/W BSR. Bank Select 04h-07h --- RSVD . Reser ved T able 5-51. Bank 4 Register Map Offset T ype Name 00h RO T[...]

136 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C T able 5-53. Bank 6 Register Map Offset T ype Name 00h R/W IRCR3. IR Contro l 3 01h R/W MIR_PW . MIR Pulse Width 02h R/W SIR_PW . SIR Pulse Width 03h R/W BSR. Bank Select 04h R/W BFPL. Beginning Flags/Preamble Length 05h-07h --- RSVD . Reser ved T able 5-54. Bank 7 Register Map Offs[...]

AMD Geode™ SC3200 Processor Data Book 137 SuperI/O Module 32581C T able 5-56 . Bank 1 Bi t Map Register Bits O f f s e t N a m e 76543210 00h LBGD(L) LBGD[7:0] (Low Byte Data) 01h LBGD(H) LBGD[15:8] (High Byte Data) 02h RSVD RSVD 03h LCR BKSE SBRK STKP EPS PEN STB WLS[1:0] BSR BKSE BSR[6:0] (Bank Select) 04h-07h RSVD RSVD T able 5-57 . Bank 2 Bi [...]

138 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 06h RFRML(L)/ RFRCC(L) RFRML[7:0] / RFRCC[7:0] (Low Byte Data) 07h RFRML(H)/ RFRCC(H) RSVD RFRML[12:8] / RFRCC[12:8] (High Byte Data) T able 5-59. Bank 4 Bit Map (Continued) Register Bits O f f s e t N a m e 76543210 T able 5-60 . Bank 5 Bi t Map Register Bits O f f s e t N a m e 76[...]

AMD Geode™ SC3200 Processor Data Book 139 6 Core Logic Mo dule 32581C 6.0 Core Logic Module The Core Logic module is an enh anced PCI-to-Sub-ISA bridge (South Br idge), this module is ACPI-compliant, and provides A T/Sub-ISA functionality . The Core Logic module also contains state-of-the-a r t p ower management. T wo bus mastering IDE controller[...]

140 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C Integrated A u dio • A C9 7 V ersion 2.0 compliant interface to audio codecs • Secondar y codec suppor t • AMC97 codec suppor t Video Processor Interface • Synchronous serial interface to the Video Processor • T ranslates video and clock control register accesses from P[...]

AMD Geode™ SC3200 Processor Data Book 141 Core Logic Mo dule 32581C 6.2.1 Fast- PCI Interface to Exte rnal PCI Bus The Core Logic modu le provides a PCI bus interface that is both a slav e for PCI cycles init iated by the GX1 module or other PCI master de vices, and a non-preemptive master f or DMA transf er cycles. It is also a standard PCI mast[...]

142 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.2.1 Video Re trace Interrupt Bit 7 of the “Serial P acket” can be used to generate an SMI whenev er a video retrace occurs within the GX1 module. This function is nor mally not used for pow e r management but f or SoftV GA routines. Setting F0 Index 83h[2] = 1 enables thi[...]

AMD Geode™ SC3200 Processor Data Book 143 Core Logic Mo dule 32581C F or example , if a channel had on e Mode 4 device and one Mode 0 de vice, then the Mode 4 de vice would hav e com- mand timings f or Mod e 0 and data timing f or Mode 4. Th e Mode 0 device would ha ve both command and data timings f or Mode 0. Note that f or the Mode 0 case, the[...]

144 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.3.4 UltraDMA/33 Mode The IDE controller of the Core Logic mod ule suppor ts UltraDMA/33. It utilizes the standard IDE Bus Master func- tionality to interface , initiate and control the transfer . UltraDMA/33 definition also i ncor porates a Cyclic Redun- dancy Checking (CRC) [...]

AMD Geode™ SC3200 Processor Data Book 145 Core Logic Mo dule 32581C 6.2.4 Universal Se rial Bus The Core Logic module provides three complete, indepen- dent USB por ts. Each por t has a Data "Negative" and a Data "P ositive" signal. The USB por ts are Open Host Controll er Interf ace (Open- HCI) compliant. The OpenHCI specific[...]

146 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.5.1 Sub-ISA Bus Cycles The ISA bus controller issues multiple ISA cycles to satisfy PCI transactions that are larger than 16 bits. A full 32-bit read or write resul ts in two 16-bit ISA transactions or f o ur 8- bit ISA transactions. The ISA controller gathers the data from m[...]

AMD Geode™ SC3200 Processor Data Book 147 Core Logic Mo dule 32581C Figure 6-3. PCI to ISA Cyc les with Delay ed T ransaction Enab led 6.2.5.3 Sub-ISA Bu s Data Steering The Core Logic mod ule performs all of the required d ata steerin g from SD[7:0] to SD[15:0] du ring nor mal 8-bit ISA cycles, as well as during DMA and ISA master cycles. It han[...]

148 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.5.5 ISA DMA DMA transf ers occur between ISA I/O periphe rals and sys- tem memory (i.e., not a vailabl e e x terna lly). The data width can be either 8 or 16 bits. Out of the sev en DMA ch annels av ailable, f our are used f or 8-bit transfers while the remain- ing three are [...]

AMD Geode™ SC3200 Processor Data Book 149 Core Logic Mo dule 32581C 6.2.5.6 ROM Interface The Core Logic mo dule positi vely decodes memor y addresses 000F0000h-000FFFFFh (64 KB) an d FFFC0000h-FFFFFFFFh (256 KB) at reset. These me mor y cycles cause the Core Logic module to clai m the cycle, and generate an ISA b us memor y cycle with ROMCS# ass[...]

150 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C Figure 6-6. PCI Change to Sub-ISA and Back 6.2.6 A T Compati bility Logic The Core Logic module integrates: • T wo 8237-equivalent DMA controllers with full 32-bit addressing • T wo 8259A-equivalent interrupt controllers providing 13 individually programmable e xter nal inter[...]

AMD Geode™ SC3200 Processor Data Book 151 Core Logic Mo dule 32581C DMA T ransfer Modes Each DMA channel can be programmed for single , blo ck , demand or cascade transf er modes. In the most commonly used mode, single transfer mode, one DMA cycle occurs per DRQ and the PCI bus is released after e very cycle. This allows the Core Logi c module to[...]

152 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C DMA Addressing Capability DMA transf ers occur over the entire 32-bit address range of the PCI bus. This is accomplished by using the DMA con- troller’ s 16-bit memor y add ress registers in conjunction with an 8-bit DMA Low P age register and an 8-bit DMA High P age register .[...]

AMD Geode™ SC3200 Processor Data Book 153 Core Logic Mo dule 32581C 6.2.6.3 Programmable Interrupt Contr olle r The Core Logic module con tains two 8259A-equivalent programmab le interrup t controllers, with eight interr upt request lines each, for a total of 16 interr upts. The PCI device supports all x86 mod es of operation except Special Fully[...]

154 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C PIC Interrupt Sequence A typical A T -compatible interrupt sequence is as follo ws. Any unmasked interrupt generates the inter nal INTR signal to the CPU. The interrupt contro ller then responds to the interrupt acknowledge (INT A) cycles from the CPU . On the first INT A cycle t[...]

AMD Geode™ SC3200 Processor Data Book 155 Core Logic Mo dule 32581C 6.2.7.1 I/O P or t 092h System Control I/O P or t 092 h allows f or a f ast keyboard asser tion of an A20# SMI and a fast ke yboard CPU reset. Decoding for this register may be disab led via F0 Index 52h[3]. The asser tion o f a fast k eyboard A20# SMI is controlled by either I/O[...]

156 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.9 P ower Mana g ement Logic The Core Logic mo dule integrates advanced pow er man- agement features including idle timers for common system peripherals, address trap registers for programmab le address ranges for I/O or memor y accesses, f o ur program- mable general purpose [...]

AMD Geode™ SC3200 Processor Data Book 157 Core Logic Mo dule 32581C 6.2.9.2 Sleep States The SC3200 suppor ts f our Sleep state s (SL1-SL3) and the Soft Off state (G2 /S5). Thes e states are fully compliant with the ACPI sp ecific ation, revision 1.0. When the SLP_EN bit (F1BAR1+I/O Offset 0Ch[13]) is set to 1, the SC3200 ente rs an SLx state acc[...]

158 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.9.3 P ower Planes Control The SC3200 suppor ts up to three power planes. Three sig- nals are used to control these power planes. T able 6-6 describes th e signals and when each is asser ted. These signals allow control of the po wer of system devices and the SC3200 itse lf . [...]

AMD Geode™ SC3200 Processor Data Book 159 Core Logic Mo dule 32581C P ower Button The power b utton (PWRBTN# ) input provides two e vents: a wak e request, a nd a sleep request. For both these e vents , the PWRBTN# signal is d ebounced (i.e., the signal state is transf erred only after 1 4 to 16 ms without transitions, to ensure that the signal i[...]

160 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.10 P ower Management Programming The power management resources provided by a com- bined GX1 module and Core Logic module base d system suppor ts a high efficiency power management implementa- tion. The follo wing explanations per tain to a full-featured “notebook” power [...]

AMD Geode™ SC3200 Processor Data Book 161 Core Logic Mo dule 32581C The automatic speedup events (video and IRQ) f or Sus- pend Modulation should be used together with software- controlled speedup register s fo r major I/O ev ents such as any access to the FDC, HDD , or parallel/serial por ts, since these are indications of major system activitie[...]

162 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.10.3 Peripheral P ower Manag ement The Core Logic module provides peripheral power man- agement using a combination of device idle timers, address traps, and general pur pose I/O pins. Idle timers are used in conjunction with traps to suppor t powering down per ipheral device[...]

AMD Geode™ SC3200 Processor Data Book 163 Core Logic Mo dule 32581C P ower Managem ent SMI Status Repor ting Registers The Core Logic mod ule updates status registers to reflect the SMI sources. P ower management SMI sources are the de vice idle timers, address traps, and general purpos e I/O pins. P ower management e vents are repor ted to the G[...]

164 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.10.4 Po w er Manageme nt Programming Summary T able 6-9 provides a programming register summar y for the power management timers, tr aps, and functions. For com- plete bit inform ation regarding th e registers listed in T able 6-9, ref er to Section 6.4.1 "Br idge, GPIO [...]

AMD Geode™ SC3200 Processor Data Book 165 Core Logic Mo dule 32581C 6.2.11 GP IO Interface Up to 64 GPIOs in the in the Core Logi c module are pro- vided f or system control. For further information, see Sec- tion 4.2 "Multiplexing, Inte rr upt Selection, and Base Address Registers" on page 70 an d T able 6-30 "F0BAR0+I/ O Offset: [...]

166 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C Physical Region Descriptor T able Address Bef ore the bus master starts a master transfer it must be pro- grammed with a pointer (PRD T able Address register ) to a Ph ysical Region Descr iptor T able. This pointer sets the star t- ing memor y location of the Physical Region Desc[...]

AMD Geode™ SC3200 Processor Data Book 167 Core Logic Mo dule 32581C 4) Read the SMI Status register to clear the Bus Master Error and End of P age bits (bits 1 and 0). Set the correct directi on to the Read or Write Co ntrol bit (Command register bit 3). Note that the direction of the data transfer of a par ticular bus master is fixed and therefo[...]

168 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.12.2 AC97 Codec Interface The AC97 codec (e.g., LM4548) is the master of the serial interf ace and generates the clocks to Core Logic module. Figure 6-13 shows the signal connections between two codecs and the SC3 200: • Codec1 can be AC97 Re v . 1.3 or higher compliant. ?[...]

AMD Geode™ SC3200 Processor Data Book 169 Core Logic Mo dule 32581C 6.2.12.3 VSA T echnolo gy Support Hard ware The Core Logic mod ule incor porates the requi red hard- ware in order to suppor t the Vir tual System Arch itecture (VSA) technology f or cap ture and playbac k of audio using an external codec. This el iminates much of the hardware tr[...]

170 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C In F ast Path Write, the Core Logic modul e responds to writes to the following addresses: 388h, 38Ah, 38Bh, 2x0h, 2x2h, and 2x8h. T able 6-38 on page 262 shows the bit formats of the sec- ond lev el SMI status repor ting registers and the F ast Path Read/Write programming bits. [...]

AMD Geode™ SC3200 Processor Data Book 171 Core Logic Mo dule 32581C 6.2.12.4 IRQ Configuration Registers The Core Logic modul e provides the ability to set an d clear IRQs inter nally through software control. If the IRQs are configured for softw are control, they do not respond to ex ter nal hardware. There are two registers provided for this f [...]

172 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.12.6 LPC Interface Signal De finitions The LPC specification lists seven required and six optional signals for supporti ng the LPC interface. Man y of the sig- nals are the same sign als found on the PCI interf ace and do not require any new pins on the host. Required signals[...]

AMD Geode™ SC3200 Processor Data Book 173 Core Logic Module - PCI Configuration Space an d Access Methods 32581C 6.3 Register Descriptions The Core Logic modul e is a multi-function module. Its reg- ister space can be broadly divided into three categories i n which specific types of registers are located: 1) Chipset Register Space (F0-F5) (Note t[...]

174 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Re gister Summary 32581C 6.3.2 Register Su mmary The tables in this subsection summarize the registe rs of the Core Logic module. Included in the tables are the regis- ter’ s reset values and page ref erenc es where the bit f or- mats are f ound. Note: Function 4 (F4) is f or Video P[...]

AMD Geode™ SC3200 Processor Data Book 175 Core Logic Module - Register Summar y 32581C 6Ch-6Fh 32 R/W ROM Mask Register 0000FFF0h P age 198 70h-71h 16 R/W IOCS1# Base Address Register 0000h Page 199 72h 8 R /W IOCS1# Contro l Register 00h P age 199 73h 8 --- Rese rved 00h P age 1 99 74h-75h 16 R/W IOCS0 Base Address Register 0000h P age 199 76h 8[...]

176 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Re gister Summary 32581C B8h 8 RO DMA Shadow Register xxh P age 215 B9h 8 RO PIC Shadow Register xxh P age 215 BAh 8 RO PIT Shado w R egister xxh P age 215 BBh 8 RO R TC Index Shadow Register xxh Page 216 BCh 8 R/W Clock Stop Control Register 00h P age 216 BDh-BFh --- --- Rese rved 00h[...]

AMD Geode™ SC3200 Processor Data Book 177 Core Logic Module - Register Summar y 32581C T able 6-15 . F0B AR0: GPIO Support Register s Summar y F0BAR0+ I/O Offset Width (Bits) T ype Name Reset Va l u e Reference (T able 6-30) 00h-03h 32 R/W GPDO0 — GPIO Data Out 0 Register FFFFFFFFh Page 222 04h-07h 32 RO GPDI0 — GPIO Data In 0 Register FFFFFF[...]

178 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Re gister Summary 32581C T able 6-17. F1: PCI Header Registe rs f or SM I Status and A CPI Su ppor t Summary F1 Index Width (Bits) T ype Name Reset Va l u e Reference (T able 6-32) 00h-01h 16 RO V endor Identification Registe r 100Bh Page 234 02h-03h 16 RO Device Identification Registe[...]

AMD Geode™ SC3200 Processor Data Book 179 Core Logic Module - Register Summar y 32581C T able 6-19. F1B AR1: ACPI Support Reg isters Summary F1BAR1+ I/O Offset Width (Bits) T ype Name Reset Va l u e Reference (T able 6-34) 00h-03h 32 R/W P_CNT — Processor Control Re gister 00000000h P age 245 04h 8 RO Reser ved, do not read 00h Page 245 05h 8 R[...]

180 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Re gister Summary 32581C T able 6-20. F2: PCI Header Register s for IDE Contr oller Suppor t Summary F2 Index Width (Bits) T ype Name Reset Va l u e Reference (T able 6-35) 00h-01h 16 RO V endor Identification Registe r 100Bh Page 255 02h-03h 16 RO Device Identification Register 0502h [...]

AMD Geode™ SC3200 Processor Data Book 181 Core Logic Module - Register Summar y 32581C T able 6-21 . F2BAR4: IDE Controller Support Register s Summary F2BAR4+ I/O Offset Width (Bits) T ype Name Reset Va l u e Reference (T able 6-36) 00h 8 R/W IDE Bus Master 0 Command Register — Primar y 00h Page 259 01h --- --- Not Used --- Page 259 02h 8 R/W I[...]

182 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Re gister Summary 32581C T able 6-23. F3BAR0: A udi o Suppor t Registers Summar y F3BAR0+ Memory Offset Width (Bits) T ype Name Reset Va l u e Reference (T able 6-38) 00h-03h 32 R/W Codec GPIO Status Register 00000000h P age 262 04h-07h 32 R/W Codec GPIO Control Register 00000000h P ag[...]

AMD Geode™ SC3200 Processor Data Book 183 Core Logic Module - Register Summar y 32581C T able 6-24. F5 : PCI Header Registers for X-Bus Expansion Suppo rt Summar y F5 Index Width (Bits) T ype Name Reset Va l u e Reference (T able 6-39) 00h-01h 16 RO V endor Identification Registe r 100Bh Page 276 02h-03h 16 RO Device Identification Register 0505h[...]

184 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Re gister Summary 32581C T able 6-26. PCIUSB: USB PCI Confi guration Regis ter Summary PCIUSB Index Width (Bits) T ype Name Reset V alue Reference (T able 6-41) 00h-01h 16 RO V endor Identification 0E11h P age 282 02h-03h 16 RO Device Identification A0F8h Page 282 04h-05h 16 R/W Comman[...]

AMD Geode™ SC3200 Processor Data Book 185 Core Logic Module - Register Summar y 32581C T able 6-27. USB_BAR: USB Controller Regist ers Summary USB_BAR0 +Memory Offset Width (Bits) T ype Name Reset V alue Reference (T able 6-42) 00h-03h 32 R/W HcRevision 00000110h P age 285 04h-07h 32 R/W HcControl 00000000h P age 285 08h-0Bh 32 R/W HcCommandStatu[...]

186 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Re gister Summary 32581C T able 6-28. ISA Legacy I/O Re gister Summary I/O P ort T ype Name Reference DMA Channel Control Registers (T able 6-43) 000h R/W DMA Channel 0 Address Register Page 295 001h R/W DMA Channel 0 T ransfer Count Register P age 295 002h R/W DMA Channel 1 Address Re[...]

AMD Geode™ SC3200 Processor Data Book 187 Core Logic Module - Register Summar y 32581C 487h R/W DMA Channel 0 High P age Register P age 300 489h R/W DMA Channel 6 High P age Register P age 300 48Ah R/W DMA Channel 7 High Page Register P age 300 48Bh R/W DMA Channel 5 High Page Register P age 300 Programmable Interval Timer Registers (T able 6-45)[...]

188 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 6.4 Chipset Register Space The Chipset Register Space of the Core Logic module is comprised of six separate functions (F0-F5), each with its own register space . Base Address Registers (BARs) in each PCI header register space set the[...]

AMD Geode™ SC3200 Processor Data Book 189 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 4 Memory Write an d In validate. Allow the Core Logic module to do memory write and invalidate cycles , if the PCI C ache Line register (F0 Index 0Ch) is set to 32 bytes (08h). 0: Disable. (Def ault) 1: Enab le. 3 Special Cycles. All[...]

190 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 08h Device Revision ID Register (RO) Reset V alue: 00h Index 09h-0Bh PCI Class Co de Register (RO) Reset V alue: 060100h Index 0Ch PCI Cache Line Siz e Register (R/W) Reset V alue: 00h 7:0 PCI Cache Line Size Register . This re[...]

AMD Geode™ SC3200 Processor Data Book 191 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 40h PCI Function Control Register 1 (R/W) Reset V alue: 39h 7:6 Reserved. Must be set to 0. 5 Reserved. Must be set to 0. 4 PCI Subtractive Decode . 0: Disable transf er of subtractive decode address to e x ternal PC I bus . Ex[...]

192 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 1 P ower Management Configuration T rap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function 1 (F1) register space, an SM I is generated. Write s are trapped; access to the register is d[...]

AMD Geode™ SC3200 Processor Data Book 193 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 2 IDE Reset. Reset IDE bus . 0: Disab le. 1: Enab le (drive ID E_RST # low ). Write 0 to clear. This bit is lev el-sensitive and must be cleared after the reset is enab led. Note: When X-Bus W ar m Star t is enabled (bit 0 = 1) or du[...]

194 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 4Ch-4Fh T op of System Memory (R/W ) Rese t V alue: FFFFFFFFh 31:0 T op of System Memory . Highest address in system used to deter mine acti ve decode for e xter nal PCI mastered memor y cycles. If an external PCI master reques[...]

AMD Geode™ SC3200 Processor Data Book 195 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 52h ROM/A T Logic Control Register (R/W) Re set V alue: 98h 7 Snoop Fast Keyboar d Gate A20 an d Fast Reset. Enab les the sno op logic associat ed with keyboard commands f or A20 Mask and Reset. 0: Disable snooping. The ke yboa[...]

196 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 54h-59h Reser ved Reset V alue: 00h Index 5Ah Decod e Control Register 1 (R/W) Re set V alue: 01h Indicates PCI positive or negativ e decodi ng f or various I/O por ts on the ISA bus. Note: P ositive decoding b y the Core Logic[...]

AMD Geode™ SC3200 Processor Data Book 197 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 4 Secondary IDE C ontroller P ositive Decode . Selects PCI positive or subtr active decoding f or accesses to I/O po rts 170h- 177h and 376h-377h (excluding writes to 377h). 0: Subtractive . Subtractiv ely decoded IDE addresses are f[...]

198 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 60h-63h ACPI Contr ol Re gister (R/W) Reset V alue: 00000000h 31:8 Reserved. Must be set to 0. 7 SUSP_3 V Shut D own PLL5. Allow interna l SUSP_3V to shut down PLL5. 0: Clock generator is stopped when internal SUSP_3V is active[...]

AMD Geode™ SC3200 Processor Data Book 199 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 70h-71h IOCS1# Base Address Re gister (R/W) Reset Value: 0000h 15:0 I/O Chip Select 1 Base Address. This 16-bit value represent s the I/O base address used to enable assertion of IOCS1# (ball D10 or N30 - see PMR[23] in T able [...]

200 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 78h-7Bh DOCCS# Base Address Register (R/W) Reset V alue: 00000000h 31:0 DiskOnChip Chip Select Base Address. This 32-bit v alue represents the memor y base address used to ena ble assertion of DOCCS# (BGU481 ball A9 or N31, see[...]

AMD Geode™ SC3200 Processor Data Book 201 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 1 Idle Timers. Device idle timers. 0: Disab le. 1: Enab le. Note: Disab l e at this lev el does n ot reload the timers on the enable. The timers are disab led at their current counts. This bit has no affect on the Suspend Modulation [...]

202 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 3 Keyboar d/Mouse Idle Timer Ena ble. T urn on K eyboard/Mouse Idle Timer Coun t Register (F0 Index 9Eh) and generate an SMI when the timer expires . 0: Disab le. 1: Enab le. If an access occurs in the address ranges listed belo w , [...]

AMD Geode™ SC3200 Processor Data Book 203 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 82h Po wer Management Enable Register 3 (R/W) Re set V alue: 00h 7 Video Access T rap. If this bit is enabled and an access occurs in the video address range (sets bit 0 of the GX1 module’ s PSERIAL register), an SMI is gener[...]

204 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 1 Floppy Disk Access T rap. 0: Disab le. 1: Enab le. If this bit is enabled and an access occurs in the address ranges listed below , an SMI is generated. — Primar y floppy disk: I/O P or t 3F2h-3F5h, 3F7h. — Secondary floppy dis[...]

AMD Geode™ SC3200 Processor Data Book 205 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 2 Video Retrace Interrupt SMI. Allow SMI generation whenev er video retrace occurs. 0: Disab le. 1: Enab le. This inf or mation is decoded from the serial conn ection (PSERIAL r egister , bit 7) from the GX1 module. This function is [...]

206 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 85h Second Level PME/SMI Status Mirror Register 2 (RO) Reset Value: 00h The bits in this register c ontain second lev el status repor ting. T o p lev el st atus is repor ted in F1BAR0+I/O Offset 00h/02h[0]. This register is cal[...]

AMD Geode™ SC3200 Processor Data Book 207 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 86h Second Level PME/SMI Status Mirror Register 3 (RO) Reset Value: 00h The bits in this register c ontain second lev el status repor ting. T o p lev el st atus is repor ted in F1BAR0+I/O Offset 00h/02h[0]. This register is cal[...]

208 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 87h Second Level PME/SMI Status Mirror Register 4 (RO) Reset Value: 00h The bits in this register cont ain second lev el status repor ting. T o p le vel status is reported at F 1BAR0+I/O Offset 00h/02h[0]. This register is call[...]

AMD Geode™ SC3200 Processor Data Book 209 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 89h General Purpose Timer 1 Control Register (R/W) Reset V alue: 00h 7 General Purpose Timer 1 TImebase . Selects timebase for General Purpose Timer 1 (F0 Index 88h). 0: 1 second. 1: 1 millisecond. 6 Re-trigger General Purpose [...]

210 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 8Ah General Purpose Timer 2 Count Register (R/W) Reset V alu e: 00h 7:0 GPT2_COUNT . This field rep resents the load value f or General Purpose Timer 2 . This value can represent either an 8-bit or 16-bit counter (configured in[...]

AMD Geode™ SC3200 Processor Data Book 211 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 8Eh VGA Timer Count Register (R/W) Reset V alue: 00h 7:0 V GA Tim er Load V alue . This field represents the load value for V GA Timer . It is loaded into the counter w hen the timer is enabled (F0 Inde x 83h[3] = 1). The count[...]

212 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 96h Su spend Configuration Register (R/ W) Re set V alue: 00h 7:3 Reserved. Must be set to 0. 2 Suspend Mode Conf iguration. Special 3V Suspend mode to suppor t powering down the GX1 module dur ing Suspend. 0: Disab le. 1: Enab[...]

AMD Geode™ SC3200 Processor Data Book 213 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 9Eh-9Fh Keyboard / Mouse Idle Timer Count Register (R/W) Rese t V alue: 0000h 15:0 Keyboar d / Mouse Idle Timer Coun t. This idle timer determines when the key board and mouse are not in use so that the LCD screen can be blank [...]

214 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index A Ch-ADh Secondary Hard Disk Idle Timer Count Reg ister (R/W) Reset V alue: 0000h 15:0 Secondary Hard Disk Idle Timer Count. This idle timer is used to determine whe n the secondary hard disk is not in use so that it can be pow[...]

AMD Geode™ SC3200 Processor Data Book 215 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index B8h DMA Shadow Register (RO) Re set V alue: xxh 7:0 DMA Sha dow . This 8-bit port seq uences through the follo wing list of shadowed DMA Controller registers. At po wer on, a pointer star ts at the first register in the list an[...]

216 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index BBh R T C Index Shadow Register (R O) Reset V alue: xxh 7:0 RTC Index Shadow . The R T C Shadow register contains the last written value of the R TC Index register (I/O P or t 070h). Index BCh Cloc k Stop Con trol Register (R/W[...]

AMD Geode™ SC3200 Processor Data Book 217 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index CCh User Defined Device 1 Control Register (R/W) Reset V alue: 00h 7 Memory or I/O Mapp ed. Deter mines how User Defined Device 1 is mapped. 0: I/O . 1: Memory . 6:0 Mask. If bit 7 = 0 (I/O): Bit 6 0: Disable write cycle tracki[...]

218 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index ECh Timer T est Register (R/W) Reset V alue: 00h 7:0 Timer T est V alue . The Timer T est register is in tended only for test and deb ug pur poses. It is not intended for setting opera- tional timebases. F or nor mal operation,[...]

AMD Geode™ SC3200 Processor Data Book 219 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 4 User Defined Device Idle Timer 1 (UDEF1) SMI Status. Indicates whether or not an SMI was caused by e xpiration of User Defined Device 1 (UDEF1) Idle Timer Count Register (F0 Inde x A0h). 0: No . 1: Y es. T o enable SMI generation, [...]

220 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 3 Keyboar d/M ouse Access T rap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the ke yboard or mouse. 0: No . 1: Y es. T o enable SMI generation, set F0 Inde x 82 h[3] = 1. 2 Parallel/Serial Access[...]

AMD Geode™ SC3200 Processor Data Book 221 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 2 Codec SD A T A_IN SMI Status. Indicates whether or not an SMI was ca used by AC97 Codec producing a positiv e edge on SD A T A_IN. 0: No . 1: Y es. T o enable SMI generation, set F0 Inde x 80 h[5] = 1. 1 RTC Alarm (IRQ8#) SMI Statu[...]

222 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 6.4.1.1 GPIO Supp ort Registers F0 Inde x 10h, Base Address Register 0 (F0BAR0) poin ts to the base address of where the GPIO run time and configu- ration registers are located. T able 6-29 giv es the bit f or mats of I/O mapped regi[...]

AMD Geode™ SC3200 Processor Data Book 223 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Offset 10h-13h GPDO1 — GPIO Data Out 1 Register (R/W) Reset V alue: FFFF FFFFh 31:0 GPIO Data Out. Bits [31:0] of this register correspond to GPIO63-GPIO32 signals, respective ly . The value of each bit determines the value driven [...]

224 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 5:0 Signal Select. Selects the GPIO signal to be configured in the Bank se lected via bit 5 setting (i.e., Bank 0 or Bank 1). See T able 4-2 on page 70 f or GPIO ba ll muxing options. GPIOs without an associated ball n u mber are not[...]

AMD Geode™ SC3200 Processor Data Book 225 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 4 PME Edge/Level Select. Selects the type (edge or lev el) of the signal that issues a PME from the selected GPIO signal. 0: Edge input. (Default) 1: Lev el input. For normal operation, alwa ys set this bit to 0 (edge input ). Errati[...]

226 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 6.4.1.2 LPC Support Registers F0 Inde x 14h, Base Address Register 1 (F0BAR1) poin ts to the base address of the regist er space that contains the configuration registers for LPC suppor t. T able 6-31 gives the bit formats of the I/O[...]

AMD Geode™ SC3200 Processor Data Book 227 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 8 IRQ8# Source. Selects the interface source of the IRQ8# signal. 0: ISA - IRQ8# inter nal signal. (Connected to inter nal RTC .) 1: LPC - SERIRQ (ball J31). 7 IRQ7 S our ce . Selects the interf ace source of the IRQ7 signal. 0: ISA [...]

228 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 14 IRQ14 P olar ity . If LPC is selected as the interface source f or IRQ14 (F0BAR1+I/O Offset 00h[14] = 1), this bit allows signal polarity s election. 0: Active high. 1: Active lo w . 13 IRQ13 P olar ity . If LPC is selected as the[...]

AMD Geode™ SC3200 Processor Data Book 229 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 2 SMI# P o larity . This bit allows signal polar ity se lection of the SMI# generated from LPC. 0: Active high. 1: Active lo w . 1 IRQ1 Polarity . If LPC is selected as the interf ace source for IRQ1 (F0BAR1+I/O Offset 00h[1] = 1), t[...]

230 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 2 DRQ2 Source. Selects the interface source of the DRQ2 signal. 0: ISA - DRQ2 (unava ilable e xter nally). 1: LPC - LDR Q# (ball L28). 1 DRQ1 Source. Selects the interface source of the DRQ1 signal. 0: ISA - DRQ1 (unava ilable e xter[...]

AMD Geode™ SC3200 Processor Data Book 231 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 1 LPC Serial Port 0 Addressing. Serial P or t 0 addresses. See bit 16 for decode . Address selection made via F0BAR1+I/O Offset 14h[4:2]. 0 LPC Parallel P or t Addressing. P arallel P or t addresses. See bit 16 for decode. Address se[...]

232 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Offset 18h-1Bh LAD_D1 — LPC Address D ecode 1 Register (R/W) Reset V alue: 00000000h 31:16 Reserved. Must be set to 0. 15:9 Wide Generic Base Address Select. Defines a 512 byte space. Can be mapped anywhere in the 64 KB I/O space. [...]

AMD Geode™ SC3200 Processor Data Book 233 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 3 LPC Timeout Err or Status. Indicates whether or not an error was generated by a timeout on LPC . 0: No . 1: Y es. Write 1 to clear. 2 LPC Error Write Status. Indicates whether or not an error was generated during a write o peration[...]

234 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 6.4.2 SMI Status an d A CPI Regi sters - Function 1 The register space design ated as Function 1 (F1) is used to configure the PCI por tion of suppor t hardware for the SMI Status and ACPI Support registe rs. The bit f or mats for th[...]

AMD Geode™ SC3200 Processor Data Book 235 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C 6.4.2.1 SMI Status Suppor t Registers F1 Index 10h, Base Address Register 0 (F1BAR0), p oints to the base address f or SMI Status register locations. T able 6-33 gives the bit f or mats of I/O mapped SMI Status regis- ters accessed thro[...]

236 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 6 SMI Source is a V GA Timer Event. Indicates whether or not an SMI was caused by the e xpiration of the V GA Timer (F0 Index 8Eh). 0: No . 1: Y es. T o enable SMI generation, set F0 Inde x 83 h[3] to 1. 5 SMI Source is Video Retrace[...]

AMD Geode™ SC3200 Processor Data Book 237 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C 12 SMI Source is NMI. (Read to Clear) Indicates whether or not an SMI was caused by NMI activity . 0: No . 1: Y es. 11 SMI Source is IRQ2 of SIO Module . (Read to Clear) Indicates whether or not an SMI was caused by IRQ2 of the SIO modu[...]

238 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 1 SMI Source is A udio Subsystem. (Read Only , Read Does Not Clear) Indicates whethe r or not an SMI was caused by the audio subsystem. 0: No . 1: Y es. The second lev el of status is found in F3BAR0+Memor y Offset 10h/12h. 0 SMI Sou[...]

AMD Geode™ SC3200 Processor Data Book 239 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C 0 SMI Source is Expired General Purpose Timer 1. Indicates whether or not an SMI wa s caused by the e xpiration of Gen- eral Pur pose Timer 1 (F0 Index 88h). 0: No . 1: Y es. T o enable SMI generation, set F0 Inde x 83 h[0] = 1. Offset [...]

240 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C Offset 08h-09h SMI Speedup Disable Register (Read to Enable) Reset V alue: 0000h 15:0 SMI Speedup Disable. If bit 1 in the Susp end Configuration Register is se t (F0 Index 96h[1] = 1), a read of this register inv okes the SMI handle[...]

AMD Geode™ SC3200 Processor Data Book 241 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Offset 22h-23h Second Level ACPI PME/SMI Status Register (RC) Reset V alue: 0000h The bits in this register cont ain second lev el of SMI status repor ting. T op le v el is repor ted in F 1BAR0+I/O Offset 00h/02h[2]. Reading this regist[...]

242 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 21 EXT_SMI5 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an asser tion of EXT_SMI5. 0: No . 1: Y es. T o enable SMI generation, set bit 5 to 1. 20 EXT_SMI4 SMI Status. (Read to Clear) Indicates whether or[...]

AMD Geode™ SC3200 Processor Data Book 243 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C 10 EXT_SMI2 SMI Status. (Read Only) Indicates whether or not an SMI was caused b y an asser tion of EXT_SMI2. 0: No . 1: Y es. T o enable SMI generation, set bit 2 to 1. 9 EXT_SMI1 SMI Status. (Read Only) Indicates whether or not an SMI[...]

244 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 0 EXT_SMI0 SMI Enable. When this bit is asser ted, allow EXT_SMI0 to generate an SMI on negative-edge e vents. 0: Disab le. 1: Enab le. T op le vel SMI status is repor ted at F1BAR0+00h/02h[10]. Second lev el SMI status is repor ted [...]

AMD Geode™ SC3200 Processor Data Book 245 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C 6.4.2.2 A CPI Suppor t Registers F1 Index 40h, Base Address Register 1 (F1BAR1), p oints to the base addre ss of wher e the ACPI Suppor t registers are located. T able 6-34 shows the I/O mapped A CPI Sup- por t registers accessed throug[...]

246 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 0 PWRBTN_DBNC_DIS (Power Button Debounce). When enabled, a high-to-low or lo w- to-high transition of greater than 15.8 ms is required on PWRBTN# before it is recognized. 0: Enable. (Def ault) 1: Disable. (No debounce) Offset 08h-09h[...]

AMD Geode™ SC3200 Processor Data Book 247 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C 4 BM_STS (Bus Master Status). Indicates if PME was caused by a system bus master requesting the system bus. 0: No . 1: Y es. For the PME to gener ate an SCI, set F1BAR1+I/O Offset 0Ch[1] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2[...]

248 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 13 SLP_EN (Sleep Enable). (Write Only) Allow the system to sequence into the sl eeping state associated with the SLP_TYPx (bits [12:10]). 0: Disab le. 1: Enab le. This is a write only bit and reads of this bit alwa ys retur n a 0. Th[...]

AMD Geode™ SC3200 Processor Data Book 249 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Offset 0Fh ACPI_BIOS_EN Register (R/W) Reset V alu e: 00h 7:2 Reserved. Must be set to 0. 1 BIOS_RLS (BIOS Release). (Write Only) When this bit is asser ted, allow the BIOS to release control o f the global lock. 0: Disab le. 1: Enab le[...]

250 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 7 Reserved. Must be set to 0. 6 USB_STS. Indicates if PME was caused b y a USB interr upt ev ent. 0: No . 1: Y es. Write 1 to clear. For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[6] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. ([...]

AMD Geode™ SC3200 Processor Data Book 251 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Offset 12h-13h GPE0_EN — General Purpose E ven t 0 Enable Register (R/W) Reset V alue: 0000h In order for the A CPI ev ents described below to generate an SCI, the SCI_EN bit must also be set (F1BAR1+I/O Offset 0Ch[0 ] = 1) . The SCIs[...]

252 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C Offset 14h GPWIO Control Register 1 (R/W) Re set V alue: 00h 7:4 Reserved. Must be set to 0. 3 Reserved. 2 GPWIO2_POL. Select GPWIO2 polarity . 0: Active high 1: Active lo w 1 GPWIO1_POL. Select GPWIO1 polarity . 0: Active high 1: Ac[...]

AMD Geode™ SC3200 Processor Data Book 253 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Offset 16h GPWIO Data Register (R/W) Reset V alue: 00h This register contains the direct values of the GPWIO2-GPWIO0 pins. Write operations are valid only f or bits defin ed as outputs . Reads from this register read the last wr itten v[...]

254 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 3:0 SCI_IRQ_ROUTE. SCI is routed to: 0000: Disable 0100: IRQ4 1000: IRQ8 1100: IRQ12 0001: IRQ1 0101: IRQ5 1001: IRQ9 1101: IRQ13 0010: Reser ved 0010: IRQ6 1010: IRQ10 1110: IRQ14 0011: IRQ3 0011: IRQ7 1011: IRQ11 1111: IRQ15 For mo[...]

AMD Geode™ SC3200 Processor Data Book 255 Core Logic Module - IDE Controller Registers - Function 2 32581C 6.4.3 IDE Controller Regis ters - Function 2 The register space design ated as Function 2 (F2) is used to configure Channels 0 and 1 and the PCI por tion of sup- por t hardware fo r the IDE controllers. The bit formats for the PCI Header/Cha[...]

256 AMD Geode™ SC3200 Processor Data Book Core Logic Module - IDE C ontroller Registers - Function 2 32581C Index 30h-3Fh Reserved Reset V alue: 00h Index 40h-43h Channel 0 Drive 0 PI O Register (R/W) Reset V alue: 00009172h If Index 44h[31] = 0, F or mat 0. Bits [15:0] configure the same timing control for both command and data. Format 0 setting[...]

AMD Geode™ SC3200 Processor Data Book 257 Core Logic Module - IDE Controller Registers - Function 2 32581C Index 44h-47h Channel 0 Drive 0 DMA C ontrol Register (R /W) Reset V alue: 00077771h The structure of this register depends on the value of bit 20. If bit 20 = 0, Multiword DMA Settings for a F a st-PCI clock frequency of 33.3 MHz: — Multi[...]

258 AMD Geode™ SC3200 Processor Data Book Core Logic Module - IDE C ontroller Registers - Function 2 32581C Index 50h-53h Channel 1 Drive 0 PI O Register (R/W) Reset V alue: 00009172h Channel 1 Drive 0 Programmed I/O Control Register . See F2 Index 40h f or bit descr iptions. Index 54h-57h Channel 1 Drive 0 DMA C ontrol Register (R /W) Reset V al[...]

AMD Geode™ SC3200 Processor Data Book 259 Core Logic Module - IDE Controller Registers - Function 2 32581C 6.4.3.1 IDE Controller Support Registers F2 Index 20h, Base Address Register 4 (F2BAR4), p oints to the base address o f where the registers for IDE control- ler configuration are located. T able 6-36 giv es the bit for- mats of the I/O mapp[...]

260 AMD Geode™ SC3200 Processor Data Book Core Logic Module - IDE C ontroller Registers - Function 2 32581C Offset 08h IDE Bus Master 1 Co mmand Register — Secondar y (R/W) Reset V alue: 00h 7:4 Reserved. Must be set to 0. Must retur n 0 on reads. 3 Read or Write Control. Sets the direction of bus master transf ers. 0: PCI reads are performed. [...]

AMD Geode™ SC3200 Processor Data Book 261 Core Logic Module - Audio Registers - Function 3 32581C 6.4.4 Audio Register s - Function 3 The register designated as Func tion 3 (F3) is used to con- figure the PCI por tion of suppor t hardware f o r the audio registers. The bit formats for the PCI Header regi sters are given in T able 6-37. A Base Add[...]

262 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Audio Registers - Function 3 32581C 6.4.4.1 A udio Suppor t Registers F3 Index 10h, Base Address Register 0 (F3BAR0), p oints to the base address of where the registers for audio sup- por t are located. T able 6-38 giv es th e bit f or mats of the memor y mapped audio configuration reg[...]

AMD Geode™ SC3200 Processor Data Book 263 Core Logic Module - Audio Registers - Function 3 32581C 16 Codec Status V alid. (Rea d Only) Indicates if the status in bits [15:0] of this r egister is valid. This bi t is high during slots 3 to 11 of the AC97 frame (i.e ., for appro ximately 14.5 µs), for e very frame. 0: No . 1: Y es. 15:0 Codec Statu[...]

264 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Audio Registers - Function 3 32581C 4 Audio Bus Master 2 SMI Status. Indicates if an SMI was caused by an e vent occurring on Audio Bus Master 2. 0: No . 1: Y es. SMI generation is enabled when A udio Bus Maste r 2 is enabled (F3BAR0+Memory Offset 30h[0] = 1). An SMI is then generated [...]

AMD Geode™ SC3200 Processor Data Book 265 Core Logic Module - Audio Registers - Function 3 32581C 4 Audio Bus Master 2 SMI Status. Indicates if an SMI was caused by an e vent occurring on Audio Bus Master 2. 0: No . 1: Y es. SMI generation is enabled when A udio Bus Maste r 2 is enabl ed (F3BAR0+Memory Offset 30h[0] = 1). An SMI is then gen - era[...]

266 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Audio Registers - Function 3 32581C 12 DMA T rap SMI Status. (Read to Clear) Indicates if an SMI was caused by a trapped I/O access to the DMA I/O T rap. 0: No . 1: Y es. (See the note included in the general descr iption of this register abov e.) This is the third lev el of SMI status[...]

AMD Geode™ SC3200 Processor Data Book 267 Core Logic Module - Audio Registers - Function 3 32581C 5 Low MPU I/O T rap. If this bit is enabled and an access occurs at I/O Port 300h-301h, an SMI is gene rated. 0: Disab le. 1: Enab le. T op le vel SMI status is repor ted at F1BAR0+I/O Offset 00h/02h[1]. Second lev el SMI status is repor ted at F3BAR[...]

268 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Audio Registers - Function 3 32581C 7 IRQ7 Intern al. Configures IRQ7 for internal (so ftware) or e xternal (hardware) use. 0: Exter nal. 1: Internal. 6 Reserved. Must be set to 0. 5 IRQ5 Intern al. Configures IRQ5 for internal (so ftware) or e xternal (hardware) use. 0: Exter nal. 1: [...]

AMD Geode™ SC3200 Processor Data Book 269 Core Logic Module - Audio Registers - Function 3 32581C 20 Mask Internal IRQ4. (Write Only) 0: Disab le. 1: Enab le. 19 Mask Internal IRQ3. (Write Only) 0: Disab le. 1: Enab le. 18 Reserved. (Write Only) Must be set to 0. 17 Mask Internal IRQ1. (Write Only) 0: Disab le. 1: Enab le. 16 Reserved. (Write Onl[...]

270 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Audio Registers - Function 3 32581C 1 Assert Masked Internal IRQ1. 0: Disab le. 1: Enab le. 0 Reserved. Must be set to 0. Offset 20h A udio Bus Master 0 Command Re gister (R/W) Re set V alue: 00h Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4. 7:4 R[...]

AMD Geode™ SC3200 Processor Data Book 271 Core Logic Module - Audio Registers - Function 3 32581C Offset 28h A udio Bus Master 1 Command Re gister (R/W) Re set V alue: 00h Audio Bus Master 1: Input from codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 7:4 Reserved. Must be set to 0. Must retur n 0 on reads. 3 Read or Write Control. Set the [...]

272 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Audio Registers - Function 3 32581C Offset 30h A udio Bus Master 2 Command Re gister (R/W) Re set V alue: 00h Audio Bus Master 2: Output to codec; 16-Bit; Slot 5. 7:4 Reserved. Must be set to 0. Must retur n 0 on reads. 3 Read or Write Control. Sets the transf er direction of Audio Bus[...]

AMD Geode™ SC3200 Processor Data Book 273 Core Logic Module - Audio Registers - Function 3 32581C Offset 38h A udio Bus Master 3 Command Re gister (R/W) Re set V alue: 00h Audio Bus Master 3: Input from codec; 16-Bit; Slot 5. 7:4 Reserved. Must be set to 0. Must retur n 0 on reads. 3 Read or Write Control. Sets the transf er direction of Audio Bu[...]

274 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Audio Registers - Function 3 32581C Offset 40h A udio Bus Master 4 Command Re gister (R/W) Re set V alue: 00h Audio Bus Master 4: Output to codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memor y Offset 08h[19] selects slot). 7:4 Reserved. Must be set to 0. Must retur n 0 on reads. 3 Read or Write[...]

AMD Geode™ SC3200 Processor Data Book 275 Core Logic Module - Audio Registers - Function 3 32581C Offset 48h A udio Bus Master 5 Command Re gister (R/W) Re set V alue: 00h Audio Bus Master 5: Input from codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[20] sele cts slot). 7:4 Reserved. Must be set to 0. Must retur n 0 on reads. 3 Read or Writ[...]

276 AMD Geode™ SC3200 Processor Data Book Core Logic Module - X-Bus Expansi on Interface - Function 5 32581C 6.4.5 X-Bus Expansion Interface - Function 5 The register space design ated as Function 5 (F5) is used to configure the PCI por t ion of suppor t hardware for accessing the X-Bus Expansion suppor t registers. The bit f or mats f or the PCI[...]

AMD Geode™ SC3200 Processor Data Book 277 Core Logic Module - X-Bus Expansion Interface - Fu nction 5 32581C Index 1Ch-1Fh Base Address Register 3 - F5BAR3 (R/W) Reset V alue: 00000000h Reserved. Reser ved f or possible future use by the Core Logic module. Configuration of this register is programmed th rough the F5BAR3 Mask Register (F5 Index 4C[...]

278 AMD Geode™ SC3200 Processor Data Book Core Logic Module - X-Bus Expansi on Interface - Function 5 32581C Index 44h-47h F5B AR1 Mask Address Regis ter (R/W) Reset V alue: 00000000h T o use F5BAR1, the mask register should be programmed first. The mask register def ines the size of F5BAR1 and whether the accessed offset registers are memor y or[...]

AMD Geode™ SC3200 Processor Data Book 279 Core Logic Module - X-Bus Expansion Interface - Fu nction 5 32581C Index 64h-67h Scratchpad: Usually used f o r Co nfiguration Block Address (R/W) Reset V alue: 00000000h BIOS writes a value, of t he Configuration Bloc k Address. Index 68h-FFh Reserved T able 6-39. F5: PCI Header Registers for X-Bus Expan[...]

280 AMD Geode™ SC3200 Processor Data Book Core Logic Module - X-Bus Expansi on Interface - Function 5 32581C 6.4.5.1 X-Bus Expansio n Suppor t Registers F5 Index 10h, Base Address Register 0 (F5BAR0) set the base address that allows PCI access to addi tional I/O Con- trol suppor t registers. T able 6-40 shows the suppor t regis- ters accessed th [...]

AMD Geode™ SC3200 Processor Data Book 281 Core Logic Module - X-Bus Expansion Interface - Fu nction 5 32581C Offset 04h-07h I/O Control Regi ster 2 (R/W) Reset V alue: 00000002h 31:2 Reserved. Write as read. 1 Video Processor Access Enable. Allows access to video processor using F4BAR0. 0: Disab le. 1: Enable. (Def ault) Note: This bit is readabl[...]

282 AMD Geode™ SC3200 Processor Data Book Core Logic Module - USB Con troller Registers - PCIUSB 32581C 6.4.6 USB Controller Registers - PCIUSB The registers designated as PCIUSB are 32-bit registers decoded from the PCI address bits [7 :2] and C/BE[3:0]#, when IDSEL is high, AD[10:8] select the app ropriate func- tion, and AD[1:0] are 00. The PC[...]

AMD Geode™ SC3200 Processor Data Book 283 Core Logic Module - USB Controller Registers - PCIUSB 32581C Index 06h-07h Status Register (R/W) R eset V alue: 0280h The PCI specification defines this register to record status in f ormation for PCI rela ted ev ents. This is a read/write register . Howe ver , writes can only reset bits. A bit is reset w[...]

284 AMD Geode™ SC3200 Processor Data Book Core Logic Module - USB Con troller Registers - PCIUSB 32581C Index 14h-2Bh Reserved Reset V a lue: 00h Index 2Ch-2Dh Subsystem V en dor ID (RO) Reset V alue: 0E11h Index 2Eh-2Fh Subsystem ID (RO) Reset V alue: A0F8h Index 30h-3Bh Reserved Reset V a lue: 00h Index 3Ch Interrupt Line Register (R/W) Reset V[...]

AMD Geode™ SC3200 Processor Data Book 285 Core Logic Module - USB Controller Registers - PCIUSB 32581C T able 6-42. USB_B AR+Memory Offset: USB Co ntroller Regi sters Bit Description Offset 00h-03h HcRevision Register (R O) Reset V alue = 00000110h 31:8 Reserved. Read/Wr ite 0s. 7:0 Revision (Read Only). Indicates the Open HCI Specification revis[...]

286 AMD Geode™ SC3200 Processor Data Book Core Logic Module - USB Con troller Registers - PCIUSB 32581C 6 RootHubStatusChang e. This bit is set when th e content of HcRhStatus or the content of any HcRhP or tStatus register has changed. 5 FrameNumberOverflow . Set w hen bit 15 of F rameNumber changes value. 4 UnrecoverableErr or (Read Only). This[...]

AMD Geode™ SC3200 Processor Data Book 287 Core Logic Module - USB Controller Registers - PCIUSB 32581C 6 RootHubStatusChang eEnable. 0: Ignore. 1: Disable interrupt generation due to Root Hub Status Change. 5 FrameNumberOverflowEnable. 0: Ignore. 1: Disable interrupt generation due to Fr ame Numbe r Ov erflow . 4 UnrecoverableErr orEnable . This [...]

288 AMD Geode™ SC3200 Processor Data Book Core Logic Module - USB Con troller Registers - PCIUSB 32581C Offset 34h-37h HcFmInterval Register (R/W) Reset V alue = 00002EDFh 31 FrameIntervalT oggle (Read On ly). This bit is toggled by HCD when it loads a new v alue into F rameInter val. 30:16 FSLargestDataP acket (Read Only). This field specifies a[...]

AMD Geode™ SC3200 Processor Data Book 289 Core Logic Module - USB Controller Registers - PCIUSB 32581C 7:0 NumberDownstreamP or ts (Read Only). USB suppor ts three downstream por ts. Note: This register is only reset by a pow er-on rese t (PCIRST#). It is wr itten during system initialization to configure the Root Hub . These bit should not be wr[...]

290 AMD Geode™ SC3200 Processor Data Book Core Logic Module - USB Con troller Registers - PCIUSB 32581C Offset 54h-57h HcRhPortStatus[1] Register (R/W) Reset V alue = 0000000 0h 31:21 Reserved. Read/Wr ite 0s. 20 P or tResetStatusChang e. This bit indicates that the por t reset signa l has completed. 0: P or t reset is not complete. 1: P or t res[...]

AMD Geode™ SC3200 Processor Data Book 291 Core Logic Module - USB Controller Registers - PCIUSB 32581C 1 Read: PortEnableStatus. 0: P or t disab led . 1: P or t enabled. Write: SetP ortEnable. Writing a 1 sets PortEnableStatus. Writing a 0 has no effect. 0 Read: CurrentConnectStatu s. 0: No device connected. 1: Device connected. If DeviceRemo vea[...]

292 AMD Geode™ SC3200 Processor Data Book Core Logic Module - USB Con troller Registers - PCIUSB 32581C 3 Read: Po rtOverCurrentInd icator . This bit reflects the state of the OVRCUR pi n dedicated to this por t. This field is only valid if NoOverCurrentProtection is cleared and Ov erCurre ntProtectionMode is set. 0: No over-current condition. 1:[...]

AMD Geode™ SC3200 Processor Data Book 293 Core Logic Module - USB Controller Registers - PCIUSB 32581C 8 Read: Po rtPowerS tatu s. This bit reflects the power state of the port regardless of the power s witching mode. 0: P or t po wer is off. 1: P or t po wer is on. If NoP owerSwitching is set, this bit is alwa ys read as 1. Write: SetP ortP ower[...]

294 AMD Geode™ SC3200 Processor Data Book Core Logic Module - USB Con troller Registers - PCIUSB 32581C 1 EmulationInterrupt (Read Only). This bit is a static decode of the emulation interr upt condition. 0 EmulationEnable. When set to 1 the HC is enabled for legacy emul ation and will decode accesses to I/O registers 60h and 64h and generate IRQ[...]

AMD Geode™ SC3200 Processor Data Book 295 Core Logic Module - ISA Legacy Register Space 32581C 6.4.7 ISA Legacy Register Space The ISA Legacy registers reside in the ISA I/O address space in the address range from 000h to FFFh and are accessed through typical input/ output instructions (i.e., CPU direct R/W) with the designated I/O por t address [...]

296 AMD Geode™ SC3200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32581C 2 Channel 2 T erminal Co unt. Indicates if TC was reached. 0: No . 1: Y es. 1 Channel 1 T erminal Co unt. Indicates if TC was reached. 0: No . 1: Y es. 0 Channel 0 T erminal Co unt. Indicates if TC was reached. 0: No . 1: Y es. Write DMA Comm and Regis[...]

AMD Geode™ SC3200 Processor Data Book 297 Core Logic Module - ISA Legacy Register Space 32581C I/O Port 00Bh DMA Channel Mode Register , Channels 3:0 (WO) 7:6 T r ansfer Mode. 00: Demand. 01: Single. 10: Bloc k. 11: Cascade. 5 Address Direction. 0: Increment. 1: Decrement. 4 Auto-initialize. 0: Disab le. 1: Enab le. 3:2 T r ansfer T ype. 00: V er[...]

298 AMD Geode™ SC3200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32581C I/O Port 0D0h (R/W) Read DMA Status Register , Channels 7:4 Note: Channels 5, 6, and 7 are not suppor ted. 7 Channel 7 Request. Indicates if a request is pending. 0: No . 1: Y es. 6 Channel 6 Request. Indicates if a request is pending. 0: No . 1: Y es.[...]

AMD Geode™ SC3200 Processor Data Book 299 Core Logic Module - ISA Legacy Register Space 32581C I/O Port 0D2h Software DMA Request Register , Channels 7:4 (W) Note: Channels 5, 6, and 7 are not suppor ted. 7:3 Reserved. Must be set to 0. 2 Request T y pe. 0: Reset. 1: Set. 1:0 Channel Number Request Select. 00: Illegal. 01: Channel 5. 10: Channel [...]

300 AMD Geode™ SC3200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32581C I/O Port 0DEh DMA Write Mask Register Command, Channels 7:4 (W) Note: Channels 5, 6, and 7 are not suppor ted. T able 6-43. DMA Chan nel Control Registers (Continued) Bit Description T able 6-44. DMA Pa g e Register s Bit Description I/O Port 081h DMA [...]

AMD Geode™ SC3200 Processor Data Book 301 Core Logic Module - ISA Legacy Register Space 32581C T able 6-45. Programmable Inter val Timer Regist ers Bit Description I/O Port 040h Write PIT Timer 0 Counter 7:0 Counte r V alue. Read PIT Timer 0 Statu s 7 Counter Ou tput. State of counter output signal. 6 Counter Lo aded. Indicates if the last count [...]

302 AMD Geode™ SC3200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32581C I/O Port 042h Write PIT Timer 2 Counter (Speaker) 7:0 Counte r V alue. Read PIT Timer 2 Status (Spea ker) 7 Counter Ou tput. State of counter output signal. 6 Counter Lo aded. Indicates if the last count written is loaded. 0: Y es. 1: No . 5:4 Current [...]

AMD Geode™ SC3200 Processor Data Book 303 Core Logic Module - ISA Legacy Register Space 32581C T able 6-46. Programmab le Interrupt Contr oller Registers Bit Description I/O Po rt 020h / 0A0h Master / Slave PIC ICW1 (WO) 7:5 Reserved. Must be set to 0. 4 Reserved. Must be set to 1. 3 Tr i g g e r M o d e . 0: Edge . 1: Le vel. 2 V ector Address I[...]

304 AMD Geode™ SC3200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32581C 2 IRQ2 / IRQ10 Mask. 0: Not Masked. 1: Mask. 1 IRQ1 / IRQ9 Mask. 0: Not Masked. 1: Mask. 0 IRQ0 / IRQ8 Mask. 0: Not Masked. 1: Mask. I/O Port 020h / 0A0h Master / Slave PIC OCW2 (WO) 7:5 Rotate/EOI Codes. 000: Clear rotate in Auto EOI mode 100: Set ro [...]

AMD Geode™ SC3200 Processor Data Book 305 Core Logic Module - ISA Legacy Register Space 32581C 3 IRQ3 / IRQ11 Pending. 0: Y es. 1: No . 2 IRQ2 / IRQ10 Pending. 0: Y es. 1: No . 1 IRQ1 / IRQ9 Pending. 0: Y es. 1: No . 0 IRQ0 / IRQ8 Pending. 0: Y es. 1: No . Interrupt Service Reg ister 7 IRQ7 / IRQ15 In-Service . 0: No . 1: Y es. 6 IRQ6 / IRQ14 In-[...]

306 AMD Geode™ SC3200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32581C T able 6-47. Keyboa rd Controll er Register s Bit Description I/O Port 060h External Keyboar d Controller Data Register (R/W) Keyboar d C ontroller Data Register . All accesses to this por t are passed to the ISA bus. If the f ast keyboard gate A20 and[...]

AMD Geode™ SC3200 Processor Data Book 307 Core Logic Module - ISA Legacy Register Space 32581C T able 6-48. Real-Time Cloc k Registers Bit Description I/O Po rt 070h RTC Address Register (WO) This register is shadowed within the Core Logic module and is read through the RTC Shadow Register (F0 Inde x BBh). 7 NMI Mask . 0: Enab le. 1: Mask. 6:0 RT[...]

308 AMD Geode™ SC3200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32581C 3 IRQ3 Edge or L evel Sensitive Select. Selects PIC IRQ3 sensitivity configuration. 0: Edge . 1: Le vel. 2:0 Reserved . Must be set to 0. I/O Port 4D1h Interrupt Edg e/Level Select Register 2 (R/W) Re set V alue: 00h Notes: 1. If ICW1 - bit 3 in the PI[...]

AMD Geode™ SC3200 Processor Data Book 309 7 Video Processor Module 32581C 7.0 Video Processor Module The Video Processor module co ntains a high performance video back-end accelerator , a video/graphics Mixer/ Blender , a Video Input Port (VIP), suppor ting a TFT inter- f ace. The bac k-end accelerator fu nctions include hori zontal and vertical [...]

310 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C 7.1 Module Ar chitecture Figure 7-1 shows a top-lev el block diagram of the Video Processor . For inf or mation abou t the relationship between the Video Processor an d the other modules of th e SC3200, see Section 2.2 on page 22. The Video Processor module includes the follo[...]

AMD Geode™ SC3200 Processor Data Book 311 Video Processor Module 32581C 7.2 Functional Description T o understand why the Video Processor functions as it does, it is first impor tant to understand the difference between video and graphics. Video is pictures in motion, which usua lly star ts out in an encod ed f or mat (i.e. , MPEG2, A VI, MPEG4) [...]

312 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C Figure 7-2. NTSC 525 Lines, 60 Hz, Odd Field Figure 7-3. NTSC 525 Lines, 60 Hz, Even Field V er t ical Retrace - Logical Lines 4-9 — Scan Lines 4-9 V er t ical Retrace - Logica l Lines 10-21 — Scan lines 10-21 V er tical Retrace - Logical Lines 22, 23 — Scan lines 22, 2[...]

AMD Geode™ SC3200 Processor Data Book 313 Video Processor Module 32581C 7.2.1 Video Inp ut P or t (VIP) The VIP block is designed to interface the SC3200 with e xterna l video processors (e.g., Philips PNX1300 or Sigma Designs EM8400) or external TV decode rs (e.g., Philips SAA7114). It inputs CCIR-656 Vid eo and raw VBI data sourced by those de [...]

314 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C The GenLock control hardware is used to synch ronize the video input’ s fiel d with the GX1 module’ s graphics frame . The graphics data is alwa ys se nt full frame. F or the Gen- Lock function to perf or m correctly , the GX1 module’s Dis- play Controller must be progr[...]

AMD Geode™ SC3200 Processor Data Book 315 Video Processor Module 32581C Figure 7-5. Capture Video Mode Bob Example Using On e Video Frame Buffer We av e The Wea ve method assembles the odd field and e ven field together to form the complete frame, and then renders the “wea ved” frames to the displa y de vice. The Vide o data is conv er ted fr[...]

316 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C 3) Field Interrupt. When the field interr upt occurs on the completion of a n odd field, the interr upt must program the Video Data Odd Base Address with the other buff er’s address. The odd field will pin g-pong between the two buff ers. When the interr upt is due to the c[...]

AMD Geode™ SC3200 Processor Data Book 317 Video Processor Module 32581C 7.2.2 Video Block The Video block rece ives video data from the VIP block or the GX1 module’ s video frame buffer . Th e video data is for- matted and scaled and then sent to the Mixer/Blender . The video data also changes clock domains while in the Video bloc k. It is clo [...]

318 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C 7.2.2.2 Horizontal Downscal er with 4 -T ap Fi ltering The Video Processor implements up to 8:1 hor izontal downscaling with 4-tap filter ing for horizontal inter polati on. Filter ing is performed on vi deo data input to the Video Pro- cessor . This da ta is fed to the filte[...]

AMD Geode™ SC3200 Processor Data Book 319 Video Processor Module 32581C 7.2.2.3 Line Buffer s After the data has been option ally horizontally downscaled the video data is stored in a 3- line buff er . Each li ne is 360 D WORDs, which means a line width of up to 720 pixels can be stored. This buffer supports two functions. First, the clock domain[...]

320 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C 7.2.3 Mixer/Blende r Block The Mixer/Blender bloc k of the Video Pro cessor module perf orm s all the necessar y functions to proper ly mix/blend the video data and the graphics data. These functions include Color Space Conv ersion (CSC), optional Gamma correction, color/chro[...]

AMD Geode™ SC3200 Processor Data Book 321 Video Processor Module 32581C 7.2.3.1 YUV to RGB CSC in Video Data Path This CSC must be enabled if the video data is in the YUV color space. The CSC_FOR_ VIDEO bit, F4BAR0+Memor y Offset 4Ch[10], controls this CSC . YUV video data is passed through this CSC to obtain 24-bit RGB data using th e f o llowin[...]

322 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C 7.2.3.4 Color/Chroma K ey and Mixer/Blender The Mixer/Blender takes each pix el of the graphics and video data streams and mi x es o r blends them together . Mixing is simply choosing the graphics pix el or the video pixel. Blending tak es a percenta ge of a graphics pix el ([...]

AMD Geode™ SC3200 Processor Data Book 323 Video Processor Module 32581C Mixing/Blendin g Operation T able 7-2 on page 323 shows the tr uth table used to create th e flow diagram, Figure 7-12 on page 3 24, that the Mixer/ Blender logic uses to deter mine each pixels disposition. T able 7-2. T ruth T able for Alpha Blending COLOR_ CHROMA_SEL 1 1. C[...]

324 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C Figure 7-12. Color Ke y and Alpha Blending Logic Color register enabled f or this window “Graphics 2 inside Video” is enabled Cursor color ke y matches graphics value Pix el outside the video window No Ye s Use selected cur- sor color for pixel No No Pixel value 3 matches[...]

AMD Geode™ SC3200 Processor Data Book 325 Video Processor Module 32581C 7.2.4 TFT I nterface The TFT interf ace can be programmed to one of two sets of balls: IDE balls or Par allel P or t balls. PMR[23] of the Gen- eral Co nfigur ation registers prog ram where the TFT inte r- f ace e xists (see T able 4-2 on page 70). Note: If the TFT interface [...]

326 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C 7.2.5 Integrated PL L The integrated PLL can gen erate frequencies up to 135 MHz from a single 27 MH z source. The clock frequency is programmable using two registers . Figure 7-14 shows the bloc k di agram of the Video Processor integ rated PLL. F REF is 27 MHz, generated b [...]

AMD Geode™ SC3200 Processor Data Book 327 Video Processor Module - Register Summary 32581C 7.3 Register Descriptions The register space for accessing and configur ing the Video Processor is located in the Co re Logic Chipset Register Space (F0-F5). The Chipset Register Space is accesse d via the PCI interf ace using the PCI T ype One Configuratio[...]

328 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Register Summary 32581C 28h-2Bh 32 R/W Miscellaneous Register 00001400h Page 336 2Ch-2Fh 32 R/W PLL2 Clock Select Register 00000000h Page 336 30h-33h 32 --- Reser ved 00000000h P age 336 34h-37h 32 RO Reser ved 00000000h P age 336 38h-3Bh 32 RO Reserved 00000000h Page 336 3Ch-3Fh [...]

AMD Geode™ SC3200 Processor Data Book 329 Video Processor Module - Register Summary 32581C T able 7-5. F4BAR2: VIP Support Registers Summary F4BAR2+ Memory Offset Width (Bits) T ype Name Reset Va l u e Reference (T able 7-8) 00h-03h 32 R/W Video Interface P or t Configuration Register 00000000h Page 345 04h-07h 32 R/W Video Interface Control Regi[...]

330 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C 7.3.2 Video Processo r Register s - Function 4 The register space design ated as Function 4 (F4) is used to configure the PCI por t ion of suppor t hardware for accessing the Video Processor suppor t registers, including VIP (sepa rate[...]

AMD Geode™ SC3200 Processor Data Book 331 Video Processor Module - Video Processor Registers - Function 4 32581C Index 3Dh Interrupt Pin Register (R/W) Reset V alue: 03h This register selects which interrupt pin the device uses. VIP uses INTC# after reset. INT A#, INTB# or INTD# can be selected by writing 1, 2 or 4, respectively . Index 3Eh-FFh R[...]

332 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C 7.3.2.1 Video Proc essor Support Registe rs - F4B AR0 F4 Index 10h, Base Address Re gister 0 (F4BAR0) sets th e base address that allows PCI access to the Video Proces- sor suppor t registers, not including VIP . A separate base addres[...]

AMD Geode™ SC3200 Processor Data Book 333 Video Processor Module - Video Processor Registers - Function 4 32581C 0 VID_EN (Video Enable). Enables video acceleration hardware . 0: Disable (reset) video module. 1: Enab le. Offset 04h-07h Display Co nfiguration Register (R/W) Reset V alue: x0000000h General configuration register f or display contro[...]

334 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C Offset 08h-0Bh Video X P osition Register (R/W) Reset V alue: 00000000h Provides the windo w X position. Th is register is programmed relativ e to CRT horiz ontal sync input (not ph ysical screen position ). Note: H_T OT AL and H_SYNC_[...]

AMD Geode™ SC3200 Processor Data Book 335 Video Processor Module - Video Processor Registers - Function 4 32581C Offset 14h-17h Video Color Key Re gister (R/W) Reset V alue: 00000000h Provides the video color k ey . The color key can be used to al low irregular shaped o verla ys of graphics onto video, or video ont o gr aph- ics, within a scaled [...]

336 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C Offset 28h-2Bh Miscellaneous Register (R /W) Reset V alue: 00001400h Configuration and control register for miscell aneous characteristics of the Video Processor. 31:13 Reserved. 12 PLL2_PWR_EN (PLL2 Po wer-Do wn Enable). 0: P ower -do[...]

AMD Geode™ SC3200 Processor Data Book 337 Video Processor Module - Video Processor Registers - Function 4 32581C Offset 3Ch-3Fh Video Downscaler Cont r o l Register (R/W) Reset V alue: 00000000h Controls the characteristics of the inte grated video do w nscaler . 31:7 Reserved 6 DTS (Downscale T ype Select). 0: T ype A (Downscale formula is 1/m+1[...]

338 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C Offset 4Ch-4Fh Video De-Interlacing and Al ph a Control Register (R/W) Reset V alue: 00060000h 31:22 Reserved. 21:20 ALPHA3_WIN_PRIORITY (Alpha Wind ow 3 Priority). Determines the priority of Alph a Window 3. A higher number indi- cate[...]

AMD Geode™ SC3200 Processor Data Book 339 Video Processor Module - Video Processor Registers - Function 4 32581C 8 GFX_INS_VIDEO (Graphics Inside Video). This bit works in conjunction with bit COLOR_CHROMA_SEL (F4BAR0+Mem- or y Offset 4Ch[20]). COLOR_CHROMA _SEL selects whether the gr aphics is used f or color ke ying or the video data stream is [...]

340 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C Offset 60h-63h Alpha Window 1 X P osi tion Register (R/W) Reset V alue: 00000000h Note: H_T OT AL and H_SYNC_END are values progr ammed in the GX1 module’s Displa y Cont roller Timing registers (GX_BASE+Memory Offset 8330h[26:19] and[...]

AMD Geode™ SC3200 Processor Data Book 341 Video Processor Module - Video Processor Registers - Function 4 32581C Offset 70h-73h Alpha Window 2 X P osi tion Register (R/W) Reset V alue: 00000000h Note: H_T OT AL and H_SYNC_END are values progr ammed in the GX1 module’s Displa y Cont roller Timing registers (GX_BASE+Memory Offset 8330h[26:19] and[...]

342 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C Offset 80h-83h Alpha Window 3 X P osi tion Register (R/W) Reset V alue: 00000000h Note: H_T OT AL and H_SYNC_END are values progr ammed in the GX1 module’s Displa y Cont roller Timing registers (GX_BASE+Memory Offset 8330h[26:19] and[...]

AMD Geode™ SC3200 Processor Data Book 343 Video Processor Module - Video Processor Registers - Function 4 32581C Offset 90h-93h Video Request Register (R/W) Reset V al ue: 001B0017h 31:28 Reserved. Set to 0. 27:16 VIDEO_X_REQ (Video Horizontal Request). Determines the hor izontal (pixel) lo cation at which to start requesting video data out of th[...]

344 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C Offset 420h-423h GenLock Regi ster (R/W) Reset V alue: 00000000h 31:24 Reserved. Must be set to 0. 23 ODD_T O (Odd Fie ld Time Ou t). Indicates CGENTO 0 (F4BAR0+Memor y Offset 43Ch[15:0]) has expired. This bit can be reset by writing 1[...]

AMD Geode™ SC3200 Processor Data Book 345 Video Processor Module - Video Processor Registers - Function 4 32581C 7.3.2.2 VIP Support Registers - F4BAR2 F4 Inde x 18h, Base Address Register 2 (F4BAR2) poin ts to the base address of where the VIP Configuration registers are located. T able 7-8 shows the memor y mapped VIP sup- por t registers acces[...]

346 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C 10 Auto-Flip. Video port operation mo de. 0: The video por t automatically detects the e ven and odd fi elds based on the VP_HREF and VP_VSYNC_IN signals or the CCIR656 control codes. 1: The even/odd field detect logic is disab led and[...]

AMD Geode™ SC3200 Processor Data Book 347 Video Processor Module - Video Processor Registers - Function 4 32581C 8 Video Data Captur e Active. (Read Only) 0: Video data is not being stored to memor y . 1: Video data is now being stored to memor y . 7:1 Reserved. (Read Only) 0 Run Status. (Read Only) 0: Video por t capture is not active. 1: Video [...]

348 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C Offset 40h-43h VBI Data Odd Base Register (R/W) Reset V alue: 00000000h This register specifies the base address in graphics memor y where VBI data for odd fields are stored. Changes to this register take effect at the beginning of the[...]

AMD Geode™ SC3200 Processor Data Book 349 8 Debu gging and Monitoring 32581C 8.0 Deb ugging and Monitor ing 8.1 T estability (JT A G) The T est Access P or t (T AP) allows board lev el intercon nec- tion verification and chip production tests. An IEEE- 1149.1a compliant test interface, T AP suppor ts all IEEE mandator y instr uctions as well as s[...]

350 AMD Geode™ SC3200 Processor Data Book Debu gging and Monitoring 32581C[...]

AMD Geode™ SC3200 Processor Data Book 351 9 Electrical Specifications 32581C 9.0 Electr ical Specifications This chapter provides inf or mation abo ut: • General electrical specificatio ns • DC characteristics • A C character istics All voltage v alues in this chap ter are with respect to V SS unless otherwise noted . 9.1 General Specificat[...]

352 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.1.4 Operating Conditions T able 9-3 lists the various power supplies of the SC3200 and provides the device operating conditions . Notes: 1) All power sources except V BA T must be connected, even if the function is not used. 2) V SB , and V SBL must be on if an y other v[...]

AMD Geode™ SC3200 Processor Data Book 353 Electrical Specifications 32581C T able 9-4 indicates whic h power r ails are used for each signal of the SC3 200 e xter nal interface. P ow er planes not listed in this table are interna l, and are not related to signals of the e xte rnal interface. 9.1.5 DC Current DC current is not a simple me asuremen[...]

354 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.1.5.3 Definition of Sy stem Conditions f or Measuring On P ara meters The SC3200’ s current is highly depende nt on two func- tional characteristics, DCLK (DOT clock) and SDRAM fre- quency . T able 9-5 shows how these f actors are co ntrolled when measur ing the typica[...]

AMD Geode™ SC3200 Processor Data Book 355 Electrical Specifications 32581C 9.1.6 Ball Capacitance and Inductance T able 9-8 gives ball capacitance and inductance values . T able 9-7. DC Characteristics f or Active Idle, Sleep, a nd Off States Symbol ParameterNote 1 Min T yp Max Unit Comments I CC3IDLE f CL K = 233 MHz, I/O Current @ V IO = 3.3V ([...]

356 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.1.7 Pull-Up and Pull- Down Resistors The follo wing table lists input balls that are internal ly con- nected to a pull-up (PU) or pull-d own (PD) resistor . If these balls are not used, they do not require connection to an e xternal PU or PD resistor . Note: The resistor[...]

AMD Geode™ SC3200 Processor Data Book 357 Electrical Specifications 32581C 9.2 DC Characteristics T able 9-10 descri bes the signal buffer types of the SC3200. (See T able 3-2 "BGD432 Ball Assi gnment - Sor ted by Ball Number" on page 29 and T able 3-2 "BGU481 Ball Assign- ment - Sor ted by Ball Number" on page 29) for each si[...]

358 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.2.1 IN AB DC Characteristics 9.2.2 IN BTN DC Characteristics 9.2.3 IN PCI DC Characteristics Note that the b uffer type f or PCICLK (ball A7) is IN T - not IN PCI . Symbol P a rameter Min Max Unit Comments V IH Input Hi gh V oltage 1.4 V V IL Input Low V oltage -0.5 ( No[...]

AMD Geode™ SC3200 Processor Data Book 359 Electrical Specifications 32581C 9.2.4 IN STRP DC Characteristics 9.2.5 IN T DC Characteristics 9.2.6 IN TS DC Characteristics 9.2.7 IN TS1 DC Characteristics Symbol P a rameter Min Max Unit Comments V IH Input Hi gh V oltage 0.6V IO V IO +0.3 (Note 1) V V IL Input Low V oltage 0.3V IO V I IL Input Leakag[...]

360 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.2.8 IN USB DC Characteristics Figure 9-1. Differential Input Sensitiv ity f or Common Mode Range 9.2.9 O AC9 7 DC Characteristics 9.2.10 OD n DC Characteristics Symbol P a rameter Min Max Unit Comments V IH Input Hi gh V oltage 2.0 V IO +0.3 (Note 1) V V IL Input Low V o[...]

AMD Geode™ SC3200 Processor Data Book 361 Electrical Specifications 32581C 9.2.11 OD PCI DC Ch aracteristic s 9.2.12 O p/n DC Characterist ics 9.2.13 O PCI DC Characteristics 9.2.14 O USB DC Characteristics 9.2.15 TS p/n DC Characteristic s 9.2.15.1 Exceptions 1) I OH is valid f or a GPIO pin only when it is not configured as op en-drain. 2) Sign[...]

362 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3 A C Characteristics The tables in this section list the following A C character is- tics: • Output delays • Input setup requirements • Input hold requirements • Output float del a ys • P ower-up sequencing requirements The default le vels for measurement of t[...]

AMD Geode™ SC3200 Processor Data Book 363 Electrical Specifications 32581C 9.3.1 Memor y Controller Int erface The minimum input setup and hold ti mes described i n Figure 9- 3 (legend C an d D) define the smallest acce ptable sampling window during which a synchronou s input signal must be stable to ensure correct operation. Figure 9-3. Memory C[...]

364 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C T able 9-12. Memory C ontroller Timing Parameters Symbol P a rameter Min Max Unit Comments t 1 Control output valid from SDCLK[3:0] -3.0 + (x * y) 0.1 + (x * y) ns Note 1, Note 2 t 2 MA[12:0], BA[1.0] output v alid from SDCLK[3:0] -3.2 + (x * y) 0.1 + (x * y) ns Note 2 t 3[...]

AMD Geode™ SC3200 Processor Data Book 365 Electrical Specifications 32581C Figure 9-4. Memory Controller Output V alid Timing Diagram Figure 9-5. Read Data In Setup and Hold Timing Diagram SDCLK[3:0] Control Output, MA[12:0] BA[1:0], MD[63:0] t 1 , t 2 , t 3 t 6 t 7 t 7 V REF V OH D V OL D V REF t 10 t 11 SDCLK_IN Data V a lid MD[63:0] Read Data [...]

366 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.2 Video Port Figure 9-6. Video Input P or t Timing Diagram T able 9-13. Video Input P or t Timing Pa rameters Symbol P aramete r Min Max U nit Comments t VP_C VPCKIN cycle time 18 ns t VP_S Video P or t input setup time before VPCKIN ri sing edge 6n s t VP_H Video P or[...]

AMD Geode™ SC3200 Processor Data Book 367 Electrical Specifications 32581C 9.3.3 TFT I nterface Figure 9-7. TFT Timing Diagram T able 9-14. TFT Timing P arameters Symbol P aramete r Min Max U nit Comments t OV TFTD[17:0], TF TDE valid time after TFTDCK rising ed ge (multiple x ed on IDE) 08 n s t OV TFTD[17:0], TF TDE valid time after TFTDCK risi[...]

368 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.4 ACCESS.b us Interface The f ollowing tab les describe the timing f or the ACCESS .bus sig nals. Notes: 1) All ACCESS.b u s timing is not 100% tested. 2) In this table t CLK = 1/24MHz = 41.7 ns . T able 9-15. A CCESS.bus Input Timing P arameter s Symbol P arameter Min[...]

AMD Geode™ SC3200 Processor Data Book 369 Electrical Specifications 32581C Figure 9-8. A CB Signals: Rising Time and F alling Timing Diagram Figure 9-9. A CB Start and Stop Condition Timing Diagram t SD Afo AB1D/AB2D signal fall time 300 ns t SD Aro AB1D/AB2D signal r ise time 1 μ s t SD Aho AB1D/AB2D hold time 7 * t CLK - t SCLfo After AB1C/AB2[...]

370 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9 -10. A CB Star t Condit ion Timing Diagram Figure 9-11. ACB Data Bit Timing Dia gram t CSTRsi t DHCsi Star t Conditi on t CSTRhi AB1D AB1C t CSTRho t CSTRso t DHCso AB2D AB2C t SCLhigho t SCLlowo t SD Aho t SD Av o t SDAso AB1D AB1C t SDAsi t SCLlowi t SCLhighi t [...]

AMD Geode™ SC3200 Processor Data Book 371 Electrical Specifications 32581C 9.3.5 PCI Bus In terface The SC3200 is complia nt with PCI Bus Rev . 2.1 specifica- tions. Rele vant information from the PCI Bus specifications is provided below . All parameters in T a ble 9-17 are not 100% tested. The parameters in this table are further descr ibed in F[...]

372 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-13. V/I Curve s for PCI Output Signals Pull-Up Pull-Down T est P oint V IO 0.9 V IO DC Drive P oint AC Drive P oint 0.3 V IO 0.6 V IO 0.1 A C Drive P oint DC Drive P oint T est P oint V IO Equation A fo r V IO >V OUT >0.7 V IO I OL = (256/V IO )* V OUT *(V I[...]

AMD Geode™ SC3200 Processor Data Book 373 Electrical Specifications 32581C Figure 9-14. PCICLK Timing and Measurement P oints T able 9-18. P CI Clock P a rameters Symbol Parameter Min Max Unit Comments t CYC PCICLK cycle time 30 ns Note 1 t HIGH PCICLK high time 11 ns No te 2 t LO W PCICLK low time 11 ns No te 2 PCICLK sr PCICLK slew Rate 1 4 V/n[...]

374 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-15. Load Circuits for Ma ximum Time Measurements T able 9-19. PCI Timing Parameters Symbol Parameter Min Max U nit Comments t VA L PCICLK to signal valid delay (on the b us) 2 11 ns Note 1, Note 2 t VA L (ptp) PCICLK to sig nal valid dela y (GNT#) 2 9 ns Note 1, N[...]

AMD Geode™ SC3200 Processor Data Book 375 Electrical Specifications 32581C 9.3.5.1 Measurement and T est Conditions Figure 9 -16. Outpu t Timing Measur ement Cond itions T able 9-20. Measurement Condition P arameters Symbol V alue Unit Comments V TH 0.6 V IO V Note 1 V TL 0.2 V IO V Note 1 V TEST 0.4 V IO V V STEP (rising edge ) 0.285 V IO V V ST[...]

376 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-17. Input Timing Measurement Conditions Figure 9-18. PCI Reset Timing V TEST V TEST Input V alid t SU t H V TEST V MAX V TH V TL PCICLK Input V TH V TL ) ( 100 ms (typ) ) ( t RST t RST -CLK t RST -OFF TRI_ST A TE PCI Signals PCIRST# PCICLK PO WER POR# t FA I L V I[...]

AMD Geode™ SC3200 Processor Data Book 377 Electrical Specifications 32581C 9.3.6 Sub-ISA Int erface All output timing is guaranteed for 50 pF load, unle ss other- wise specified. The ISA Clock divisor (defined in F0 Index 50h[2:0] of the Core Logic module) is 011. T able 9-21. S ub-ISA Timing P ara meters Symbol Parameter Bus Width (Bits) T ype M[...]

378 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C t RD Y A2 IOCHRD Y valid after IOR#/MEMR#/ RD#/DOCR# /IOW#/M EMW#/WR#/ DOCW# F E 8 M, I/O 366 9-19 9-20 t IOCSA IOCS[1:0]#/ DOCS#/ROM CS# driv en active from A[23:0] v alid 8, 16 M, I/O 34 9-19 9-20 t IOCSH IOCS[1:0]#/DOCS#/ROMCS# valid hold after A[23:0] invalid 8, 16 M, [...]

AMD Geode™ SC3200 Processor Data Book 379 Electrical Specifications 32581C Figure 9-19. Sub-ISA Read Operation Timing Diagram t RDx t ARx Valid Valid Valid Data t RCUx t RA t RVDS t RDH t HZ A[23:0]/BHE# D[15:0] t RDYAx t RDYH MEMW#/DOCW# ROMCS#/DOCCS# IOW#/WR# IOCS[1:0]# (Read) t IOCSA t IOCSH t WDAR D[15:0] (Write) IOR#/RD#/TRDE# MEMR#/DOCR# IO[...]

380 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-20. Sub-ISA Write Opera tion Timing Diagram t WRx t AWx Valid Valid Valid Data t WCUx t WA t DH A[23:0]/BHE# TRDE# D[15:0] IOCHRDY t RDYAx t RDYH DOCCS#/ROMCS# t IOCSH IOCS[1:0]# t DF t DVx t IOCSA IO W#/WR# MEMW#/DOCW# IOR#/RD# MEMR#/DOCR# t WTR Note: x indicates[...]

AMD Geode™ SC3200 Processor Data Book 381 Electrical Specifications 32581C 9.3.7 LPC Interface Figure 9-21. LPC Output Timing Diagram Figure 9-22. LPC Input Timing Diagram T able 9-22. LPC and SERIRQ Timing Paramete rs Symbol P a rameter Min Max Unit Comments t VA L Ou tput V alid delay 0 17 ns After PCICLK ri sing edge t ON Float to Activ e dela[...]

382 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.8 IDE Interfa ce Figure 9-23. IDE Reset Timing Diagram T able 9-23. IDE Genera l Timing P arameters Symbol Parameter Min Max Unit Comments t IDE_F ALL IDE signals fall time (from 0.9V IO to 0.1V IO )5 n s C L = 40 pF t IDE_R ISE IDE signals rise time (from 0.1V IO to 0[...]

AMD Geode™ SC3200 Processor Data Book 383 Electrical Specifications 32581C T able 9-24. IDE Register T ransf er to/fr om Device Timing P arameters Symbol P arameter Mode Unit Comments 01235 t 0 Cycle time (min) 600 383 240 180 120 ns No te 1 t 1 Address v alid to IDE_IOR[0 :1]#/ IDE_IO W[0:1]# setup (mi n) 70 50 30 30 25 ns t 2 IDE_IOR[0:1]#/IDE_[...]

384 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-24. Register T ransf er to/fr om Device Timing Diagram ADDR valid 1 WRITE READ t 0 t 1 t 2 t 9 t 2i t 3 t 5 t 6z t 6 t A t 4 t C t RD t B t C IDE_IOR0# IDE_IOW0# IDE_IORD Y0 2,3 IDE_IORD Y0 2,4 IDE_IORD Y0 2,5 Notes: 1) De vice address consists of signals IDE_CS[0[...]

AMD Geode™ SC3200 Processor Data Book 385 Electrical Specifications 32581C T able 9-25. IDE PIO Data T ransfer to/ fr om Device Timing Parameters Symbol P arameter Mode Unit Comments 01234 t 0 Cycle time (min) 600 383 240 180 120 ns No te 1 t 1 Address v alid to IDE_IOR[0 :1]#/ IDE_IO W[0:1]# setup (mi n) 70 50 30 30 25 ns t 2 IDE_IOR[0:1]#/IDE_I[...]

386 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9- 25. PIO Data T ransfer to/from Device Timing Diagram ADDR valid 1 WRITE IDE_DATA[15:0] READ IDE_DATA[15:0] t 0 t 1 t 2 t 9 t 2i t 3 t 5 t 6z t 6 t A t 4 t C t RD t B t C IDE_IOR0# IDE_IOW0# IDE_IORD Y0 2,3 IDE_IORD Y0 2,4 IDE_IORD Y0 2,5 Notes: 1) De vice address[...]

AMD Geode™ SC3200 Processor Data Book 387 Electrical Specifications 32581C T able 9-26 . IDE Multiw ord DMA Data T ransfer Timing P arameters Symbol P arameter Mode Unit Comments 012 t 0 Cycle time (min) 480 15 0 120 ns Note 1 t D IDE_IOR[0:1]#/IDE_IOW[0:1]# (min) 215 80 70 ns t E IDE_IOR[0:1]# data a ccess (max) 150 60 50 ns t F IDE_IOR[0:1]# da[...]

388 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-26. Multiwor d DMA Data T ransfer Timing Diagram t M t N t L t j t K t D t I t E t Z t F t G t G t H t 0 IDE_CS[1:0]# IDE_DATA[15:0] IDE_DATA[15:0] IDE_DREQ0 IDE_DA CK0# IDE_IOR0# IDE_IOW0# Notes: 1) F or Multiword DMA transf ers, the Device ma y negate IDE_ DREQ[[...]

AMD Geode™ SC3200 Processor Data Book 389 Electrical Specifications 32581C T able 9-27 . IDE UltraDMA Data Bu rst Timin g Parameter s Symbol P arameter Mode 0 Mode 1 Mode 2 Unit Comments Min Max Min Max Min Max t 2CYC T ypical sustained average two cycle time 240 160 120 ns T wo cycle time allowing f or clock variations (from rising edge to next [...]

390 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C All timing parameters are measured at the connector of the device to which the parameter applies. For e xample, the sender stops generating STROBE edges t RFS after the negation of DMARD Y . Both STRO BE and DMARD Y timing measurements are taken at the connector of the sen[...]

AMD Geode™ SC3200 Processor Data Book 391 Electrical Specifications 32581C Figure 9-28. Sustained UltraDMA Data In Bur st Timing Diagram t DS t DH t DS t DH t DH t DVH t DVS t DVH t DVS t DVH t 2CYC t CYC t CYC t 2CYC IDE_D A T A[15:0] at device IDE_D A T A[15:0] at host IDE_IRD Y0 (DSTROBE0) at de vice IDE_IRD Y0 (DSTROBE0) at host Note: IDE_DA [...]

392 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-29. Host P ausing an UltraDMA Data In Burst Timing Diagram t RP IDE_D A T A[15:0] (de vice) t RFS t SR IDE_IRD Y0 (DSTROBE0) (device) IDE_IOR0 (HDMARD Y0 ) (host) IDE_IOW0 (ST OP0) (host) IDE_D ACK0 (host) IDE_DREQ0 (device) Notes: 1) The host can asser t IDE_IOW[[...]

AMD Geode™ SC3200 Processor Data Book 393 Electrical Specifications 32581C Figure 9-30. Device T erminating an Ultr aDMA Da ta In Burst Timing Dia gram IDE_D A T A[15:0] (de vice) IDE_CS[0:1]# IDE_ADDR[2:0] CR t ACK t DV H t DV S t ZAH t AZ t SS t LI t AC K t IORDZ t ACK t MLI t LI t LI IDE_IRD Y0 (DSTROBE0) (device) IDE_IOR0# (HDMARD Y0#) (host)[...]

394 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-31. Host T erminatin g an UltraDMA Data In Bur st Timing Diagram IDE_D A T A[15:0] (de vice) IDE_CS[0:1]# IDE_ADDR[2:0] CR t ACK t DV H t DV S t AC K t IORD Y Z t ACK t MLI t LI t RP t MLI t LI t RFS t AZ t ZAH IDE_IRD Y0 (DSTROBE0) (device) IDE_IOR0# (HDMARD Y0#)[...]

AMD Geode™ SC3200 Processor Data Book 395 Electrical Specifications 32581C Figure 9-32. Initiating an UltraDMA Data Out Burst Timing Diagram IDE_D A T A[15:0] (de vice) IDE_CS[0:1]# IDE_ADDR[2:0] t UI t AC K t ENV t LI t UI t ZIORD Y t ACK t DV S t DV H t AC K IDE_D ACK0# (host) IDE_DREQ0 (device) IDE_IO W0# (ST OP0#) (host) IDE_IORD Y0 (DDMARD Y[...]

396 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-33. Sustained UltraDMA Data Out Bur st Timing Diagram t DS t DH t DS t DH t DH t DVH t DVS t DVH t DVS t DVH t 2CYC t CYC t CYC t 2CYC IDE_D A T A[15:0] at host IDE_D A T A[15:0] at de vice IDE_IOR0# (HSTRO BE0#) at host IDE_IOR0# (HSTRO BE0#) at de vice Note: IDE[...]

AMD Geode™ SC3200 Processor Data Book 397 Electrical Specifications 32581C Figure 9 -34. Device Pausing an Ult raDMA Da ta Out Burst Tim ing Diagram t RP IDE_D A T A[15:0] (host) t RFS t SR IDE_IOR0# (HSTROBE0#) (host) IDE_DA CK0# (host) IDE_DREQ0 (device) IDE_IOW0# (ST OP0#) (host) IDE_IORD Y0# (DDMARD Y0#) (device) Notes: 1) The de vice can de-[...]

398 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-35. Host T erminating an UltraDMA Data Out Bur st Timing Diagram IDE_D A T A[15:0] (host) IDE_CS[0:1]# IDE_ADDR[2:0] CR t LI t MLI t AC K t LI t SS t LI t ACK t DV H t DV S t AC K t IORD YZ IDE_IOR0# (HSTROBE0#) (host) IDE_IORD Y0# (DDMARD Y0)# (device) IDE_IO W0#[...]

AMD Geode™ SC3200 Processor Data Book 399 Electrical Specifications 32581C Figure 9-3 6. Device T erminating an UltraDMA Data Out Burst Timing Diagram IDE_D A T A[15:0] (host) IDE_CS[0:1]# IDE_ADDR[2:0] CR t ACK t DV H t DV S t RFS t ACK t IORDZ t ACK t MLI t LI t RP t MLI t LI IDE_IOR0# (HSTROBE0#) (host) IDE_IORD Y0# (DDMARD Y0#) (device) IDE_D[...]

400 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.9 Universal Se rial Bus (USB) Interface T able 9-28 . USB Timing Parameters Symbol P arameter Min Ma x Unit Figur e Comments Full Speed Source (Note 1, Note 2) t USB_R1 DPOS_P or t1,2,3, DNEG_P or t1,2,3 Driver Rise Time 4 20 ns 9-37 (Monotonic) from 10% to 90% of the [...]

AMD Geode™ SC3200 Processor Data Book 401 Electrical Specifications 32581C t USB_DJU22 Source diff e rential driver jitter for paired transactions –150 15 0 ns 9-38 Function (downstream), Note 4 t USB_SE2 Source EOP width 1.25 1.5 μ s 9-39 Note 4, Note 5 t USB_DE2 Diff erential to EOP transiti on ske w –40 10 0 ns 9-39 Note 5 t USB_RJD21 Rec[...]

402 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-37. Data Signal Rise and F all Timing Diagram Figure 9-38. Source Differenti al Data Jitter Ti ming Diagram Rise Time F all Ti me t USB_R1,2 t USB_F1,2 90% 90% 10% 10% Differential Data Lines C L C L Full Speed: 4 to 20 ns at C L = 50 pF Low Speed: 75 ns at C L = [...]

AMD Geode™ SC3200 Processor Data Book 403 Electrical Specifications 32581C Figure 9-39. EOP Width Timing Diagram Figure 9-40 . Receiver J itter T oleran ce Timing Di agram EOP Width Data Crossov er Lev el Diff erential Data Lines t period_F tperiod_L Differential Data to SE0 Skew N*t period_F + t USB_DE1 N*t period_L + t USB_DE2 t USB_SE1, t USB_[...]

404 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.10 Se rial P o rt (U ART) Figure 9-41. U ART , Sharp-IR, SIR, and C onsumer Remote Co ntrol Timing Diagram T able 9-29. U ART , Sharp-IR, SIR, and Consumer Remote Contr ol Timing P arameters Symbol Parameter Min Max Unit Comments t BT Single bit time in U AR T and Shar[...]

AMD Geode™ SC3200 Processor Data Book 405 Electrical Specifications 32581C 9.3.11 Fast IR Port Figure 9-42. Fast IR (MIR and FIR) Timing Dia gram T able 9- 30. Fa st IR P ort Timing P arameters Symbol P a rameter Min Max Unit Comments t MPW MIR signal pulse width t MWN -25 (Note 1) t MWN +25 ns T rans mitter 60 ns Rece iver M DRT MIR tr an smitte[...]

406 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.12 Parallel Port Interfa ce Figure 9-43. Standar d Parallel P or t T ypical Data Exchange Timing Diagram T able 9-31 . Standar d P arallel P or t Timing P arameters Symbol Parameter Min T yp Max Unit Comments t PDH P or t data hold 500 ns Note 1 t PDS P or t data setup[...]

AMD Geode™ SC3200 Processor Data Book 407 Electrical Specifications 32581C Figure 9-44. Enhanced P arallel P or t Timing Diagram T able 9- 32. Enhanced P arallel P ort Timing P arameters Symbol P arameter Min Max EPP 1.7 EPP 1.9 Unit Comments t WW19a WRITE# active from W AIT# low 45 x ns t WW19i a WRITE# inactive from W AIT# low 45 x ns t WST19a [...]

408 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.12.1 Extende d Capab ilities P or t (ECP) Figure 9-45. ECP Forward Mode Timing Diagram T able 9-33. ECP Forward Mode Timing P arameters Symbol P a rameter Min Max U nit Comments t ECDSF Data setup bef ore STB# active 0 ns t ECDHF Data hold after BUSY inactive 0 ns t EC[...]

AMD Geode™ SC3200 Processor Data Book 409 Electrical Specifications 32581C Figure 9-46. ECP Reverse Mod e Timing Diagram T able 9-34. ECP Reverse Mod e Timing Parameter s Symbol P a rameter Min Max U nit Comments t ECDSR Data setup bef ore A CK# active 0 ns t ECDHR Data hold after AFD# active 0 ns t ECLHR AFD# inactive after A CK# active 75 ns t [...]

410 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.13 Audio Interface (A C97) Figure 9-47. A C97 Reset Timing Dia gram Figure 9-48. A C97 Sync Timing Diagram T able 9-35. AC Reset Timing Parameters Symbol P aramete r Min T yp Max Unit Comments t RST_LO W AC97_RST# activ e low pulse width 1.0 µs t RST2CLK A C97_RST# in[...]

AMD Geode™ SC3200 Processor Data Book 411 Electrical Specifications 32581C Figure 9-49. A C97 Cloc ks Diagram T able 9-37. A C97 Clocks P arameters Symbol Parameter Min T yp Max Unit Comments F BIT_CLK BIT_CLK frequency 12.288 MHz t CLK_PD BIT_CLK period 81.4 ns t CLK_J BIT_CLK output jitter 750 ps t CLK_H BIT_CLK high pulse width 32.56 40.7 48.8[...]

412 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-50. AC97 Data TIming Diagram T able 9-38 . A C97 I/O Timing Parameters Symbol Parameter Min T yp Max Unit Comments t AC 97_S Input setu p to f alling edge of BIT_CLK 15.0 ns t AC 97_H Hold from falling edge of BIT_CLK 10.0 ns t AC 97_OV SD A T A_OUT or SYNC valid [...]

AMD Geode™ SC3200 Processor Data Book 413 Electrical Specifications 32581C Figure 9-51. AC97 Rise and F all Timing Diagram T able 9-39. A C97 Signal Rise and Fall Timi ng P arameters Symbol Parameter Min T yp Max Unit Comments trise CL K BIT_CLK rise time 2 6 ns tfall CLK BIT_CLK f all ti me 2 6 ns trise SYNC SYNC r ise time 2 6 ns C L = 50 pF tf[...]

414 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-52. A C97 Low P ower Mode Timing Diagram T able 9- 40. A C97 Low P ower Mode Timing Parameter s Symbol Parameter Min T yp Max Unit Comments t s2_pdow n End of Slot 2 to BIT_CLK, SD A T A_IN low 1.0 µs SYNC BIT_CLK SDATA_OUT SDATA_IN Slot 1 Slot 2 Note: BIT_CLK is[...]

AMD Geode™ SC3200 Processor Data Book 415 Electrical Specifications 32581C 9.3.14 Po we r Management I nterface LED# Cycle time: 1 s ± 0.1 s, 40%-60% duty cycle . Figure 9-53. PWRBTN# T rigger and ONCTL# Timing Diagram Figure 9-54. GPWIO and ONCTL# Timing Diagram T able 9-41. PWRBTN# Ti ming Parameters Symbol Parameter Min Max U nit Comments t P[...]

416 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.15 Po we r-Up Sequencing Figure 9-55. Po wer-Up Sequenci ng With PWRBTN# Timing Diagr am T able 9-43. P ower -Up Sequence Using the P ower Button Timing Pa rameters Symbol Parameter Min Max U nit Comments t 1 V oltage sequence -100 100 ms Opti mum po wer-up results wit[...]

AMD Geode™ SC3200 Processor Data Book 417 Electrical Specifications 32581C Figure 9-56. P ower -Up Sequencing Without PWRBTN# Timing Diagram A CPI is n on-functional and all ACPI outputs are undefi ned when the power-up sequence does not include u sing the power button. SUSP# is an internal signal gen erated from the A C PI block. W ithout an A C[...]

418 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.16 JT A G Interface Figure 9-57. TCK Measurement P oints and Timing Diagram T able 9-45 . JT A G Timing P arameters Symbol Parameter Min Max U nit Comments TCK frequency 25 MHz t 1 TCK per iod 40 ns t 2 TCK high time 10 ns t 3 TCK low time 10 ns t 4 TCK rise time 4 ns [...]

AMD Geode™ SC3200 Processor Data Book 419 Electrical Specifications 32581C Figure 9-58. JT A G T est Timing Diagram TCK t 8 Input Output TDO TDI, t 11 t 13 t 9 t 7 t 6 t 12 t 10 TMS Signals Signals[...]

420 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C[...]

AMD Geode™ SC3200 Processor Data Book 421 10 Pac kage Specifications 32581C 10.0 P ac kage Specifications 10.1 Thermal Characteristics The junction-to-case ther mal resistance ( θ JC ) of the pac k- ages shown in T able 10-1 ca n be used to calculat e the junction (die) temperature under any given circumstance. Note that there is no specificatio[...]

422 AMD Geode™ SC3200 Processor Data Book Pac kage Specificatio ns 32581C 10.1.1 Heatsi nk Considerations T able 10-2 on page 421 shows the maximum allowed ther- mal resistance of a heatsink for par ticular operating envi- ronments. The calculated values, defined as θ CA , represent the required ability of a par ticular heatsink to transf er hea[...]

AMD Geode™ SC3200 Processor Data Book 423 Pac kage Specifications 3258 1C 10.2 Physical Dimensions The figures in this section provide the mechanical package outl ine f o r the BGU481 (481-T er minal Ball Grid Arra y Cavity Up) package. Figure 10-2. BGU481 P acka g e - T op Vie w[...]

424 AMD Geode™ SC3200 Processor Data Book Pac kage Specificatio ns 32581C Figure 10-3. BGU481 P ackage - Bottom Vie w[...]

AMD Geode™ SC3200 Processor Data Book 425 Appendix A: Suppor t Document ation 32581C Appendix A Suppor t Documentation A.1 Order Inf ormation Ordering P a rt Numb er (AMD OPN) 1 1. The “F” suffix denotes the Pb-free (lead-free) package. See Section 10.0 on page 421 for the BGU481 (481-terminal Ball Grid Array Cavity Up) package specificati on[...]

426 AMD Geode™ SC3200 Processor Data Book Appendix A: Data Bo ok Revision History 32581C A.2 Data Book Revision History This document is a repo r t of the revi sion/creation process of the data book fo r the AMD Geode™ SC320 0 processor . Any re vi sions (i.e., additions, deletions , parameter co rrections, etc.) are recorded in the tab le belo[...]

AMD Geode™ SC3200 Processor Data Book 427 Appendix A: Data Book Revision Histor y 32581C C (F ebruar y 2 007) T able 9-3 "Operating Conditions" on page 352: Change maximum VCORE and VSBL values from 1.89V to 1.99V . T able A-1. Revision History (Continu ed) Revision # (PDF Date) Revisio ns / Comments[...]

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