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Xilinx ML403 manual

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  • Page 1

    XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 1 © 2007 Xilinx, Inc. All rights reser v ed. All Xilinx trademarks, registered trademarks, patents , and fur ther disclaimers are as listed at http://www .xilinx.com/legal.htm . P owerPC is a trademark of IBM Inc. All other trademarks and registered trademarks are the proper ty of their respective[...]

  • Page 2

    Introduction XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 2 R Intr oduction This application note accompanies a ref erence system built on the ML403 de velopment board. Figure 1 is a bloc k diagram of the ref erence system. The system uses the embedded P owerPC (PPC) as the microprocessor and the OPB IIC core . IIC Primer Figure 2 shows compo[...]

  • Page 3

    Introduction XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 3 R Figure 4 shows the f or mat of the data transf er of two bytes on the IIC b us, beginning with the ST ART (S) condition and ending with the ST OP (P) condition, bounded by an idle IIC (F) b us. After a ST ART condition, an eight bit field is transmitted containing a 7 bit address [...]

  • Page 4

    Reference System Specifics XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 4 R Figure 6 shows the ac knowledge bit on the IIC bus . Figure 7 shows b us arbitration of two masters. The IIC b us is a multi-master bus . Masters monitor the IIC bus to determine if the bus is activ e. The bus is inactiv e when SCL and SD A are high f or a bus free p[...]

  • Page 5

    Reference System Specifics XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 5 R ML403 XC4VFX12 Address Map OPB IIC Registers Ta b l e 2 provides the register map f or the OPB IIC core. Ta b l e 3 provides a description of the OPB IIC control register . T able 1: ML403 XC4VSX12 System Address Map P eripheral Instance Base Address High Address PLB[...]

  • Page 6

    Reference System Specifics XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 6 R Status Register (SR) This register contains the status of the OPB IIC Bus Interf ace. All bits are cleared upon reset. Ta b l e 4 provides a definition of the status register . 27 TXAK T ransmit Acknowledge Enable. This bit specifies the value driven onto the SD A [...]

  • Page 7

    Reference System Specifics XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 7 R Ta b l e 5 provides a register description of the Interr upt Status register . 30 AAS Addressed as Slave. When the address on the IIC bus matches the Slav e address in the Address Register (ADR), the IIC Bus Interface is being addressed as a Slav e and switches to Sl[...]

  • Page 8

    Reference System Specifics XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 8 R Configuring the OPB IIC Core Figure 8 shows ho w to specify the values of IIC generics in EDK. T o access the dialog bo x in the figure, doub le click on the OPB IIC core in the EDK System Assembly Vie w .. Micr ochip 24LC04 The Microchip T echnology 24LC04B-I/ST w[...]

  • Page 9

    ML403 Board Inf ormation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 9 R is ‘1010 f or read and wr ite operations . The A2, A1 bits are dont cares. The A0 bit is used b y the master de vice to select which of the two 256-word bloc ks of memor y are accessed. The 24LC04 write transactions are either a byte write or a page write. The page wr[...]

  • Page 10

    ML403 Board Inf ormation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 10 R The resistors are located on the board as shown in Figure 12 . Figure 12: ML40x Resistors X979_12_022 3 07[...]

  • Page 11

    ML403 Board Inf ormation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 11 R If additional IIC de vices are connected to the bus via the e xpansion header as shown in Figure 13 , inser t additional pull-up resistors on the e xter nal signals connected at pins 31 and 32. The resistor values are dependent on the v oltage. Figure 13: Expansion Hea[...]

  • Page 12

    ML403 Board Inf ormation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 12 R Figure 14 shows the FPGA pins driving the IIC Bus. T otalPhase Aard vark Adapter In the ref erence design, the OPB IIC in the XC4VFX12 on the ML403 board interfaces to the IIC in the Aardvark Adapter . The Aardvark IIC/SPI Embedded Systems interface is a m ulti- functi[...]

  • Page 13

    ML403 Board Inf ormation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 13 R Figure 15 shows the Aardv ar k Control Center GUI. Interfacing to the OPB IIC on the ML403 Boar d to the Aar dv ark Adapter Figure 16 shows the principle interf ace blocks when tr ansf err ing data between the OPB IIC in the XC4VFX12 on the ML403 board and the IIC in t[...]

  • Page 14

    ML403 Board Inf ormation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 14 R 3. Inv oke XMD and connect to the MicroBlaz e processor by the f ollowing command: xmd -opt xapp.opt 4. Download the e xecutab le by the f ollowing command dow <path>/executable.elf Executing the Reference System fr om EDK T o ex ecute the system using EDK, follo[...]

  • Page 15

    ML403 Board Inf ormation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 15 R low_le vel_dynamic_eeprom : This project transmits and receiv es data using the low le vel (L0) software driver . The OPB IIC is the master and the 24LC04 is configured as the slav e. The OPB IIC master writes data into the 24LC04 and reads it back. This is a polled m[...]

  • Page 16

    Running the Applications XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 16 R Figure 18 shows the slav e example . The message is in transmit.txt, and is the sentence "Lester was here .". The transaction log matches the message. The address is 0x70. Click Master Write to generate the transaction. Running the Applications In XPS, select[...]

  • Page 17

    Running the Applications XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 17 R Select dynamic_eepr om and r ight clic k to build the project. If more than one softw are project is used, make the un used software projects inactive . Connect a serial cable to the RS232C por t on the ML403 board. Star t up a HyperT er minal. Set Bits per second to 9[...]

  • Page 18

    Using ChipScope with OPB IIC XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 18 R Using ChipScope with OPB IIC T o facilitate the use of ChipScope to analyz e OPB IIC hardware, the iic.cdc file is included in the ml403_ppc_opb_iic/chipscope director y . The iic.cdc is used to inser t a ChipScope ILA core into the opb_iic core. The f ollowing st[...]

  • Page 19

    Using ChipScope with OPB IIC XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 19 R 5. Figure 23 shows the GUI f or making net connections. Clic k Next to mov e to the Modify Connections window . If there are any red data or trigger signals, correct them. The Filter P atter n can be used to find net(s). As an e xample of using the Filter Pattern,[...]

  • Page 20

    Using ChipScope with OPB IIC XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 20 R The wa vef or m view er is more readable when buses r ather than discrete signals are displa yed. The Re verse Bus Order operation belo w Add to Bus in the figure can be useful in analyzing ChipScope results. 11. Set the trigger in the T rigger Setup window . The [...]

  • Page 21

    Linux Kernel XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 21 R 13. ChipScope results are analyzed in the w avef or m windo w as shown in Figure 25 . The wa vef or ms ma y be easier to read if the discrete signals are removed after the y are renamed. T o share the results with remote colleagues, sa ve the results in the w av eform window as a [...]

  • Page 22

    Linux Kernel XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 22 R 5. Under OS and Libraries , set the entries as shown in Figure 26 . V erify that the target director y is the same as the director y containing the Linux source . Figure 26: BSP Settings X979_26_012907[...]

  • Page 23

    Linux Kernel XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 23 R 6. Click Connect_P eriphs and add the OPB_INTC , OPB_SYSA CE, OPB_IIC, OPB_SPI, OPB_IIC , and OPB 16550 per ipherals , using the instance names shown in Figure 27 . Click OK . 7. Select Software → Generate Libraries and BSPs to generate the LSP in ml403_ppc_opb_iic/linux . 8. F [...]

  • Page 24

    Simulation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 24 R command from the command prompt: impact -batch etc/download.cmd 12. Inv oke XMD . From the ml403_ppc_opb_iic/linux directory , enter the f ollowing commands in the XMD window . rst dow arch/ppc/boot/images/zImage.initrd.elf con 13. View the output in the HyperT erminal window . Logi[...]

  • Page 25

    Simulation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 25 R In most cases, after data is transmitted, the test w aits for an interrupt from the OPB IIC . Inter nal signal names used in the OPB IIC core are pro vided in Ta b l e 6 . Figure 28: OPB IIC Simulation T able 6: Internal Signals in OPB IIC Signal Name Functionality Txak T ransmit ac[...]

  • Page 26

    Simulation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 26 R The simulation runs f or 2000 ns as shown in Figure 29 . There are 3 sections in the simulation, shown in the f ollowing figures. Figure 29: Complete Simulation X979_29_022 3 07[...]

  • Page 27

    Simulation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 27 R In the first test, which is shown in Figure 30 , the OPB IIC registers are read to v er ify the correct reset v alues. The interrupt registers are written and read. This occurs from 0 - 10 s . F ollowing this, an arbitration test is run. IIC_AA is initially the b us master , with t[...]

  • Page 28

    Simulation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 28 R Figure 31 provides the Arbitration Lost test code . This pseudo-code can be track ed in the simulation. Figure 31: Arbitration Lost T est Code w r i t e A D R _ 20 0x 2 0 wri t e CR_ 2 0 40 wri t e CR_ A A 0x0 1 wri t e AD R_A A AA wri t e I ER_ A A 0 x 04 w r i t e R C _FI F O_ PIR[...]

  • Page 29

    Simulation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 29 R The second test, shown in Figure 32 , runs from 575 s to 790 s ., Ths master , AA, receives 3C and 55 from 20. The f ollowing stimuli / results is seen in the opb_iic.wlf file. Figure 32: Simulation with iic_AA as Master X979_ 3 2_022 3 07[...]

  • Page 30

    Simulation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 30 R Figure 33 provides the test code used in the simulation with the OPB IIC with the AA address as the master . Figure 33: T est code with iic_AA as Master wri t e CR_ 2 0 0x4 0 -- G C, E n w r i t e A D R _ 20 0x 2 0 - S et s a dd r e ss as 0x 2 0 wri t e CR_ A A 0x0 1 - E n ab le w r[...]

  • Page 31

    Simulation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 31 R Figure 34 shows the third test sho wn in opb_iic.wlf , run from 800 - 2000 us. IIC_20 is the master writing to IIC_AA, which is a 10-bit slav e. Figure 34: Simulation with iic_AA as Master X979_ 3 4_012907[...]

  • Page 32

    Simulation XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 32 R Figure 35 provides the test code f or simulation with IIC_AA as master . Figure 35: T est Code for Simulation with iic_20 as Master write DTR_20 0xF2 write DTR_20 0xD5 read TX_FIFO_OCY 0x01 write CR_20 0x0D -- Tx, MS, En write RC_FIFO_PIRQ 0x01 write IER_AA 0x20 -- Enable AAS wait_f[...]

  • Page 33

    References XAPP979 (v1.0) F ebruar y 26, 2007 www .xilinx.com 33 R References DS434 OPB IIC Bus Interf ace (v1.02a) XAPP765 Getting Star ted with EDK and MontaVista Linux ML40x Embedded De velopment Platf or m User Guide UG080 (v2.5) May 24, 2006 ChipScope ILA T ools T utorial The IIC Bus Specification V ersion 2.1 Jan uar y 2000 Philips Semicondu[...]