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A good user manual
The rules should oblige the seller to give the purchaser an operating instrucion of Texas Instruments TMS320VC5402, along with an item. The lack of an instruction or false information given to customer shall constitute grounds to apply for a complaint because of nonconformity of goods with the contract. In accordance with the law, a customer can receive an instruction in non-paper form; lately graphic and electronic forms of the manuals, as well as instructional videos have been majorly used. A necessary precondition for this is the unmistakable, legible character of an instruction.
What is an instruction?
The term originates from the Latin word „instructio”, which means organizing. Therefore, in an instruction of Texas Instruments TMS320VC5402 one could find a process description. An instruction's purpose is to teach, to ease the start-up and an item's use or performance of certain activities. An instruction is a compilation of information about an item/a service, it is a clue.
Unfortunately, only a few customers devote their time to read an instruction of Texas Instruments TMS320VC5402. A good user manual introduces us to a number of additional functionalities of the purchased item, and also helps us to avoid the formation of most of the defects.
What should a perfect user manual contain?
First and foremost, an user manual of Texas Instruments TMS320VC5402 should contain:
- informations concerning technical data of Texas Instruments TMS320VC5402
- name of the manufacturer and a year of construction of the Texas Instruments TMS320VC5402 item
- rules of operation, control and maintenance of the Texas Instruments TMS320VC5402 item
- safety signs and mark certificates which confirm compatibility with appropriate standards
Why don't we read the manuals?
Usually it results from the lack of time and certainty about functionalities of purchased items. Unfortunately, networking and start-up of Texas Instruments TMS320VC5402 alone are not enough. An instruction contains a number of clues concerning respective functionalities, safety rules, maintenance methods (what means should be used), eventual defects of Texas Instruments TMS320VC5402, and methods of problem resolution. Eventually, when one still can't find the answer to his problems, he will be directed to the Texas Instruments service. Lately animated manuals and instructional videos are quite popular among customers. These kinds of user manuals are effective; they assure that a customer will familiarize himself with the whole material, and won't skip complicated, technical information of Texas Instruments TMS320VC5402.
Why one should read the manuals?
It is mostly in the manuals where we will find the details concerning construction and possibility of the Texas Instruments TMS320VC5402 item, and its use of respective accessory, as well as information concerning all the functions and facilities.
After a successful purchase of an item one should find a moment and get to know with every part of an instruction. Currently the manuals are carefully prearranged and translated, so they could be fully understood by its users. The manuals will serve as an informational aid.
Table of contents for the manual
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Page 1
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory [...]
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Page 2
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 T ABLE OF CONTENTS Description 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]
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Page 3
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 description The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the [...]
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Page 4
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 description (continued) CV HDS1 A18 A17 V SS A16 D5 D4 D3 D2 D1 D0 RS X2/CLKIN X1 HD3 CLKOUT V SS HPIEN[...]
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Page 5
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 description (continued) TMS320VC5402 GGU P ACKAGE (BOTTOM VIEW) A B D C E F H J L M K N G 1 2 3 4 5 6 7[...]
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Page 6
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Assignments for the TMS320VC5402GGU (144-Pin BGA) Package † SIGNAL NAME BGA BALL # SIGNAL NAME BG[...]
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Page 7
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 terminal functions The following table lists each signal, function, and operating mode(s) grouped by fu[...]
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Page 8
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 T erminal Functions (Continued) TERMINAL NAME DESCRIPTION TYPE † TERMINAL NAME DESCRIPTION TYPE † I[...]
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Page 9
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 T erminal Functions (Continued) TERMINAL NAME DESCRIPTION TYPE † TERMINAL NAME DESCRIPTION TYPE † O[...]
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Page 10
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 T erminal Functions (Continued) TERMINAL NAME DESCRIPTION TYPE † TERMINAL NAME DESCRIPTION TYPE † [...]
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Page 11
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 11 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 T erminal Functions (Continued) TERMINAL NAME DESCRIPTION TYPE † TERMINAL NAME DESCRIPTION TYPE † [...]
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Page 12
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory Th e ’5402 device provides both on-chip ROM and RAM memories to aid in system performance and[...]
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Page 13
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 13 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory map Page 0 Program Hex Data On-Chip DARAM (OVL Y = 1) External (OVL Y = 0) MP/MC = 0 (Microcomp[...]
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Page 14
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 relocatable interrupt vector table (continued) 1 5 76543210 IPTR MP/MC OVL Y A VIS DROM CLK OFF SMUL S[...]
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Page 15
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 15 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 0 0000 1 0000 1 3FFF Page 1 Lower 16K External 2 0000 2 3FFF Page 2 Lower 16K External . . . .[...]
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Page 16
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 on-chip peripherals The ’5402 device has the following peripherals: Software-programmable wait-s[...]
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Page 17
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 17 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 software-programmable wait-state generator (continued) T able 2. Software W ait-State Register (SWWSR)[...]
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Page 18
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 programmable bank-switching wait states The programmable bank-switching logic of the ’5402 is functi[...]
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Page 19
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 19 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 parallel I/O ports Th e ’5402 has a total of 64K I/O ports. These ports can be addressed by the PORT[...]
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Page 20
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial ports The ’5402 device includes two high-speed, full-duplex multichanne[...]
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Page 21
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 21 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial ports (continued) On the receiver , receive frame synchronization and clo[...]
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Page 22
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 clock generator (continued) The reference clock input is then divided by two (DIV mode) to generate cl[...]
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Page 23
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 23 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DMA controller The ’5402 direct memory access (DMA) controller transfers data between points in the [...]
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Page 24
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DMA priority level Each DMA channel can be independently assigned high priority or low priority relati[...]
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Page 25
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 25 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DMA channel index registers (continued) The element index and the frame index affect address adjustmen[...]
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Page 26
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DMA channel interrupt selection The DMA controller can generate a CPU interrupt for each of the six ch[...]
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Page 27
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 27 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory-mapped registers The ’5402 has 27 memory-mapped CPU registers, which are mapped in data memor[...]
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Page 28
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory-mapped registers (continued) T able 10. Peripheral Memory-Mapped Registers NAME ADDRESS DESCRIP[...]
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Page 29
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 29 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 McBSP control registers and subaddresses The control registers for the multichannel buffered serial po[...]
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Page 30
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DMA subbank addressed registers (continued) T able 12. DMA Subbank Addressed Registers DMA NAME ADDRES[...]
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Page 31
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 31 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 interrupts V ector-relative locations and priorities for all internal and external interrupts are show[...]
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Page 32
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 interrupts (continued) The bits of the interrupt flag register (IFR) and interrupt mask register (IMR)[...]
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Page 33
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 33 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 documentation support Extensive documentation supports all TMS320 DSP family of devices from produ[...]
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Page 34
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over specified temperature range (unless otherwise noted) † Supply voltage [...]
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Page 35
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 35 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended operating case temperature range (unless otherwise noted) [...]
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Page 36
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 internal oscillator with external crystal The internal oscillator is enabled by connecting a crystal a[...]
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Page 37
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 37 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 divide-by-two clock option (PLL disabled) Th e frequency of the reference clock provided at the X2/CLK[...]
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Page 38
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multiply-by-N clock option Th e frequency of the reference clock provided at the X2/CLKIN pin can be m[...]
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Page 39
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 39 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory and parallel I/O interface timing timing requirements for a memory read (MSTRB = 0) [H = 0.5 t [...]
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Page 40
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory and parallel I/O interface timing (continued) PS , DS R/W MSTRB D[15:0] A[19:0] CLKOUT t h(D)R [...]
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Page 41
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 41 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory and parallel I/O interface timing (continued) switching characteristics over recommended operat[...]
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Page 42
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory and parallel I/O interface timing (continued) PS , DS R/W MSTRB D[15:0] A[19:0] CLKOUT t d(CLKH[...]
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Page 43
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 43 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory and parallel I/O interface timing (continued) timing requirements for a parallel I/O port read [...]
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Page 44
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory and parallel I/O interface timing (continued) switching characteristics over recommended operat[...]
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Page 45
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 45 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ready timing for externally generated wait states ti mi ng requirements for externally generated wait [...]
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Page 46
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ready timing for externally generated wait states (continued) MSC MSTRB READY D[15:0] A[19:0] CLKOUT t[...]
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Page 47
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 47 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ready timing for externally generated wait states (continued) t su(RDY) MSC IOSTRB READY A[19:0] CLKOU[...]
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Page 48
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ready timing for externally generated wait states (continued) IOSTRB MSC READY D[15:0] A[19:0] CLKOUT [...]
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Page 49
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 49 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 HOLD and HOLDA timings timing requirements for memory control signals and HOLDA , [H = 0.5 t c(CO) ] ([...]
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Page 50
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 reset, BIO , interrupt, and MP/MC timings tim ing requirements for reset, BIO , interrupt, and MP/MC [[...]
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Page 51
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 51 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 reset, BIO , interrupt, and MP/MC timings (continued) BIO CLKOUT RS , INTn , NMI X2/CLKIN t h(BIO) t h[...]
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Page 52
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 instruction acquisition (IAQ ), interrupt acknowledge (IACK ), external flag (XF), and TOUT timings sw[...]
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Page 53
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 53 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 instruction acquisition (IAQ ), interrupt acknowledge (IACK ), external flag (XF), and TOUT timings (c[...]
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Page 54
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial port timing timing requirements for McBSP [H=0.5t c(CO) ] † (see Figure[...]
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Page 55
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 55 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial port timing (continued) (n–2) Bit (n–1) (n–3) (n–2) Bit (n–1) ([...]
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Page 56
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial port timing (continued) timing requirements for McBSP general-purpose I/O[...]
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Page 57
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 57 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or sl[...]
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Page 58
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or sl[...]
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Page 59
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 59 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or sl[...]
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Page 60
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or sl[...]
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Page 61
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 61 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 HPI8 timing switching characteristics over recommended operating conditions †‡§¶ [H = 0.5t c(CO)[...]
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Page 62
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 HPI8 timing (continued) timing requirements †‡§ (see Figure 35, Figure 36, Figure 37, and Figure [...]
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Page 63
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 63 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 HPI8 timing (continued) V alid t su(HSL-DSL) V alid t su(HBV -DSL) t su(HBV -DSL) ‡ HAS HBIL t h(DSL[...]
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Page 64
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 HPI8 timing (continued) Second Byte First Byte Second Byte t d(HCS-HRDY) HCS HDS HRDY Figure 36. Using[...]
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Page 65
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 65 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DA T A PGE (S-PQFP-G144) PLASTIC QUAD FLA TP ACK 4040147/C 10/96 0,27 72 0,17 37 73 0,13 NO[...]
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Page 66
SPRS079E – OCT OBER 1998 – REVISED AUGUST 2000 66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DA T A GGU (S-PBGA-N144) PLASTIC BALL GRID ARRA Y P ACKAGE 0,80 0,10 M 0,08 0,80 9,60 TYP 1[...]
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Page 67
PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) DSG5402PGE100 ACTIVE LQFP PGE 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YR TMS320VC5402GGU100 ACTIVE BGA GGU 144 160 TBD SNPB Level-3-220C-168HR TMS320VC5402GGUR10 ACTIVE BGA GGU 144 1000 T[...]
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Page 68
IMPORT ANT NOTICE T exas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orde[...]
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Page 69
WWW .ALLDA T ASHEET .COM Copyright © Each Manufacturing Company . All Datasheets cannot be modified without permission. This datasheet has been download from : www .AllDataSheet.com 100% Free DataSheet Search Site. Free Download. No Register . Fast Search System. www .AllDataSheet.com[...]