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Summit S93WD463 manual

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Table of contents for the manual

  • Page 1

    © SUMMIT MICROELECTRONICS, Inc. 2001 • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com 1 S93WD462/S93WD463 Characteristics subject to change without notice Precision Supply-V oltage Monitor and Reset Controller With a W atchdog Timer and 1k-bit Micro wire Memory SUM[...]

  • Page 2

    2 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. PIN FUNCTIONS Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output V CC +2.7 to 6.0V Power Supply GND Ground RESET/RESET# RESET I/O PIN CONFIGURATION DEVICE OPERATION APPLICATIONS The S93WD462/WD463 is ideal for applications requir- ing low volt[...]

  • Page 3

    3 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status [...]

  • Page 4

    4 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deselected for a minimum of 250ns (t CSMIN ). The falling edge of CS will start the auto erase cycle of the selected memory location. The ready/busy status of the S93WD462/WD463 can be determined by [...]

  • Page 5

    5 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. SK 2029 ILL 5.0 CS DI DO t CS ST ANDBY HIGH-Z HIGH-Z 101 A N A N-1 A 0 D N D 0 BUSY READY ST A TUS VERIFY t SV t HZ t EW SK 2029 ILL6.0 CS DI DO ST ANDBY HIGH-Z HIGH-Z 1 A N A N-1 BUSY READY ST A TUS VERIFY t SV t HZ t EW t CS 11 A 0 Figure 3. Write Instruction Timing Figure 4. Eras[...]

  • Page 6

    6 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. Figure 7. WRAL Instruction Timing INSTRUCTION SET Instruction Start Opcode Address Data Comments B i t x8 x16 x8 x16 READ 1 1 0 A6 – A0 A5 – A0 Read Address AN – A0 ERASE 1 11 A6 – A0 A5 – A0 Clear Address AN – A0 WRITE 1 0 1 A6 – A0 A5 – A0 D 7 – D0 D15 – D0 Wri[...]

  • Page 7

    7 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ......................................................................................................... ........................... – 55 ° C to +125 ° C Storage Temperature .......................................................[...]

  • Page 8

    8 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. Limits V CC =2.7V-4.5V V CC =4.5V-5.5V Test SYMBOL PARAMETER Min. Max. Min. Max. UNITS Conditions t CSS CS Setup Time 100 50 ns t CSH CS Hold Time 0 0 ns V IL = 0.45V t DIS DI Setup Time 200 100 ns V IH = 2.4V t DIH DI Hold Time 200 100 ns C L = 100pF t PD1 Output Delay to 1 0.5 0.2[...]

  • Page 9

    9 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. Figure 8. RESET Timing Diagram RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS 2.7 5 Volt-A 5 Volt-B Symbol Parameter Min Max Min Max Min Max Unit V TRIP Reset Trip Point 2.55 2.7 4.25 4.5 4.50 4.75 V t PURST Power-Up Reset Timeout 130 270 130 270 130 270 ms t RPD V TRIP to RESET[...]

  • Page 10

    10 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. 8 Pin SOIC 8 Pin PDIP .05 (1.27) TYP. 1 8 Pin SOIC 0.150 - 0.157 (3.80 - 4.00) 0.189 - 0.196 (4.80 - 5.00) 0.053 - 0.069 (1.35 - 1.75) 0.013 - 0.020 (0.33 - 0.51) 0.004 - 0.010 (0.10 - 0.25) 0.016 - 0.050 (0.40 - 1.27) × 45 º 0.010 - 0.020 (0.25 - 0.50) 0.228 - 0.244 (5.80 - 6.20[...]

  • Page 11

    11 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. Frequently the reset controller will be deployed on a PC board that provides a peripheral function to a system. Examples might be modem or network cards in a PC or a PCMCIA card in a laptop. In instances like this the peripheral card may have a requirement for a clean reset functio[...]

  • Page 12

    12 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. Ready/Busy Status During the internal write operation the S93WD462/WD463 memory array is inaccessible. After starting the write operation (taking CS low) the host can implement a 10ms timeout routine or alternatively it can employ a polling routine that tests the state of the DO pi[...]

  • Page 13

    13 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. ORDERING INFORMATION Blank = T ube T = T ape & Reel A = 4.5V to 5.5V V TRIP min. @ 4.25V B = 4.5V to 5.5V V TRIP min. @ 4.50V 2.7 = 2.7V to 5.5V V TRIP min. @ 2.55V S93WD462 P A T Base P ar t Number Pa ck ag e P = 8 lead PDIP S = 8 lead 150mil SOIC S93WD462 = 8-bit configuratio[...]

  • Page 14

    14 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, convey[...]