SMSC LPC47N217N manual

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Table of contents for the manual

  • Page 1

    SMSC LPC47N217N 64TQFP PRODUCT PREVIEW Revision 0.2 (09-25-08) Data Brief PRODUCT FEA TURES LPC47N217N 64-Pin Super I/O with LPC Interface  3.3 V olt Operation (5V toleran t)  Programmable Wakeup Event Interface (IO_PME# Pin)  SMI Support (IO_SMI# Pin)  GPIOs (14)  T wo IRQ Input Pins  XNOR Chain  PC2001  ACPI 2.0 Compliant [...]

  • Page 2

    ORDER NUMBER(S): LPC47N217N-JV FOR 64 PIN, TQFP LEAD-FREE ROHS COMPLIANT PACKAGE 64-Pin Super I/O with LPC Interface Revision 0.2 (09-25-08) 2 SMSC LPC47N217N 64TQFP PRODUCT PREVIEW 80 ARKA Y DRIVE, HAUPP AUGE, NY 1 1788 (631) 435-600 0, FAX (63 1) 273-3123 Copyright © 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other [...]

  • Page 3

    64-Pin Super I/O with LPC Interface SMSC LPC47N217N 64TQFP 3 Revision 0.2 (09-25-08) PRODUCT PREVIEW General Description The SMSC LPC47N217N is a 3.3V PC 99, PC200 1, an d ACPI 2.0 compli ant Super I/O Controller . The LPC47N217N implements the LPC interface, a pin re duced ISA interface which provides th e same or better performance as the ISA/X-b[...]

  • Page 4

    64-Pin Super I/O with LPC Interface Revision 0.2 (09-25-08) 4 SMSC LPC47N217N 64TQFP PRODUCT PREVIEW Block Diagram Figure 1 LPC47N217N Block Diagram TXD1, nRTS1, nDTR1 SER_IRQ PCI_CLK Vcc Vss IO_PME# Denotes Multifunction Pins SERIAL IRQ LPC BUS INTERFACE V TR CLOCK GEN CLOCKI SMI PME WDT * 16C550 COMPATIBLE SERIAL PORT 1 nCTS1, RXD1, nDSR1, nDCD1,[...]

  • Page 5

    64-Pin Super I/O with LPC Interface SMSC LPC47N217N 64TQFP 5 Revision 0.2 (09-25-08) PRODUCT PREVIEW Package Outline Notes: 1. Controlling Unit: mil limeter . 2. T olerance on the true position of the l eads is ± 0.035 mm maximum. 3. Package body dimensions D1 and E1 do no t include the mold protrusion. Maximum mold protrusion i s 0.25 mm per side[...]