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SMSC LAN9500 manual

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Table of contents for the manual

  • Page 1

    SMSC LAN9500/LAN9500i Revision 1.7 (10-02-08) DA T ASHEET Datasheet PRODUCT FEA TURES LAN9500/LAN9500i Hi-S peed USB 2.0 to 10/100 Ethernet Controller Highlight s  Single Chip Hi-S peed USB 2.0 to 10/100 Ethernet Controller  Integrated 10/100 Etherne t MAC w ith Full-Duplex Support  Integrated 10/100 Ethernet PHY with HP Auto-MDIX support [...]

  • Page 2

    Hi-S peed USB 2.0 to 10/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 2 Revision 1.7 (10-02-08) DA T ASHEET ORDER NUMBER(S): LAN9500-ABZJ FOR 56-PIN, QFN LEAD-FREE ROHS COMPLIANT P A CKAGE (0 TO +70°C TEMP RANGE) LAN9500i-ABZJ FOR 56-PIN, QFN LEAD-FREE ROHS COMPLIANT P ACKAG E (-40 T O +85°C TEMP RANGE) 80 ARKA Y DRIVE, HAUPP A UGE, NY [...]

  • Page 3

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 3 Revision 1.7 (10-02-08) DA T ASHEET T able of Content s Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

  • Page 4

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 4 SMSC LAN9500/LAN9500i DA T ASHEET List of Figures Figure 1.1 LAN9500/LAN9500i System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2.1 LAN9500/LAN9500i 56-Q FN Pin Assignments (TOP VIEW) . . . . . . . . . . .[...]

  • Page 5

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 5 Revision 1.7 (10-02-08) DA T ASHEET List Of T ables Table 2.1 MII Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2.2 EEPROM Pins . . . . . . . . . . . . . . . . . . . . . .[...]

  • Page 6

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 6 SMSC LAN9500/LAN9500i DA T ASHEET Chapter 1 Introduction 1.1 Block Diagram 1.1.1 Overview The LAN9500/LAN9500i is a high pe rformance Hi-S peed USB 2.0 to 10/100 Ethernet controller . With applications ranging from embedde d systems, set-top boxes, and PVR’ s , t[...]

  • Page 7

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 7 Revision 1.7 (10-02-08) DA T ASHEET 1.1.2 USB The USB portion of the LAN9500/LAN9500i integrates a Hi-S peed USB 2 .0 device controller and USB PHY . The USB device controller co ntains a USB low-level protocol interpreter which implemen ts the USB bus protocol, pack[...]

  • Page 8

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 8 SMSC LAN9500/LAN9500i DA T ASHEET 1.1.6 EEPROM Controller The LAN9500/LAN9500i contains an EEPROM controller for connection to an external EEPROM. This allows for the auto matic loadi ng of static configuration data upon power-on reset, pin reset, or software reset[...]

  • Page 9

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 9 Revision 1.7 (10-02-08) DA T ASHEET Chapter 2 Pin Description and Configuration Figure 2.1 LAN9500/LAN9500i 56-QFN Pin As signments (T OP VIEW) VSS NOTE: Exposed pad (VSS) on bottom of package must be connec ted to ground NOTE: When HP Auto-MDIX is activ ated, the TX[...]

  • Page 10

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 10 SMSC LAN9500/LAN9500i DA T ASHEET T able 2.1 MII Interface Pins NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION 1 Receive Error (External PHY Mode) RXER IS (PD) Receive Error: In external PHY mode, the signal on this pin is input from the external PH Y and indicates [...]

  • Page 11

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 1 1 Revision 1.7 (10-02-08) DA T ASHEET 1 T ransmit Data 3 (External PHY Mode) TXD3 O8 (PU) T ransmit Data 3: In external PHY mode, this pin functions as the transmit data 3 output to the external PHY . General Purpose I/O 7 (Internal PHY Mode Only) GPIO7 IS/O8/ OD8 (P[...]

  • Page 12

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 12 SMSC LAN9500/LAN9500i DA T ASHEET Note 2.1 Configuration strap va lues are latched on pow er-on reset and system reset. Configuration straps are identified by an u nderlined symbol n ame. Signals that function as co nfiguration straps must be augmented with an ext[...]

  • Page 13

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 13 Revision 1.7 (10-02-08) DA T ASHEET Note 2.2 Configuration strap va lues are latched on pow er-on reset and system reset. Configuration straps are identified by an u nderlined symbol n ame. Signals that function as co nfiguration straps must be augmented with an ext[...]

  • Page 14

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 14 SMSC LAN9500/LAN9500i DA T ASHEET 1 JT AG T est Clock (Internal PHY Mode) TCK IS (PU) JT AG T est Clock: In internal PHY mode, this pin functions as the JT AG test clock. The maximum operating frequency of this clock is 25MHz. Receive Data 1 (External PHY Mode) RX[...]

  • Page 15

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 15 Revision 1.7 (10-02-08) DA T ASHEET 1 Ethernet Link Activity Indicator LED nLNKA_LED OD12 (PU) Ethernet Link Activi ty Indicator LED (Active- Low): This signal is driven low (LED on) when a valid link is detected. This pin is p ulsed high (LED off) for 80mS whenever[...]

  • Page 16

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 16 SMSC LAN9500/LAN9500i DA T ASHEET T able 2.5 USB Pins NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION 1 USB DMINUS USBDM AIO USB DMINUS Note: The functionality of this pin may be swapped to USB DPLUS via the PORT_SW AP configuration strap. 1 USB DPLUS USBDP AIO USB D[...]

  • Page 17

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 17 Revision 1.7 (10-02-08) DA T ASHEET 1 PHY Interrupt (Internal PHY Mode) nPHY_INT O8 PHY Interrupt (Active-Low): In internal PHY mode, this signal can be configured to output the internal PHY interrupt signal. Note: The internal PHY interrupt signal is active-hi gh. [...]

  • Page 18

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 18 SMSC LAN9500/LAN9500i DA T ASHEET T abl e 2.9 56-QFN Package Pin Ass ignments PIN NUM PIN NAME PIN NUM PIN NAME PIN NUM PIN NA ME PIN NUM PIN NAME 1 nPHY_INT 15 VDD33A 29 EECLK/ PWR_SEL 43 TXEN 2 TXN 16 USBRBIAS 30 EECS 44 RXER 3 TXP 17 VDD18USBPLL 31 EEDO/ AUTOMD[...]

  • Page 19

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 19 Revision 1.7 (10-02-08) DA T ASHEET 2.1 Buffer T ypes T abl e 2.10 Buffer T y pes BUFFER TYPE DESCRIPTION IS Schmitt-triggered Input IS_5V 5V T olerant Schmitt-tri ggered Input O8 Output with 8 mA sink and 8mA source OD8 Open-drain output with 8mA sink O12 Output wi[...]

  • Page 20

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 20 SMSC LAN9500/LAN9500i DA T ASHEET Chapter 3 EEPROM Controller (EPC) LAN9500/LAN9500i may use an external EEPROM to store the default values for the USB descriptors and the MAC address. The EEPROM controller supports most “93C46” type EEPROMs. The EEP_SIZE stra[...]

  • Page 21

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 21 Revision 1.7 (10-02-08) DA T ASHEET Note: EEPROM byte addresses past 1Dh can be used to store data for any purpose. T abl e 3.2 describes the Co nfiguration Flags. 09h Configuration Flags 0Ah Language ID Descriptor [7 :0] 0Bh Language ID Descriptor [1 5:8] 0Ch M anu[...]

  • Page 22

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 22 SMSC LAN9500/LAN9500i DA T ASHEET 3.2 EEPROM Default s The signature value o f 0xA5 is stored at address 0. A dif ferent signature value indicates to the EEPROM controller that no EEPROM or an un-progra mmed EEPROM is attached to LAN9500/LAN9500i. In this case, th[...]

  • Page 23

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 23 Revision 1.7 (10-02-08) DA T ASHEET 3.4 An Example of EEPROM Format Interpret ation Ta b l e 3 . 4 and Ta b l e 3 . 5 provide an example of ho w the content s of a EEPROM are formatted . T abl e 3.4 is a dump of the EEPROM m e mory (256-byte EEPROM), while T able 3.[...]

  • Page 24

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 24 SMSC LAN9500/LAN9500i DA T ASHEET T able 3.5 EEPROM Example - 256 Byte EEPROM EEPROM ADDRESS EEPROM CONTENT S (HEX) DESCRIPTION 00h A5 EEPROM Prog rammed Indica tor 01h - 06h 12 34 56 78 9A BC MAC Address 12 34 56 78 9A BC 07h 01 Full-S peed Poll ing Interval for [...]

  • Page 25

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 25 Revision 1.7 (10-02-08) DA T ASHEET 20h-27h 53 00 4D 00 53 00 43 0 0 Manufac turer ID S tring (“SMSC” in UNICODE) 28h 10 Size of Product Name S tring Descriptor (16 byte s) 29h 03 Descriptor Ty pe (S tri ng Descriptor - 03h) 2Ah-37h 4C 00 41 00 4E 00 39 00 35 00[...]

  • Page 26

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 26 SMSC LAN9500/LAN9500i DA T ASHEET 64h 04 Descriptor T ype (Int erface Descriptor - 04h) 65h 00 Number i dentifying this Interface 66h 00 V alue used to select altern ative setting 67h 03 Number of Endpoints used for this interface (Le ss endpoint 0) 68h FF Class C[...]

  • Page 27

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 27 Revision 1.7 (10-02-08) DA T ASHEET 88h 04 Descriptor T ype (Int erface Descriptor - 04h) 89h 00 Number i dentifying this Interface 8Ah 00 V a lue used to select alte rnative setting 8Bh 03 Number of Endpoints used for thi s interface (Less endpoint 0) 8Ch FF Class [...]

  • Page 28

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 28 SMSC LAN9500/LAN9500i DA T ASHEET Chapter 4 Operational Characteristics 4.1 Absolute Maximum Ratings* Supply V oltage (VDD33IO, VDD33A) ( Note 4.1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +3.6V Positive voltage on signal pins, with[...]

  • Page 29

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 29 Revision 1.7 (10-02-08) DA T ASHEET 4.3 Power Consumption This section details the power consumption of LAN9 500/ LAN9500i as measured d uring various modes of operation. Power consumption val ues are provided for both the device-only , and for the device plus Ether[...]

  • Page 30

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 30 SMSC LAN9500/LAN9500i DA T ASHEET 4.3.4 Operational Power Consumption 4.3.5 Customer Evalua tion Board Operationa l Power Consumption T able 4.4 Ope rational Power Consumption - Su pply and Current @3.3V PARAMETER MIN T YPICAL MAX UNIT 100BASE-TX Full Duplex (USB [...]

  • Page 31

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 31 Revision 1.7 (10-02-08) DA T ASHEET 4.4 DC S pecifications Note 4.5 This specification appli es to all inputs and tri-stated bi-directional pins. In ternal pull-down and pull-up resi stors add +/- 50uA per-pin (typical). T able 4.6 I/O Buffer Characteristics PARAMET[...]

  • Page 32

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 32 SMSC LAN9500/LAN9500i DA T ASHEET Note 4.6 This is the total 5.5V input l eakage for the entire device. Note 4.7 XI can optionally be d riven from a 25MHz single-ended clock oscil lator . Note 4.8 Measured at line side of transformer , line replaced by 10 0 Ω (+/[...]

  • Page 33

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 33 Revision 1.7 (10-02-08) DA T ASHEET 4.5 AC S pecifications This section details the various AC timing specifications of the LAN9500/L AN9500i. Note: The MII timing adheres to the IEEE 802.3 specification. Refe r to the IEEE 802.3 specification for detailed MII timin[...]

  • Page 34

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 34 SMSC LAN9500/LAN9500i DA T ASHEET 4.5.2 Power-On Configurat ion Strap V alid T iming Figure 4.2 illustrates the configuration strap vali d timi ng requirement in rel ation to power-on. In order for valid configuration strap values to be read at p ower-on, the foll[...]

  • Page 35

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 35 Revision 1.7 (10-02-08) DA T ASHEET 4.5.3 Reset and Confi guration Strap T iming Figure 4.3 illustrates the nRESET pin ti ming requirement s and i ts relation to the configuration strap pins and output drive. As sertion of nRESET is not a requirement. However , if u[...]

  • Page 36

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 36 SMSC LAN9500/LAN9500i DA T ASHEET 4.5.4 EEPROM Timing The following specifies th e EEPROM timing requirements for LAN9500/LAN950 0i: Figure 4.4 EEPROM T i ming T able 4.1 1 EEPROM Timing V alues SYMBOL DESCRIPTION MIN TYP MAX UNIT S t ckcyc EECLK Cycle time 1 1 10[...]

  • Page 37

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 37 Revision 1.7 (10-02-08) DA T ASHEET 4.5.5 T urbo MII Interface Timing The external MII supports Turbo MII and the interface timing i s as follows. Note 4.12 These values satisfy the MII specification r equirement o f 0 ns to 25 ns clock to output delay . Note 4.13 T[...]

  • Page 38

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 38 SMSC LAN9500/LAN9500i DA T ASHEET Note 4.14 These values satisfy the 10-ns setup and hold time requirements that are necessary for the T urbo MII specificati on. T able 4.13 T urbo MII Interface Timing V alues SYMBOL DESCRIPTION MIN MAX UNITS NOTES t rxsetup RXD a[...]

  • Page 39

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 39 Revision 1.7 (10-02-08) DA T ASHEET 4.6 Clock Circuit LAN9500/LAN9500i can accept either a 25MHz crys tal (preferred) or a 25MHz single-ended clock oscillator (+/- 50ppm) input. If the single-ended clock oscillato r met hod is implemented, XO should be left unconnec[...]

  • Page 40

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 40 SMSC LAN9500/LAN9500i DA T ASHEET Chapter 5 Package Outline Notes: 1. All dimensions are in mill imeters unless otherwise noted. 2. Position tolerance of each terminal and exposed pad is +/- 0.05 mm at maxi mum material condition. Dimension “b” applies to plat[...]

  • Page 41

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 41 Revision 1.7 (10-02-08) DA T ASHEET Figure 5.2 LAN9500/LAN9500i 56-QF N Recommended PCB Land Pattern[...]

  • Page 42

    Hi-S pee d USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.7 (10-02-08) 42 SMSC LAN9500/LAN9500i DA T ASHEET Chapter 6 Revision History T able 6.1 Customer Revision History REVISION LEVEL AND DATE SECTION/FIGUR E/ENTRY CORRECTION Rev . 1.6 (09-09-08 ) All Fixed various typos T able 3.4, “Dum p of EEPROM Memory ,” on page 23 Fixed typ[...]

  • Page 43

    Hi-S peed USB 2.0 to 1 0/100 Ethernet Controller Datasheet SMSC LAN9500/LAN9500i 43 Revision 1.7 (10-02-08) DA T ASHEET T abl e 2.4, “Miscellaneous Pins,” o n pag e 14 Added new TEST3 entry , which must always be grounded. Modified buffer types for TEST1 an d TEST2 entrie s to indicate “-” as buffe r type. Buf fer type now hidden. TEST3 cor[...]