Silicon Laboratories SI5324 manual

Rev. 0.5 6/11 Copyright © 2011 by Silicon Labo rato ries Si53xx-RM A NY -F REQUENCY P RECISION C LOCKS Si5316, Si5319, Si5322, Si5323, Si5324, Si5325, Si5326, Si5327, Si536 5, Si5366, Si5367, Si5368, Si5369, Si5374, Si5375 F AMILY R EFERENCE M ANUAL[...]

Si53xx-RM 2 Rev. 0.5[...]

Si53xx-RM Rev. 0.5 3 T ABLE OF C ONTENT S Section Page 1. Any-Frequency Precision Clock Pr oduct Family Overview . . . . . . . . . . . . . . . . . . . . . . 12 2. Narrowband vs. Wideba nd Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. Any-Frequency Clock Family Members . . . . . . . . . . . . . . . . [...]

Si53xx-RM 4 Rev. 0.5 6.3.1. Manual Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.2. Automatic Clock Selection (Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.3. Hitless Switching with Phase Build-O ut (Si5323, Si5366) .[...]

Si53xx-RM Rev. 0.5 5 and Si5375 Free Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.5.1. Fr ee Run Mode Programm ing Procedur e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.5.2. Clock Control Logic in Free Run Mode . . . . . . . . . . . . . . . . . . . . [...]

Si53xx-RM 6 Rev. 0.5 8.2.1. LVPECL TQFP Ou tput Signal Format Restrict ions at 3.3 V (Si5367, Si5368, Si5369) . . . . . . 107 8.2.2. Typical Output Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.2.3. Typical Cloc k Output Scope Shots . . . . . . . . . . . . . . . . . . . [...]

Si53xx-RM Rev. 0.5 7 L IST OF F IGURES Figure 1. Si5316 Any-Frequency Ji tter Attenuator Block Di agram . . . . . . . . . . . . . . . . . . . . . 17 Figure 2. Si5319 Any-Frequency Jitter Attenuating Clock Multiplier Blo ck Diagram . . . . . . . . 18 Figure 3. Si5322 Low Ji tter Clock Multiplier Block Dia gram . . . . . . . . . . . . . . . . . . . .[...]

Si53xx-RM 8 Rev. 0.5 Figure 43. Differential Output Example Requiring Attenuatio n . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 44. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOU Tn– Together) . . . . . . . 108 Figure 45. CKOUT Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

Si53xx-RM Rev. 0.5 9 Figure 88. RF Generator, Si532 6, Si5324; No Jitter (For Reference) . . . . . . . . . . . . . . . . . . 165 Figure 89. RF Generator, Si532 6, Si5324 (50 Hz Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 90. RF Generator, Si532 6, Si5324 (100 Hz Jitter) . . . . . . . . . . . . . . . . . . . . . . . . [...]

Si53xx-RM 10 Rev. 0.5 L IST OF T ABLES Table 1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Table 2. Product Selection Gu ide (Si5322/25/65/67) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3. Recommended Operating Conditions 1 . . . . . . . . . . .[...]

Si53xx-RM Rev. 0.5 11 Table 42. Digital Hold History Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 Table 43. Digital Hold History Averaging Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 44. CKIN3/CKIN4 Frequency Selection (CK_CONF = 1) . . . . . . . . . . . [...]

Si53xx-RM 12 Rev. 0.5 1. Any-Frequency Precision Clock Produ ct Family Overview Silicon Laboratories Any-Fr equency Precision Clock products provide ji tter attenuation and clock multiplication/ clock division for applications requir i ng sub 1 ps rms jitter perfor mance. The device product family is ba sed on Silicon Laboratories' 3rd generat[...]

Si53xx-RM Rev. 0.5 13 A wide range of settings are available, but they are a su bset of the frequen cy plans supported by the Si5323 and Si5366 jitter-attenuating clock multip liers. The Si5325 and Si5367 ar e microprocesso r-controlled clock m ultipliers that can be controlled via an I 2 C or SPI interface. These devices accept clock in puts rangi[...]

Si53xx-RM 14 Rev. 0.5 T able 1. Prod uct Selection Guide Part Number Control Number of Input s and Outputs Input Frequency (MHz) * Output Frequency (MHz) * RMS Phase Jitter ( 1 2k H z – 2 0M H z ) PLL Bandwi d th Hitless Switching Free Run Mode Package Si5315 Pin 1PLL, 2 | 2 0.008–644 0.008–644 0.45 ps 60 Hz to 8k H z  6x6 mm 36-QFN Si5316[...]

Si53xx-RM Rev. 0.5 15 T able 2. Product Sel ection Guide (Si5322/25/65/67) Device Clock Input s Clock Output s  P Control Max Input Freq (MHz) 1 Max Output Frequenc y (MHz) Jitter Generatio n (12 kHz – 20 MHz) LOS Hitless Switching FOS Alarm LOL Alarm FSYNC Realignment 36 Lead 6 mm x 6 mm QFN 100 Lead 14 x 14 mm TQFP 1.8, 2.5, 3.3 V Operation [...]

Si53xx-RM 16 Rev. 0.5 2. Narrowband vs. W ideband Overview The narrowband (NB) devices of fer a nu mb er of features and cap abilities th at are not available with the wideband (WB) devices, as outlined in the below list:  Broader set of frequency pla ns due to more divisor options  Hitless switching between input clocks  Lower minimum i n[...]

Si53xx-RM Rev. 0.5 17 3. Any-Frequency Clock Family Members 3.1. Si5316 The Si5316 is a low jitter , precision jitter attenu ator fo r high-speed c ommunicatio n systems , including OC -48, OC - 192, 10G Ethernet, and 10G Fibre Channe l. The Si5316 a ccept s dual clock input s in the 19, 38, 77, 155, 3 1 1, or 622 MHz frequency range and generates [...]

Si53xx-RM 18 Rev. 0.5 3.2. Si5319 The Si5319 is a jitter-attenuating pr ecision M/N cloc k multiplier for applications requiring sub 1 ps jitter performance. The Si5 319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz and sele ct frequencies to 1.4 GHz . The Si5319 can also use its [...]

Si53xx-RM Rev. 0.5 19 3.3. Si5322 The Si5322 is a low jitter , prec ision cl ock multiplier for applications requir ing clock multiplication without jitter attenuation . The Si5322 accepts dual cloc k inputs rangi ng from 19.44 to 707 MHz and generates two frequency- multiplied clock output s ranging from 19.44 to 1050 MHz. The input clock frequenc[...]

Si53xx-RM 20 Rev. 0.5 3.4. Si5323 The Si5323 is a jitter-attenuating prec ision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, Fibre Chann el, and br oadcast vid eo (HD SDI, 3G SDI). The Si5323 accepts dual clock inpu ts ranging from 8 kHz to 707 MHz and generates two frequency-multi plied clock outpu[...]

Si53xx-RM Rev. 0.5 21 3.5. Si5324 The Si5324 is a jitter-attenuating pre cis ion clock multiplier for ap plications requiring sub 1 ps jitter performance. The Si5324 accept s dual clock input s ranging from 2 kHz to 710 MHz and generates two independent, synchronous clo ck outputs ranging from 2 kHz to 94 5 MHz and select frequencies to 1.4 GHz. Th[...]

Si53xx-RM 22 Rev. 0.5 3.6. Si5325 The Si5325 is a low jitter , prec ision cl ock multiplier for applications requir ing clock multiplication without jitter attenuation. The Si5325 accepts dual clock input s rang ing from 10 to 710 MHz and generates two independent, synchronous clock output s ranging from 2 kHz to 945 MHz and select frequencies to 1[...]

Si53xx-RM Rev. 0.5 23 3.7. Si5326 The Si5326 is a jitter-attenua ting precis ion clock multiplier for applications requiring sub 1 p s jitter performa nce. The Si5326 accept s dual clock input s ranging from 2 kHz to 710 MHz and generates two independent, synchronous clo ck outputs ranging from 2 kHz to 94 5 MHz and select frequencies to 1.4 GHz. T[...]

Si53xx-RM 24 Rev. 0.5 3.8. Si5327 The Si5327 is a jitter-attenuating pre cis ion clock multiplier for ap plications requiring sub 1 ps jitter performance. The Si5327 accept s dual clock input s ranging from 2 kHz to 710 MHz and generates two independent, synchronous clock output s ranging from 2 kHz to 808 MHz . The device provides virtually any fr[...]

Si53xx-RM Rev. 0.5 25 3.9. Si5365 The Si5365 is a low jitter , prec ision cl ock multiplier for applications requir ing clock multiplication without jitter attenuation. The Si5365 accept s four clock input s ranging from 19.44 MHz to 707 MHz and generates five frequency-mu ltiplied clock out puts ranging from 19.4 4 M Hz to 1050 MHz. The input cloc[...]

Si53xx-RM 26 Rev. 0.5 3.10. Si5366 The Si5366 is a jitter-attenuating prec ision clock multiplier for high-speed communication systems, including SONET OC-4 8/OC- 192 , Ethe rnet, a nd F ibre Chan nel. Th e S i5366 acce pts four clock in puts rang ing fr om 8 kHz to 707 MHz and generates five frequency-multiplied clock ou tput s ranging from 8 kHz [...]

Si53xx-RM Rev. 0.5 27 3.1 1. Si5367 The Si5367 is a low jitter , prec ision cl ock multiplier for applications requir ing clock multiplication without jitter attenuation . The Si5367 accepts four cl ock inputs rang ing from 10 to 707 MHz and generates five frequency- multiplied clock outputs r anging from 2 kHz to 945 MHz an d select frequencies to[...]

Si53xx-RM 28 Rev. 0.5 3.12. Si5368 The Si5368 is a jitter-attenuating precision clock mult iplier for applications requ iring sub 1 p s rms jitter performanc e. The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five independent, synchronous clo ck outputs ranging fr om 2 kHz to 945 MHz and select frequencies to 1.4 GH[...]

Si53xx-RM Rev. 0.5 29 3.13. Si5369 The Si5369 is a jitter-attenuating precision clock mult iplier for applications requ iring sub 1 p s rms jitter performanc e. The Si5369 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five independent, synchronous clo ck outputs ranging fr om 2 kHz to 945 MHz and select frequencies to 1.4 GH[...]

Si53xx-RM 30 Rev. 0.5 3.15. Si5374 The Si5374 is a hig hly in tegr ated , 4- PLL jit ter-at tenu ating precision clock multiplier for applications requiring sub 1 ps jitter perfor mance. Each of the DSPLL® clock multiplie r engines accept s two input clocks rang ing from 2 kHz to 710 MHz and generates two independe nt, synchron ous output clocks r[...]

Si53xx-RM Rev. 0.5 31 3.16. Si5375 The Si5375 is a hig hly in tegr ated , 4- PLL jit ter-at tenu ating precision clock multiplier for applications requiring sub 1 ps jitter performance. Each of the DSPLL® clock multip li er engines accept s an input clock ranging fr om 2 kHz to 710 MHz and gen erates an output clock rangin g from 2 kHz to 808 MHz.[...]

Si53xx-RM 32 Rev. 0.5 4. Device S pecifications The following t ables are intended to si mplify device selection. The specific ations in the individual device data sheets t ake precede nce over this document. Refer to the re spective device data sheet for devices not listed in th e tables below . Figure 16. Differential V olt age Characteristics Fi[...]

Si53xx-RM Rev. 0.5 33 T able 4. DC Ch aracteristics Parameter Sy mbo l T est Condition Si5316 Si5322 Si5324 Si5325 Si5365 Si5366 Si5367 Si5368 Min T yp Max Uni ts Supply Current (Independent o f Supply V oltage) I DD L VPECL Format 622.08 MH z Out All CKOUT’s Enabled  — 251 279 mA  — 394 435 mA L VPECL Format 622.08 MH z [...]

Si53xx-RM 34 Rev. 0.5 Output Clocks (CKOUTn—See “8.2. Output Clock Drivers” for Conf iguring Output Drivers for L VPECL/CML/L VDS/CMOS) Common Mode V OCM L VPECL 100  load line-to-line  V DD – 1.42 —V DD – 1.25 V Differential Output Swing V OD L VPECL 100  load line-to-line 1  1.1 ?[...]

Si53xx-RM Rev. 0.5 35 Output Drive Current (CMOS driv- ing into CKO VOL for output low or CKO- VOH for output high. CKOUT+ and CKOUT - shorted externally) CKO IO CMOS Driving into CKO- VOL for output low or CKO VOH for out- put high. CKOUT+ and CKOUT– shorted externa lly . V DD =1 . 8V ICMOS[1:0] = 1 1  —7 . 5 — m A IC[...]

Si53xx-RM 36 Rev. 0.5 Input Mid Current I IMM Se e note 2  –2 — 2 µA Input High Current I IHH See note 2  —— 2 0 µ A L VCMOS Out put Pins Output V oltage Low V OL I O =2m A V DD =1 . 6 2V  —— 0 . 4 V I O =2m A V DD =2 . 9 7V  —— 0 . 4 V[...]

Si53xx-RM Rev. 0.5 37 T able 5. DC Ch aracteristics—Microprocessor Devices (Si5324 , Si5325, Si5367, Si5368) Parameter Symbol T est Conditio n Min T yp M ax Units I 2 C Bus Lines (SDA, SCL) Input V oltage Low V ILI2C — — 0.25 x V DD V Input V oltage High V IHI2C 0.7 x V DD —V DD V Input Current I II2C VIN = 0.1 x V DD to 0.9 x V DD –10 ?[...]

Si53xx-RM 38 Rev. 0.5 Figure 18. SPI Timing Diagra m T able 7. DC Ch aracteristics—Narrowband Devices (Si53 16, Si5319, Si5323, Si5366, Si5368) Parameter Symbol T est Condition Min T yp M ax Unit Single-Ended Reference Clock In put Pin XA (XB with cap to gnd) Input Resistance XA RIN (RA TE[1:0] = LM, ML, MH, or HM) — 10 — k  Input V oltage[...]

Si53xx-RM Rev. 0.5 39 Figure 19. Frame Synchronization T iming CLKOUT _2 CLKIN_4* FSYNC_ALIGN FSYN COUT* * CLKIN _2 and CLKI N_4 ar e the ac tive i nput c lock and f rame sync p air in this example t FSSU t FSH t 1/f FSYNC Fixed number of CLKOUT _2 clock cy cles. LATF[...]

Si53xx-RM 40 Rev. 0.5 T able 8. AC Characteristics—All De vices Parameter Symbol T est Condit ion Si5316 Si5322 Si5324 Si5325 Si5365 Si5366 Si5367 Si5368 Min T yp Max Unit s Input Frequency CKN F  19.38 — 710 MHz  19.43 — 707.35 MHz   0.002 — 707.35 MHz  10 — 71 0 MHz When used as frame synchroniza tio n inp u t ?[...]

Si53xx-RM Rev. 0.5 41 LV C M O S P i n s Input Capacitance C in   —— 3p F Minimum Rese t Pulse Width t RSTMN   1—— µ s Reset to Micropro- cessor Access Ready t READY   —— 1 0 m s L VCMOS Out put Pins LOSn Trigger Window LOS TRIG From last CKIN_n  to internal detection of[...]

Si53xx-RM 42 Rev. 0.5 Device Ske w Output Clock Skew , see Section 7.7.4 t SKEW  of CKOUT_n to  of CKOUT_m, CKOUT_n and CKOUT_m at same frequency and signal format PHASE OFFSET = 0 SQICAL = 1 CKOUT_AL W A YS_O N=1   —— 1 0 0 p s Coarse Skew Adjust Resolution t PHRES Using CLA T [7:0] register  —1 / F VCO ?[...]

Si53xx-RM Rev. 0.5 43 Output Phase Change due to T emperature V ari- ation t TEMP Max phase changes from –40 to +85 °C   — 300 500 ps Jitter T olera nce J TOL   See "5.2.3. Jitter T olerance" on page 49 . Phase Noise fout = 622.08 MHz CKO PN 1 kHz Offset   — –106 –87 dBc/[...]

Si53xx-RM 44 Rev. 0.5 T able 9. Jitter Generation (Si5316, Si5324, Si5366, Si5368) Parameter Symbol T est Condition 1,2,3,4,5 Min T yp Max GR-253 S p ec Unit Measurement Filter (MHz) DSPLL Bandwid th 2 Jitter Gen OC-1 92 J GEN 0.02–80 120 Hz — 4.2 6.2 30 ps pp/0.3 UIpp ps PP —. 2 7. 4 2 N / A p s rms 4–80 120 Hz — 3.7 6.4 10 ps pp/0.1 UIp[...]

Si53xx-RM Rev. 0.5 45 T able 1 1. Thermal Charact eristics Parameter Symbol T est Condition Devices V alue Unit Thermal Resistance Jun ction to Ambient  JA S till Air Si5316, Si5319, Si5322, Si5323, Si5324, Si5325 32 ºC/W Si5365, Si5366, Si5367, Si5368 40 ºC/W Thermal Resistance Jun ction to Case  JC S till Air Si5316, Si5319, Si5322, Si532[...]

Si53xx-RM 46 Rev. 0.5 5. DSPLL (All Devices) All members of the Any-Freq uency Precision Clocks family incorporate a phase-locked loop (PLL) that utilizes Silicon Laboratories' third generation DSPLL technology to eliminate jitter , noise, and the need for external VCXO and loop filter component s found in discrete PLL implem entations. This i[...]

Si53xx-RM Rev. 0.5 47 5.1. Clock Multiplication Fundamental to th ese pa rt s is a clock multiplication circuit th at is simplified in Figur e 21. By having a large range of dividers an d multipliers, ne arly any outp ut frequency c a n be created from a fixed input fr equency . For typi cal telecommunications and data communi cations applications [...]

Si53xx-RM 48 Rev. 0.5 5.2. PLL Performance All members of the Any-Freq uency Precision Clock family of devices provide extremely low jitter generat ion, a well- controlled jitter transfer function, a nd high ji tter tolerance. For more inform ation the loop band wid th and it s e f fect on jitter attenuation, see "Ap pendix H—Jitter Attenuat[...]

Si53xx-RM Rev. 0.5 49 5.2.3. J itter T oleran ce Jitter tolerance is defined as the maximum peak-to-pea k sinusoidal jitter tha t can be present o n the incoming clock before the DSPLL lose s lock. The tolerance is a function of the jitter fr equency , bec ause tolerance improves for lower input ji tter frequency . The jitter tolerance of the DSPLL[...]

Si53xx-RM 50 Rev. 0.5 6. Pin Control Part s (Si5316, Si5322, Si5323 , Si5365, Si5366) These part s provide high-performance clo ck multiplication wit h simple pin control. Many of the control inp uts are three levels: High, Low , and Medium. High and Low ar e standar d voltage levels determined by the supply volt age: V DD and Ground. If th e input[...]

Si53xx-RM Rev. 0.5 51 The Si5316 can accept a CKIN1 in put at a dif ferent freq uency tha n the CKIN2 input. The freq uency of one input clock can be 1x, 4x, or 32x the frequency of the other input clock. The output frequency is always e qual to the lower of the two clock inputs and is set via the FRQSEL [ 1:0] pins. The frequency applie d at each [...]

Si53xx-RM 52 Rev. 0.5 6.1.2. Clock M ultiplica t io n (S i5322, Si5323, Si5365, Si5366) These part s provide flexible freq uency plans for SONET , DA T AC OM , an d inte rw or kin g be tw ee n th e two ( T able 16, T able 17, an d T able 18 respectively). The CKINn input s must be th e same fr equency a s specified in the t a bles. The outputs are [...]

Si53xx-RM Rev. 0.5 53 7L L H M  19.4 4 1 19. 44 19.44 0.008 8L L H H  2 3 8.88 38. 88 0. 008 9L M L L  4 77. 76 77.76 0.008 10 LMLM  8 155.52 155.52 0.008 1 1 LMLH 8 x (255/238) 166.63 166.63 NA 12 LMML 8 x (255/237) 167.33 167.33 NA 13 LMMM 8 x (255/236) 168.04 168.04 NA 14 LMMH  16 31 1.04 31 1.04 0.008 15 LMHL  32 622.08 622.08[...]

Si53xx-RM 54 Rev. 0.5 28 MLLM  77.7 6 1/4 19.44 1 9.44 0.008 29 MLLH  1/2 38.88 3 8.88 0.008 30 MLML  1 77. 76 77.76 0.008 31 MLMM  2 155.52 155.52 0.008 32 MLMH  2 x (255/238) 166.63 166.63 NA 33 MLHL 2 x (255/237) 167.33 167.33 NA 34 MLHM 2 x (255/236) 168.04 168.04 NA 35 MLHH  4 3 11 . 0 4 3 11 . 0 4 0 . 0 0 8 36 MMLL  8 622[...]

Si53xx-RM Rev. 0.5 55 56 HLLL 167.33 237/255 155.52 155.52 NA 57 MMHM  1 167.33 167.33 NA 58 HLLM 4 x (237/255) 622.08 622.08 NA 59 MHML  4 669.33 669.33 NA 60 HLLH 168.04 236/255 155.52 155.52 NA 61 MMHM  1 168.04 168.04 NA 62 HLML 4 x (236/255) 622.08 622.08 NA 63 MHML  4 672.16 672.16 NA 64 HLMM  31 1.04 1 31 1.04 31 1.04 0.008 65[...]

Si53xx-RM 56 Rev. 0.5 82 HHLH 669.33 1/4 x 237/255 155.52 155.52 NA 83 HMML  1/4 167.33 167.33 NA 84 HHML 237/255 622.08 622.08 NA 85 HMMH  1 669.33 669.33 NA 86 HHMM 672.16 1/4 x 236 /255 155.52 155.52 NA 87 HMML  1/4 168.04 168.04 NA 88 HHMH 236/255 622.08 622.08 NA 89 HMMH  1 672.16 672.16 NA T able 16. SONET Clock Multiplication Set[...]

Si53xx-RM Rev. 0.5 57 T able 17. Dat acom Clock Multiplication Settings (FRQTBL = M, CK_CONF = 0) Setting FRQSEL[3:0] WB f IN (MHz) Mult Factor f OUT * (MHz) 0L L L L  15.625 2 31.25 1L L L M  46 2 . 5 2 LLLH  81 2 5 3L L M L  16 250 4L L M M  25 17/4 106.25 5 LLMH  51 2 5 6 LLHL 25/4 x 66/64 161.13 7 LLHM 51/8 x 66/64 164.36 8 LL[...]

Si53xx-RM 58 Rev. 0.5 34 MLHM  125 10/8 x 66/64 161.13 35 MLHH 10/8 x 66/64 x 255/238 172.64 36 MMLL 10/8 x 66 /64 x 255/237 173.37 37 MMLM  5x6 6 / 6 4 6 4 4 . 5 3 38 MMLH 5 x 66/64 x 255/23 8 690.57 39 MMML 5 x 66/64 x 255/23 7 693.48 40 MMMM  156.25 66/64 161.13 41 MMM H 66/64 x 255/238 172.64 42 MMHL 66/64 x 255/237 173.37 43 MMHM  [...]

Si53xx-RM Rev. 0.5 59 69 HLML 173.37 4/5 x 64/66 x 237/255 125 70 HLMM 64/66 x 23 7/255 156 .25 71 HLMH  237/255 161.13 72 HLHL 4 x 237/255 644.53 73 MHMM  46 9 3 . 4 8 74 HLHM 176.1 2/3 x 64/66 x 238/255 106.25 75 HLLL 64/66 x 23 8/255 159.3 75 76 HLLM  238/255 164.36 77 HLLH  4 x 238/255 657.42 78 MHMM  47 0 4 . 3 8 79 HLHH 176.84 [...]

Si53xx-RM 60 Rev. 0.5 102 HHML 693.48 1/5 x 64/66 x 237/255 125 103 HHMM 1/4 x 64/66 x 237/255 156.25 104 HHMH  1/4 x 237/255 161.13 105 H MML  1/4 173.37 106 HHHL 237/255 64 4.53 107 HMMM  16 9 3 . 4 8 108 HHHM 704.38 1/6 x 64/66 x 238/255 106.25 109 HHLL 1/4 x 64/66 x 238/255 159.375 1 10 HHLM  1/4 x ( 238/255) 1 64.36 111 H M M L [...]

Si53xx-RM Rev. 0.5 61 T able 18. SONET to Dat acom Clock Multiplication Settings Setting FRQSEL[3 :0] WB f IN (MHz) Mult Factor f OUT * (MHz) 0 LLLL 0.008 31 25 25 1 LLLM 6480 51.84 2 LLLH 53125/8 53.125 3 LLML 15625/2 62.5 4 LLMM 53125/4 106.25 5 LLMH 15625 125 6 LLHL 7 8125/4 156. 25 7 LLHM 159375/8 159.375 8 LLHH 53125/2 212.5 9 LMLL 53125 425 1[...]

Si53xx-RM 62 Rev. 0.5 30 MLML  62.500 2 125 31 MLMM  4 250 32 MLMH 74.176 91/25 0 27 33 MLHL 1 74.17582 34 MLHM 91 x 1 1/250 x 4 74.25 35 MLHH 74.250 4/1 1 27 36 MMLL 4 x 250/1 1 x 91 74.17582 37 MMLM 1 74.25 38 MMLH 77.760 10625/7776 106.25 39 MMML 3125/1944 125 40 MMMM 15625 /7776 156.25 41 MMMH 31875/15552 159.375 42 MMHL 15625/7776 x 66/6[...]

Si53xx-RM Rev. 0.5 63 52 MHHM 155.520 15625/15552 156.25 53 MHHH 31875/31 104 159.375 54 HLLL 15625/15552 x 66/6 4 161.13 55 HLLM 31875/31 104 x 66/64 164.36 56 HLLH 15625/155 52 x 66/ 64 x 255/238 172.64 57 HLML 31875 /31 104 x 66/ 64 x 255/238 176.1 58 HLMM 10625/7776 212.5 59 HLMH 10625/3888 425 60 HLHL 15625/388 8 x 66/64 644.53 61 HLHM 31875/7[...]

Si53xx-RM 64 Rev. 0.5 6.1.3. CKOUT3 and CKOUT4 (Si5365 and Si5366) Submultiples of th e output frequency on CKOUT1 and CKOUT2 can be produced on the CKOUT3 and CKOUT4 outputs using the DIV34 [1:0] cont rol pins as shown in T able 19. 6.1.4. Loop bandwid th (Si5316, Si 5322, Si5323, Si536 5, Si5366) The loop bandwid th (BW) is digit ally programmab [...]

Si53xx-RM Rev. 0.5 65 6.2. PLL Self-Calibration An internal self-calibrati on (ICAL) is performed before op eration to optimize loop paramete rs and jitter performance. While the se lf-calibration is being performed , the DSPLL is being internally controlled by th e self- calibration state machine, and the LO L alarm will be active for narrowband p[...]

Si53xx-RM 66 Rev. 0.5 T able 20. Si5316 , Si5322, and Si5323 Pins and Reset Pin # Si5316 Pin Name Si5322 Pin Name Si5323 Pin Name Must Reset af ter Changing 2 N/A FRQTBL FRQTBL Y e s 1 1 RA TE 0 N/A RA TE 0 Y es 14 DBL_BY DBL2_BY DBL2_BY No 15 RA TE1 N/A RA TE1 Y es 19 N/A N/A DEC No 20 N/A N/A INC No 22 BWSEL0 BWSEL0 BWSEL0 Y es 23 BWSEL1 BWSEL1 B[...]

Si53xx-RM Rev. 0.5 67 6.3. Pin Control Input Clock Control This section describes the clock select ion capabilities (manual input selection, automatic input selection, hitless switching, and revertive sw itching). When switching between two clocks, LOL may temporarily go high if the two clocks differ in frequency by more than 100 ppm. 6.3.1. Man ua[...]

Si53xx-RM 68 Rev. 0.5 6.3.2. Automati c Clock Selecti on (Si5322, Si5323, Si5365, Si5366) The AUT OSEL input pin set s the input clock selection mode as shown in T a ble 24. Automatic switching is either revertive o r non-revert ive. Setting AUTOSEL to M or H, c hanges the CSn_CAm pins to output pins tha t indica te the state of the a utomatic cloc[...]

Si53xx-RM Rev. 0.5 69 At power-on or rese t, the va lid CKINn with the highest priority (1 being the highest priority) is auto matically selected. If no valid CKINn is av ailable, the device suppre sses the output clocks and waits for a valid CKINn signal. If the currently selected CKINn goes into an alarm st ate, the nex t valid CKINn in priority [...]

Si53xx-RM 70 Rev. 0.5 6.4. Digit al Hold/VCO Freeze All Any-Frequency Pr ecision Clo ck devices featur e a hold over or VCO free ze mode, wh ereby the DSPL L is locked to a digital value. 6.4.1. Narro wband Digi ta l Hold (S i5316, Si5323 , Si5366) If an LOS or FOS condition exists on the selected input clock, the device enters digit al hold. In th[...]

Si53xx-RM Rev. 0.5 71 6.6. Output Phase Adjust (Si5323, Si5366) Overall device skew (CKINn to CKOUT_n phase delay) is controllable via th e INC and DEC input pins . A positive pulse applied at the INC pin incr eases the de vice skew by 1/f OSC , one period of the DCO ou tput clock . A pulse on the DEC pin decreases the skew by the same amount. Sinc[...]

Si53xx-RM 72 Rev. 0.5 6.6.5. Disa bling FS_O UT (Si5366 ) The FS_OUT maybe disabled via the DBLFS pin, see T abl e 29. The additional state (M) prov ided allows for FS_OUT to drive a CMOS load while th e other clock outputs use a dif ferent signal format as specified by the SFOUT[1:0] pins. 6.7. Output Clock Drivers The devices include a flexible o[...]

Si53xx-RM Rev. 0.5 73 6.8. PLL Byp ass Mode The device support s a PLL bypa ss mode in which the select ed input clock is fed di rectly to all enabled output buffers, byp assing the DSPLL. In PLL bypass mode, the i nput and output clocks will be at the same frequency . PLL bypass mode is useful in a laborato ry environment to measure system perf or[...]

Si53xx-RM 74 Rev. 0.5 6.9.3. FSYNC Align Alarm (Si5366 and CK_CONF = 1 and FRQTBL = L) At power-up or an y time after the PLL h as lost lock an d relocked , the dev ice automa tically per forms a re alignmen t of FS_OUT us ing the curre ntly active sync in put. After this , as long as the PLL remains in lock and a realignment is not requested, FS_O[...]

Si53xx-RM Rev. 0.5 75 6.9.5.1. PLL Lock Detect (Si5316, Si5323, Si5366) The PLL lock detection algorithm indicates the lock st atus on the LOL out put pin. The algo rithm works by continuously moni toring the phase of the input clock in relation to the phase of the feed back clock. If the time between tw o consecutive phas e cycle s lips is greater[...]

Si53xx-RM 76 Rev. 0.5 7. Microprocessor Controlled Part s (Si5 319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5 369, Si5374, Si5375) The devices in this family provide a ri ch set of cloc k multiplication/clock divi sion options, loop bandwidth selections, output clock phase adjustment, and device control options. 7.1. Clock Multiplication [...]

Si53xx-RM Rev. 0.5 77 Because there is only one DCO and all of the outp uts must be frequencies that are in teger divisions of the DCO frequency , there a re restrictions on the r atio of one output frequency to anot her output frequ ency . That is, there is considerable freedom in the ratio betwee n the input frequ ency and the first output fr equ[...]

Si53xx-RM 78 Rev. 0.5 Figure 26. Narrowband PLL Divider Settings (Si5319, Si5324, Si5326, Si5327, Si536 8, Si5369, Si5374, Si5375) T able 35. Narrowband Frequency Limit s Signal Frequency Limit s CKINn 2 kHz–710 MHz f 3 2 kHz–2 MHz f OSC 4.85–5.67 GHz f OUT 2 kHz–1.475 GHz Note: Fmax = 808 MHz for the Si5327, Si537 4 and Si5 375 T able 36. [...]

Si53xx-RM Rev. 0.5 79 The output divide r , NC1, is the product of a high-sp eed divider (N1_HS) a nd a low-speed divider ( N1_LS). Similarly , the fe edback divider N2 is the product of a h igh-speed divider N2_HS and a low-spee d divider N2_LS. When multiple combinati ons of high-speed and lo w-spee d divider values are available to produce t he [...]

Si53xx-RM 80 Rev. 0.5 calibration and will appear afte r the self-calibration routine is completed. The SQ_ICAL bit is self-clearing after a successful ICAL. After a su ccessful self-calibration ha s been perform ed with a va lid input clock, it is not ne cessary to rein itiate a self- calibration for subseq uent losses of input clock. If the in pu[...]

Si53xx-RM Rev. 0.5 81 7.3. Input Clock Confi gurations (Si5367 and Si5368) The device support s two input clock configurations based on CK_CONFIG_REG . See "6 .5. Frame Synchr onization (Si5366)" on pa ge 70 for additional det ails. 7.4. Input Clock Control This section describes the clock select ion capabilities (manual input selection, [...]

Si53xx-RM 82 Rev. 0.5 Figure 28. Si5367, Si5368, and Si5369 Input Clock Selection 7.4.1. Manual Clock Selec tion (Si5324, Si5325, Si5326, Si5367, Si5 368 , Si5369, Si5374) Manual control of input clock selection is available by setting the AUT OSEL_REG [1:0] register bit s to 00. In manua l mode, the active input cl ock is chosen via the CKSEL_REG [...]

Si53xx-RM Rev. 0.5 83 If the selected clock enters an a larm condition, the PLL enters digit al hold mode. The CKSEL_REG [1:0] c ontrols are ignored if auto matic clock selection is enabled . 7.4.2. Auto matic Clock Selection (S i5324, Si 5325, Si5326, Si5367 , Si5368, Si5369, Si537 4) The AUTOSEL_REG [1 :0] register bit s sets the input clock sele[...]

Si53xx-RM 84 Rev. 0.5 7.4.2.2. De tailed Automatic Clock S elect ion Description (Si5367, Si5368, Si5369) The prioritization of clock input s for automatic switching is shown in T able 41. For example, if CK_CONFIG_REG = 0 and t he desired clo ck priority order is CKIN4, CKIN3, CKIN2, and then CKIN1 as the lowest priority clo ck, the user should se[...]

Si53xx-RM Rev. 0.5 85 7.5. Si5319, Si5324, Si5326, Si5327, Si5368, Si 5369, Si5374 and Si 5375 Free Run Mode Figure 29. Free Run Mode Block Diagram  CKIN2 has an extra mux with a p ath to the crystal os cillator output.  When in Free Run mode, CKIN2 is sacrif iced (Si5326, Si5368, Si5369, Si537 4).  Switching between the crystal o scillato[...]

Si53xx-RM 86 Rev. 0.5 7.5.3. Free Run Referen ce Frequency Constraint s  All crystals and external oscillato rs must lie within these two bands  Not every crystal will work; they should be tested  An external oscillator can be used at all four bands  The frequency at the phase detector (f 3) must be the same for both CKIN1 and XA/[...]

Si53xx-RM Rev. 0.5 87 7.6. Digit al Hold All Any-Frequency Pr ecision Clock devices feature a hold over mode, whereby the DSPLL is locked to a digital value. 7.6.1. Narrowband Digi ta l Hold (Si5316, Si5324, Si5326, Si5368, Si5369, Si5374) After the p art's initial self-calibration (ICAL), when no valid input clock is available, the device ent[...]

Si53xx-RM 88 Rev. 0.5 If a highly stable reference, such as an oven-contro lled crystal oscillator (OCXO) is supplied at XA/XB, an extremely stable digital hold can be achieved. If a crystal is supplied at the XA/XB port , the digit al hold stability will be limited by the stability of the crystal. T able 42. Di git al Hold History Delay HIST_DEL [[...]

Si53xx-RM Rev. 0.5 89 7.6.2. History Settings for Lo w Bandwid th Devices (Si532 4, Si5327, Si5369, Si5374) Because of the extraordinar ily low lo op bandwidt h of the Si5324, Si5369 and Si537 4, it is recommended that the values for both history registers b e increased for longer histories. 7.6.3. Reco very from Digital Hold (Si531 9, Si 5324, Si5[...]

Si53xx-RM 90 Rev. 0.5 7.7. Output Phase Adjust (Si5326, Si5368) The device has a highly accurate, digita lly controlled device s kew capability . For more informatio n on Output Phase Adjustments, se e both DSPLL sim and the respective dat a sheets. Both can be do wnloaded by going to www .silabs.com/timing and clicking on “Documentatio n” at t[...]

Si53xx-RM Rev. 0.5 91 Before writing a new FLA T [14:0] valu e, the FLA T_V ALID bit must be set to 0 to hold the existing FLA T [1 4:0] value while the new value is being written. Once the new value is written, set FLA T_V ALID = 1 to enable its use. T o verify a written value into FLA T , the FLA T register sh ould be read af ter the register is [...]

Si53xx-RM 92 Rev. 0.5 Figure 32. Frame Sync Frequencies T able 44. CKIN3/CKIN4 Frequency Selec tion (CK_CONF = 1) CKLNnRA TE [2:0] CKINn Frequency (kHz) Divisor 000 2 –4 1 001 4 –8 2 010 8–16 4 01 1 16–32 8 100 32–64 16 101 64–128 32 1 10 128–256 64 1 1 1 256–5 12 128 CKIN3 CKIN4  CLKIN3RATE Clock select DCO, 4.85 GHz to 5.67 GHz[...]

Si53xx-RM Rev. 0.5 93 The NC5_LS divider uses CKOUT2 as its clock inpu t to derive FS_OUT . The limits for the NC5_LS divider are NC5_LS = [1, 2, 4, 6, …, 2 19 ] f CKOUT2 < 710 MHz Note that wh en in fram e synchronizat i on rea lign m en t m o de , w rite s t o NC5_LS are controlled by FPW_V ALID . See section “7.8.4. FS_OUT Polarity and Pu[...]

Si53xx-RM 94 Rev. 0.5 For cases where phase skew is required, see Section “7.7 . Outp ut Phase Adjust (Si53 26, Si5368)” fo r more det ails on controlling the sync input to sync output phase skew via the FSYNC_SKEW [16:0] bits. See Sectio n “8.2. Output Clock Drivers” for informatio n on the FS_OUT signal format, pulse width, and active log[...]

Si53xx-RM Rev. 0.5 95 7.9. Output Clock Driver s (Si5319, Si5324, Si5325, Si5326, Si5327 , Si5367, Si5368, Si5369, Si5374, Si5375) The device includes a flexible output driver structure th at can drive a variety of l oads, including L VPECL, L VDS, CML, and CMOS forma ts. The signal format of each output is individually config urable through the SF[...]

Si53xx-RM 96 Rev. 0.5 7.10. PLL Byp ass Mode (Si 5319, Si5324, Si5325, Si 5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375) The device support s a PLL bypass mode in which the select ed input clock is fe d directly to t he output buffers, bypassing the DSPLL. In PLL bypass mode, the input and output clocks will be at the same frequency . PLL by[...]

Si53xx-RM Rev. 0.5 97 7.1 1.1.2. Standard LOS (Si5319, Si5324, Si 5326, Si5327, Si5368, Si5369, Si5374, Si5375 ) T o facilitate automatic hitless switching, the LOS trigger time can be signi ficantly reduced by us ing the default LOS option (LOSn_EN = 1 1). The LOS circuitry divides down ea ch input clock to pr oduce a 2 kHz to 2 MHz signal. The LO[...]

Si53xx-RM 98 Rev. 0.5 Both the FOS re ferenc e and the F OS monit ored clock m ust be divided down to the same clock rate and this clock rate must be be twe en 1 0 MH z a nd 27 MHz. As ca n b e see n in Fi gu re 33 , th e va lu es for P an d Q m ust be selec ted so that the FOS comparison occurs at the same frequen cy . The registers that cont ain [...]

Si53xx-RM Rev. 0.5 99 7.1 1.3. C1B, C2B (Si5319, Si5324, Si 5325, Si5326, Si5327 , Si5 37 4 , Si53 75 ) A LOS condition causes the associated LOS1_INT or LOS2_INT read only register bit to b e set. A LOS condition on CKIN_1 will also be reflected onto C1B if CK1_BAD_PIN = 1. Likewise, a LOS condition on C KIN_2 will also be reflected onto C2B if CK[...]

Si53xx-RM 100 Rev. 0.5 7.1 1.6. C1B, C2B, C3B, ALRM OUT (Si5368 [CK_CONFIG_REG = 1]) The generation of ala rms on the C1B, C2B, C3B, and ALRMOUT output s is a function of the input clock configuration, and th e frequency offset alar m enable as shown in T able 53. The LOSn_INT and FOSn_INT signals are the raw outp uts of the alarm monitors. These a[...]

Si53xx-RM Rev. 0.5 101 7.1 1.9. Device Interrupts Alarms on internal real-time st atus bit s such as LOS1_I NT , FOS1_INT , etc. cause their associated interrupt f lags ( LOS1_FLG , FOS1_FLG , et c.) to be set and held. The inte rrupt flag bits can be individually maske d or unmasked with respect to the output in terrupt pin. Once an in terrupt fla[...]

Si53xx-RM 102 Rev. 0.5 7.13. I 2 C Serial Microprocessor Interface When configured in I 2 C co ntrol mode (CMODE = L), the control interface to the device is a 2-wire bus for bidirectional communication . The bus consists of a bidire ctional serial data line (SDA) and a serial clock in put (SCL). Both lines must be connected to the positive supply [...]

Si53xx-RM Rev. 0.5 103 7.14. Serial Microprocessor Interface (SPI) When configured in SPI control mode (CMODE = H), the co ntro l interface to the de vice is a 4-wire inter face modeled af ter commonly available micr ocontroller and serial peripheral devices. The inte rface consists of a clock input (SCLK), slave se lect input (SSb), serial d ata i[...]

Si53xx-RM 104 Rev. 0.5 Figure 36. SPI Write/Set Address Command Figure 37. SPI Read Command 7.14.1. Default Device Configuration For ease of manufacture and b ench testing of the device, the default register settin gs have been chosen to place the device in a fully-f unctio nal mode with an easily-obser vable output clock. Refer to the dat a sheet [...]

Si53xx-RM Rev. 0.5 105 8. High-S peed I/O 8.1. Input Clock Buffers Any-Frequency Precision Clock device s provide dif ferential input s for the CKINn clock input s. These inputs are internally biased to a common mode volt age and can be driven by either a single- ended or dif ferential source. Figure 38 through Figure 41 show typical interface circ[...]

Si53xx-RM 106 Rev. 0.5 Figure 40. CML/L VDS T ermination (1.8, 2.5, 3.3 V) Figure 41. CMOS T ermination (1.8, 2.5 , 3.3 V) 40 k C C ± CKIN _ CKIN + V ICM 300 100 Si53xx CML/ LVDS Driver    40 k  V DD V DD V DD CMOS Driv er R1 33 ohms 50 R2 See Table R3 150 ohms C1 100 nF R4 150 ohms C2 100 nF V ICM CKI N+ CKIN– R5 40 koh m R6 40 koh [...]

Si53xx-RM Rev. 0.5 107 8.2. Output Clock Drivers The output clocks can be conf igured to be compatible with L VPECL, CML, L VDS, or CMOS as shown in T able 56. Unused output s can be lef t unconnecte d. For micropro cessor-controlled devices, it is recommended to write “disable” to SFOUTn to disa ble the output buf fer and reduce power . When t[...]

Si53xx-RM 108 Rev. 0.5 Figure 43. Differential Output Example Requiring Attenuation Figure 44. T ypical CMOS Output Circuit (T ie CKOUTn+ and CKOUTn– T ogether) Unused output drivers should be powe red down, per T able 57, or left floating. The pin-controlled p arts ha ve a DBL2_BY pin that can be used to disable CKOUT2. T able 57. Disa bling Unu[...]

Si53xx-RM Rev. 0.5 109 Figure 45. CKOUT Structure 8.2.3. T ypica l Clock Outp ut Scope Shot s T able 58. Output Format Measurement s 1,2 Name SFOUT Pin SFOUT Code Single Vpk–pk Diff Vpk–pk Vo c m R e s e r v e d H H ———— LV D S H M 7 . 3 5 . 7 1 . 2 CML HLK 6 .25 .5 3.05 L VPECL MH 5 .75 1.5 2.10 Reserved MM 4 — — — Low Swing L VD[...]

Si53xx-RM 110 Rev. 0.5 8.3. T ypical Scope Shot s for SFOUT Options Figure 46. sfout_2, CMOS Figure 47. sfout_3, lowSwingL VDS[...]

Si53xx-RM Rev. 0.5 111 Figure 48. sfout_5, L VPECL Figure 49. sfout_6, CML[...]

Si53xx-RM 112 Rev. 0.5 Figure 50. sfout_7, L VDS[...]

Si53xx-RM Rev. 0.5 113 8.4. Cryst al/Reference Clock Interfaces (Si5 316, Si5319, Si 5323, Si5324, Si5326, Si5327, Si5366, Si5368, Si5369 , Si5374, and Si5375) All devices other than the Si5 374 and Si5375 can use an ex ternal crystal or extern al clock as a reference. T he Si5374 and Si5375 are limited to an external refe rence oscillator and cann[...]

Si53xx-RM 114 Rev. 0.5 Figure 53. Differential External Reference Input Exampl e (Not for Si5374 or Si5375) Figure 54. Differential OSC Reference Input Example for Si5374 and Si5375 LVDS, LVPECL, CML, et c. 0.01  F 1.2 V 0.6 V Si53xx XA  XB 10 k  100 0.01  F 10 k  LVDS, LVPECL, CML, et c. 0.01  F 1.2 V 0.6 V Si5374/75 OSC-P OSC-N [...]

Si53xx-RM Rev. 0.5 115 8.5. Three-Level (3 L) Input Pins (No External Resistors) Figure 55. Three Level Input Pins Parameter Symbol Min Max Input V oltage Low Vill — .15 x V DD Input V oltage Mid Vimm .45 x Vdd .55 x V DD Input V oltage High Vihh .85 x Vdd — Input Low Current Iill –6 µA — Input Mid Current Iimm –2 µA 2 µA Input High Cu[...]

Si53xx-RM 116 Rev. 0.5 8.6. Three-Level (3 L) Input Pins (With External Resistors) Figure 56. Three Level Input Pins  Any resist or pack may be used.  The Panasonic EXB-D10C183J is an example.  PCB layout is not critical.  Resistor packs are on ly needed if the leakage current of the external driver exce eds the listed current s. [...]

Si53xx-RM Rev. 0.5 117 9. Power Supply These devices incorporate an on-chip voltage regulator to po wer the device from su pply voltages o f 1.8, 2.5, or 3.3 V . Intern al core circuitry is driven from the output of this regulator while I/O circuitry uses the ext ernal supply voltage directly . Figure 57 shows a typical power supply bypass networ k[...]

Si53xx-RM 118 Rev. 0.5 10. Packages and Ordering Guide Refer to the respective dat a sheet for your device pa ckaging and ordering infor mation.[...]

Si53xx-RM Rev. 0.5 119 A PPENDIX A—N ARROWBAND R EFERENCES Resonator/External Clock Selection T able 59 shows the 1 14.285 MHz third overtone crystals that have been approve d for use with the Si53xx jitter attenuating clocks. In some applications, a crystal wi th frequencies other than 1 14.285 MHz ma y be us ed. Contact Silicon Labs for details[...]

Si53xx-RM 120 Rev. 0.5 Fundamental Mode Cryst als For cost sensitive applications that do not have the most demanding jitter requir ements, all of the narrow band devices can use fundament al mode crystals that are in the lowest fr equency band ranging fr om 37 to 41 MHz (corresponding to RA TE = LL). Unlike the other narrowband memb ers of the fam[...]

Si53xx-RM Rev. 0.5 121 A PPENDIX B—F REQUENCY P LANS AND J ITTER P ERFORMANC E (Si5316, Si5319, Si5323, S I 5324, Si5326, Si5327, Si5366, Si5368, Si 5369, Si5374, Si5375) Introduction To achieve the best jitter performance from Narrowban d Any-Frequency Clock devices, a few general guidelines should be observed: High f3 V alue f3 is defined as th[...]

Si53xx-RM 122 Rev. 0.5 Figure 61 shows similar results and ties them to RMS jitter values. It also help s to illustrate one potential remedy for solutions with low f3. Note th at 38.88 MHz x 5 = 194. 4 MHz. In this case, an FPGA was used to multiply a 38.88 M Hz input clock up by a factor of five to 194.4 M Hz, using a feature such as the Xilinx DC[...]

Si53xx-RM Rev. 0.5 123 Reference vs. Output Frequency Because of internal coupling, outpu t frequencies that are an integer multiple (or close to an integer multiple) of the XA/XB reference frequency (eit her internal or external) sh ould be avoided. Figure 62 illu strates this by showing a 38.88 MHz reference being used to gen erate both a 622.08 [...]

Si53xx-RM 124 Rev. 0.5 High Reference Frequency When selecting a refer ence frequency , with all other things being equ al, the higher the refere nce frequency , the lower the output jitter . Figure s 63 and 64 illustrate this. For a discussion of the available refer ence frequencies, see section " Resonator/External Cl ock Selection" on [...]

Si53xx-RM Rev. 0.5 125 Figure 64. Jitter vs. Reference Frequency (2 of 2) All phase noise numbers ar e in fs, RMS External Referenc e Frequency: 37 41 55 61 109 12 5.5 163 180 Jitter Bandwid th: MHz MHz MHz MHz MHz MHz MHz MHz SONET_OC48, 12 kH z to 20 MHz 1092 858 633 715 330 321 292 298 SONET_OC192_A, 20 kHz to 80 MHz 1086 855 639 698 356 335 325[...]

Si53xx-RM 126 Rev. 0.5 A PPENDIX C—T YPICAL P HASE N OISE P LOT S Introduction The following are some typical phase noise plot s. The cl ock inp ut source is a Rohde and Schwarz mo del SML03 RF Generator . Except as noted, the ph ase noise analysis eq uipment is the Ag ilent E50 52B. Also (except as noted), the Any-Frequency par t was an Si5326 o[...]

Si53xx-RM Rev. 0.5 127 Figure 66. 155.52 MHz In; 622.08 MHz Out; Loop BW = 7 Hz, Si5324[...]

Si53xx-RM 128 Rev. 0.5 Figure 67. 19.44 MHz In; 156.25 MHz Out; Loop BW = 80 Hz[...]

Si53xx-RM Rev. 0.5 129 Figure 68. 19.44 MHz In; 156.25 MHz Out; Loop BW = 5 Hz, Si5324[...]

Si53xx-RM 130 Rev. 0.5 Figure 69. 27 MHz In; 148.35 MHz Out; Light T race BW = 6 Hz; Dark T race BW = 1 10 Hz, Si5324[...]

Si53xx-RM Rev. 0.5 131 Figure 70. 61.44 MHz In; 491.52 MHz Out; Loop BW = 7 Hz, Si5324[...]

Si53xx-RM 132 Rev. 0.5 Figure 71. 622.08 MHz In; 672.16 MHz Out; Loop BW = 6.9 kHz[...]

Si53xx-RM Rev. 0.5 133 Figure 72. 622.08 MHz In; 672.16 MHz Out; Loop BW = 100 Hz[...]

Si53xx-RM 134 Rev. 0.5 Figure 73. 156.25 MHz In; 155.52 MHz Out[...]

Si53xx-RM Rev. 0.5 135 Figure 74. 78.125 MHz In; 644.531 MHz Out T able 63. Jitter V alues for Figure 74 Jitter Bandwid th 644.531 MHz Jitter (RMS) Broadband, 1 kHz to 10 MHz 223 fs OC-48, 12 kHz to 20 MHz 246 fs OC-192, 20 kHz to 80 MHz 244 fs OC-192, 4 MHz to 80 MHz 120 fs OC-192, 50 kHz to 80 MHz 234 fs Broadband, 800 Hz to 80 MHz 248 fs[...]

Si53xx-RM 136 Rev. 0.5 Figure 75. 78.125 MHz In; 690.569 MHz Out T able 64. Jitter V al ues for Figure 75 Jitter Bandwid th 690.569 MHz Jitter (RMS) Broadband, 1 kHz to 10 MHz 244 fs OC-48, 12 kHz to 20 MHz 260 fs OC-192, 20 kHz to 80 MHz 261 fs OC-192, 4 MHz to 80 MHz 120 fs OC-192, 50 kHz to 80 MHz 253 fs Broadband, 800 Hz to 80 MHz 266 fs[...]

Si53xx-RM Rev. 0.5 137 Figure 76. 78.125 MHz In; 693.493 MHz Out T able 65. Jitter V al ues for Figure 76 Jitter Bandwid th 693.493 MHz Jitter (RMS) Broadband, 1 kHz to 10 MHz 243 fs OC-48, 12 kHz to 20 MHz 265 fs OC-192, 20 kHz to 80 MHz 264 fs OC-192, 4 MHz to 80 MHz 124 fs OC-192, 50 kHz to 80 MHz 255 fs Broadband, 800 Hz to 80 MHz 269 fs[...]

Si53xx-RM 138 Rev. 0.5 Figure 77. 86.685 MHz In; 173.371 MHz and 693.493 MHz Out T able 66. Jitter V al ues for Figure 77 Jitter Bandwid th 173.371 MHz Jitter (RMS) 693.493 MHz Jitter (RMS) Broadband, 1 kHz to 10 MHz 26 2 fs 243 fs OC-48, 12 kHz to 20 MHz 297 fs 265 fs OC-192, 20 kHz to 80 MHz 309 fs 264 fs OC-192, 4 MHz to 80 MHz 196 fs 124 fs OC-[...]

Si53xx-RM Rev. 0.5 139 Figure 78. 86.685 MHz In; 173.371 MHz Out[...]

Si53xx-RM 140 Rev. 0.5 Figure 79. 86.685 MHz In; 693.493 MHz Out[...]

Si53xx-RM Rev. 0.5 141 Figure 80. 155.52 MHz and 156.25 MHz In; 622.08 MHz Out T able 67. Jitter V al ues for Figure 80 Jitter Bandwid th 155.52 MHz Input Jitter (RMS) 156.25 MHz Input Jitter (RMS ) Broadband, 100 Hz to 10 MHz 4432 fs 4507 fs OC-48, 12 kHz to 20 MHz 249 fs 251 fs OC-192, 20 kHz to 80 MHz 274 fs 271 fs OC-192, 4 M Hz to 80 MHz 166 f[...]

Si53xx-RM 142 Rev. 0.5 Figure 81. 10 MHz In; 1 GHz Out[...]

Si53xx-RM Rev. 0.5 143 Digit al Video (HD-SDI) Phase noise equip ment: Agilent model JS50 0. Jitter Band Jitter Brick W all, 10 Hz to 20 MHz 2.42 ps, RMS Peak-to-pe ak 14.0 ps 27 M Hz i n, 148. 5 M H z out -160 -140 -120 -100 -80 -60 -40 -20 0 10 100 1000 10000 1000 00 10 00000 10000000 100 000000 Of f s e t Fre que nc y ( Hz) P h ase No i se (dBc/[...]

Si53xx-RM 144 Rev. 0.5 A PPENDIX D—A LARM S TRUCTURE Figure 82. Si5324 and Si5326 Alarm Diagram in out Sticky Write 0 to clear LOS_IN T LOSX_FLG LOSX_MSK in out Sticky Write 0 to clear LOL_I NT LOL_FLG LOL_MSK in out Sticky Write 0 to clear FOS2_INT FOS2_FLG FOS2_M SK in out Sticky Write 0 to clear FOS1_INT FOS1_FLG FOS1_M SK in out Sticky Write [...]

Si53xx-RM Rev. 0.5 145 Figure 83. Si5368 Alarm Diagram (1 of 2) in out Sticky Write 0 to clear LOS_INT LOSX_FLG LOSX_MSK in out Sticky Write 0 to clear LOL_INT LOL_FLG LOL_MSK in out Sticky Write 0 to clear FOS4_INT FOS4_FLG FOS4_MSK in out Sticky Write 0 to clear FOS3_INT FOS3_FLG FOS3_MSK in out Sticky Write 0 to clear FOS2_INT FOS2_FLG FOS2_MSK [...]

Si53xx-RM 146 Rev. 0.5 Figure 84. Si5368 Alarm Diagram (2 of 2) LOS Detector FOS Detector FOS3_EN LOS3_EN LOS3_IN T C3B E CK_BAD_POL LOS Detector FOS Detector FOSI_EN LOSI_EN LOS1_INT C1B E 1 0 LOS Detector FOS Detector FOS2_EN LOS2_EN LOS2_INT C2B E 1 0 LOS4_INT CK_CONFIG_REG FSYNC_SWTCH_REG CK3_BAD_PIN CK_CONFIG_REG CK1_BAD_PIN CK2_BAD_PIN CKIN2 [...]

Si53xx-RM Rev. 0.5 147 A PPENDIX E—I NTERNAL P ULLUP , P ULLDOWN BY P IN T ables 68–79 sh ow which 2-Level CMOS pins ha ve pullups or pulldowns. Note the valu e of the pullup/pulldo wn resistor is typically 75 k  . T able 68. Si5316 Pullup/Down Pin # Si5316 Pull? 1 RST U 11 RA TE0 U, D 14 DBL2_BY U, D 15 RA TE1 U, D 21 CS U, D 22 BWSEL0 U, D[...]

Si53xx-RM 148 Rev. 0.5 T able 70. Si5323 Pullup/Down Pin # Si5323 Pull? 1R S T U 2F R Q T B L U , D 9 AUTOSEL U, D 11 R AT E 0 U , D 14 DBL2_BY U, D 15 RA TE 1 U, D 19 DEC D 20 INC D 21 CS_CA U, D 22 BWSEL0 U, D 23 BWSEL1 U, D 24 FRQSEL0 U, D 25 FRQSEL1 U, D 26 FRQSEL2 U, D 27 FRQSEL3 U, D 30 SF OUT1 U, D 33 SF OUT0 U, D T able 71. Si531 9, Si5324,[...]

Si53xx-RM Rev. 0.5 149 T able 72. Si5325 Pullup/Down Pin # Si5325 Pull? 1R S T U 21 CS_CA U, D 22 SCL D 24 A0 D 25 A1 D 26 A2_SS D 27 SDI D 36 CMODE U, D T able 73. Si5326 Pullup/Down Pin # Si5326 Pull? 1R S T U 11 R AT E 0 U , D 15 RA TE 1 U, D 19 DEC D 20 INC D 21 CS_CA U, D 22 SCL D 24 A0 D 25 A1 D 26 A2_SS D 27 SDI D 36 CMODE U, D[...]

Si53xx-RM 150 Rev. 0.5 T able 74. Si5327 Pullup/Down Pin # Si5327 Pull? 1R S T U 11 R AT E 0 U , D 15 RA TE 1 U, D 21 C S U, D 22 SCL D 24 A0 D 25 A1 D 26 A2_SS D 27 SDI D 36 CMODE U, D T able 75. Si536 5 Pullup/Down Pin # Si5365 Pull? 3R S T U 4F R Q T B L U , D 13 CS0_C3A D 22 AUT OSEL U, D 37 DBL2_BY U, D 50 DSBL5 U, D 57 CS1_C 4A U, D 60 BWSEL0[...]

Si53xx-RM Rev. 0.5 151 T able 76. Si5366 Pullup/Down Pin # Si5366 Pull? 3R S T U 4F R Q T B L U , D 13 CS0_C3A D 20 FS_SW D 21 FS_ALIGN D 22 AUT OSEL U, D 32 RA TE 0 U, D 37 DBL2_BY U, D 42 RA TE 1 U, D 50 DBL_F S U, D 51 CK_CONF D 54 DEC D 55 INC D 56 F OS_CTL U, D 57 CS1_C 4A U, D 60 BWSEL0 U, D 61 BWSEL1 U, D 66 DIV 34_0 U, D 67 DIV 34_1 U, D 68[...]

Si53xx-RM 152 Rev. 0.5 T able 77. Si5367 Pullup/Down Pin # Si5367 Pull? 3R S T U 13 CS0_C3A D 57 CS1_C 4A U, D 60 SCL D 68 A0 D 69 A1 D 70 A2_SSB D 71 SDI D 90 CMODE U, D T able 78. Si5368 Pullup/Down Pin # Si5368 Pull? 3R S T U 13 CS0_C3A D 21 FS_ALIGN D 32 RA TE 0 U, D 42 RA TE 1 U, D 54 DEC D 55 INC D 57 CS1_C 4A U, D 60 SCL D 68 A0 D 69 A1 D 70[...]

Si53xx-RM Rev. 0.5 153 T able 79. Si5369 Pullup/Down Pin # Si5368 Pull? 3R S T U 13 CS0_C3A D 21 FS_ALIGN D 32 RA TE 0 U, D 42 RA TE 1 U, D 57 CS1_C 4A U, D 60 SCL D 68 A0 D 69 A1 D 70 A2_SSB D 71 SDI D 90 CMODE U, D T able 80 . Si5374/75 Pullup/Down Pin # Si5374/75 Pull? D4 RSTL_A U D6 RSTL_B U F6 RSTL_C U F4 RSTL_D U D1 CS_CA_A U/D A6 CS_CA_ B U/[...]

Si53xx-RM 154 Rev. 0.5 A PPENDIX F—T YPICAL P ERFORMANCE : B YP ASS M ODE , PSRR, C ROSST ALK , O UTPUT F ORMAT J ITTER This appendix is divided into the following four sections:  Bypass Mode Per formance  Power Supply Noise Rejection  Crosstalk  Output Format Jitter Byp ass: 622.08 MHz In, 622.08 MHz Out Normal, Locked In Digit al Ho[...]

Si53xx-RM Rev. 0.5 155 Power Supply Noise Rejection P o we r Su ppl y N oise t o Output T ran sfe r Func t ion -1 0 5 -1 0 0 -9 5 -9 0 -8 5 -8 0 -7 5 -7 0 -6 5 -6 0 1 10 100 10 00 kHz dB 38.88 MHz in, 155.52 MHz ou t; Bandwidth = 1 10 Hz[...]

Si53xx-RM 156 Rev. 0.5 Clock Input Crosstalk Result s: T est Co nditions Jitter Ban d 155. 52 MHz in, 622 MHz out, For reference, No crosstalk 155.521 M Hz in, 622.084 MHz out, No crosst alk 155.521 MHz in, 622.084 MHz out, 155.52 MHz Xt alk, 99 Hz loop Bandwidth 155.521 MHz in, 622.084 MHz out, 155.52 MHz Xtalk, 6.72 kHz loop Bandwid th 155.521 MH[...]

Si53xx-RM Rev. 0.5 157 Clock Input Crosst alk: Phase Noise Plot s Dark blue — No crosst alk Light blue — With cros st a lk, low bandwid th Y ellow — With crosst alk, high bandwidt h Red — With crosst alk, in digit al hold 15 5. 5 21 M H z i n, 622 . 08 4 M H z out -18 0 -16 0 -14 0 -12 0 -10 0 -8 0 -6 0 -4 0 -2 0 0 10 0 1 000 10000 100 000 [...]

Si53xx-RM 158 Rev. 0.5 Clock Input Crosst alk: Det ail View Dark blue — No crosst alk Light blue — With cros st a lk, low bandwid th Y ellow — With crosst alk, high bandwidt h Red — With crosst alk, in digit al hold 155 . 521 M H z i n , 622 . 084 M H z ou t -1 3 0 -1 2 0 -1 1 0 -1 0 0 -9 0 -8 0 -7 0 -6 0 100 1000 1 0000 100000 Of f s e t F[...]

Si53xx-RM Rev. 0.5 159 Clock Input Crosst alk: Wide band Comp arison Jitter Band Jitter , w/ Xtlk Jitter , no Xtlk OC-48, 12 kHz to 20 MHz 303 fs RMS 422 fs RMS OC-192, 20 kHz to 80 MHz 316 fs RMS 366 fs RMS Broadband, 800 Hz to 80 MHz 3 40 fs RMS 1,010 fs RMS 155 .521 M H z in , 62 2. 08 4 M H z o u t - 180 - 160 - 140 - 120 - 100 -8 0 -6 0 -4 0 -[...]

Si53xx-RM 160 Rev. 0.5 Clock Input Crosst alk: Output of Rohde and Sc hwartz RF R ohde a nd S c hwa r z : 15 5 .5 2 1 M H z - 120 - 110 - 100 -9 0 -8 0 -7 0 -6 0 10 0 100 0 O ffs e t F r e q u e n c y (H z ) P h a se Noi s e ( d Bc / H[...]

Si53xx-RM Rev. 0.5 161 Jitter vs. Output Format: 19.44 MHz In, 622.08 MHz Out S pectrum Analyzer: Agilent Model E444OA T able 81. Out put Format vs. Jitter Bandwid th L VPECL Jitter (RMS) L VDS Jitter (RMS) CML Jitter (RMS) Low Swing L VDS Jitter (RMS) Broadband, 1 kHz to 10 MHz 282 fs 269 fs 257 fs 261 fs OC-48, 12 kHz to 20 MHz 297 fs 289 fs 290 [...]

Si53xx-RM 162 Rev. 0.5 A PPENDIX G—N EAR I NTEGER R ATIOS T o provide more d etails and to provide boundarie s with respect to the “Referen ce vs. Output Frequency” issue described in Append ix B on page 121, the following stu dy was performed and is presen ted below . T est Conditions  XA/XB External Reference held const ant at 38.88 MHz [...]

Si53xx-RM Rev. 0.5 163 Figure 86. ±200 ppm, 10 ppm Step s Figure 87. ±2000 ppm, 50 ppm Step s 3 8 .8 8 M Hz Exte r na l XA -XB Re fe r e n c e 0 200 400 600 800 1000 1200 155. 49 155. 5 155. 51 155. 52 155. 53 155. 54 155. 55 I nput Fre que nc y ( M H z ) RM S j i tter , fs Input Frequency 3 8 .8 8 M Hz Ex te rna l XA -XB R e fe re n c e 0 200 40[...]

Si53xx-RM 164 Rev. 0.5 A PPENDIX H—J ITTER A TTENUATION AND L OOP BW The following illustrates the effects of dif ferent loop BW values on the jitter attenuation of the Any-Frequency devices. Th e jitter cons ists of sine wave m odulation a t va rying frequencies. The RM S jitter value s of the modulated sine wave input is comp ared to the o utpu[...]

Si53xx-RM Rev. 0.5 165 Figure 88. RF Generator , Si5326, Si 5324; No Jitter (For Reference) Figure 89. RF Generator , Si5326, Si5324 (50 Hz Jitter) 622. 08 M Hz i n, 622. 08 M H z out -1. 80E + 02 -1. 60E + 02 -1. 40E + 02 -1. 20E + 02 -1. 00E + 02 -8. 00E + 01 -6. 00E + 01 -4. 00E + 01 -2. 00E + 01 0. 00E + 00 1. 00E + 01 1. 00E + 02 1. 00E+ 03 1.[...]

Si53xx-RM 166 Rev. 0.5 Figure 90. RF Generator , Si5326, Si5324 (100 Hz Jitter) Figure 91. RF Generator , Si5326, Si5324 (500 Hz Jitter) 622. 08 M Hz i n, 622. 08 M H z out -1. 80E + 02 -1. 60E + 02 -1. 40E + 02 -1. 20E + 02 -1. 00E + 02 -8. 00E + 01 -6. 00E + 01 -4. 00E + 01 -2. 00E + 01 0. 00E + 00 1. 00E + 01 1. 00E + 02 1. 00E + 03 1. 00E + 04 [...]

Si53xx-RM Rev. 0.5 167 Figure 92. RF Generator , Si5326, Si5324 (1 kHz Jitter) Figure 93. RF Generator , Si5326, Si5324 (5 kHz Jitter) 622. 08 M Hz i n, 622. 08 M H z out -1. 80E + 02 -1. 60E + 02 -1. 40E + 02 -1. 20E + 02 -1. 00E + 02 -8. 00E + 01 -6. 00E + 01 -4. 00E + 01 -2. 00E + 01 0. 00E + 00 1. 00E + 02 1. 00E + 03 1. 00E + 04 1. 00E + 05 1.[...]

Si53xx-RM 168 Rev. 0.5 Figure 94. RF Generator , Si5326, Si5324 (10 kHz Jitter) 622. 08 M Hz i n, 622. 08 M H z out -1. 80E + 02 -1. 60E + 02 -1. 40E + 02 -1. 20E + 02 -1. 00E + 02 -8. 00E + 01 -6. 00E + 01 -4. 00E + 01 -2. 00E + 01 0. 00E + 00 1. 00E + 02 1. 00E + 03 1. 00E + 04 1. 00E + 05 1. 00E+ 06 1. 00E + 07 1. 00E + 08 Of fs e t Fre que ncy [...]

Si53xx-RM Rev. 0.5 169 A PPENDIX I—Si5374 AND Si5375 PCB L AYOUT R ECOMMENDATIONS The following is a set of recom mendations and guidelines fo r printed circuit boar d layout with the Si5374 and Si5374 devices. Beca use the four DSPLLs are in close phys ical and electrica l proximity to one another , PCB layout is critical to achieving the highes[...]

Si53xx-RM 170 Rev. 0.5 Figure 96. Ground Plane and Reset These  fou r  re si s to rs  force  the  common  RE S ET  conne cti on  away  fr om  th e  BGA  foo t pri nt[...]

Si53xx-RM Rev. 0.5 171 The following is a set of recom mendations and guidelines fo r printed circuit boar d layout with the Si5374 and Si5374 devices. Beca use the four DSPLLs are in close phys ical and electrica l proximity to one another , PCB layout is critical to achieving the highest levels of jitter perfo rmance. The follow ing images were t[...]

Si53xx-RM 172 Rev. 0.5 Figure 98. OSC_P , O SC_N Rout ing OSC_P , OSC_N Av o id  placi ng  the  OCS_ P  and  OSC _N  sign a ls  on  the  sa m e  la yer  as  th e  cl ock  out put s .  Ad d  gr ounde d  gua r d  tra ces  sur r oundi ng  th e  OSC_P  and  OSC_ N  sig n a ls.[...]

Si53xx-RM Rev. 0.5 173 A PPENDIX J—Si5374 AND Si5375 C ROSST ALK While the four DSPLLs of the Si537 4 and Si5375 are in close physical an d electrical proximity to on e another , crosstalk interfer ence between the DSPLL s is minimal. The following measurement s show typical performan ce levels that can be expected for the Si5 374 and Si5375 when[...]

Si53xx-RM 174 Rev. 0.5 Figure 99. Si5374, Si5375 DSPLL A[...]

Si53xx-RM Rev. 0.5 175 Figure 100. Si5374, Si5375 DSPLL B[...]

Si53xx-RM 176 Rev. 0.5 Figure 101. Si5374, Si5375 DSPLL C[...]

Si53xx-RM Rev. 0.5 177 Figure 102. Si5374, Si5375 DSPLL D[...]

Si53xx-RM 178 Rev. 0.5 D OCUMENT C HANGE L IST Revision 0.3 to Revision 0.4  Updated AC S pecifications in T able 8, “AC Characteristics—All Devices”  Added Si5365, Si5366, Si53 67, and Si5368 operation at 3.3 V  Updated Section “7 .8 . Fr am e Synch ro niz at ion Realignment (Si5368 and CK_CONFIG_REG = 1)”  Added input clock [...]

Si53xx-RM Rev. 0.5 179 N OTES :[...]

Si53xx-RM 180 Rev. 0.5 C ONT ACT I NFORMATION Silicon La boratories Inc. 400 West Cesar Chavez Austin, TX 78701 T el: 1+(512) 416-8 500 Fax: 1+(512) 416 -9669 T oll Free: 1 +(877) 444-3032 Please visit the Silico n Labs T echnical Supp ort web page: https://www .silabs.com/support/pages/contacttechnicalsupport .aspx and register to submit a tech ni[...]