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Silicon Laboratories CP2112-EK manual

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Table of contents for the manual

  • Page 1

    Rev. 0.2 9/10 Copyright © 2010 by Silicon Labo rato ries CP2112-EK CP21 12-EK CP21 12 E VALUATION K IT U SER ’ S G UIDE 1. Kit Content s The CP21 12 Evaluation Kit contains the following items:  CP21 12 Evaluation Board  CP21 12 Product Information CD-ROM. CD contents include:  Example Windows and Mac Application s  Documentati[...]

  • Page 2

    CP21 12-EK 2 Rev. 0.2 4. CP21 12 Windows Application The HIDSMBus Example application us es the Windows CP21 12 HID-to-SMBus DLL to tr ansmit and receive dat a with the CP21 12. The application also has access to the CP21 12’s GPIO pins. Th e HIDSMBus Exam ple application is installed as part of the CD inst allation process. Figure 2 shows a scre[...]

  • Page 3

    CP21 12-EK Rev. 0.2 3 6. Figure 3 shows the Data T ransfer tab, which allows you to transfer read and write dat a over the SMBus. 7. T o Read dat a from an SMBus device (non-addre ssed mode): a. Enter the slave address in the “Read Requ est” box and the number of bytes to read. After this, click “Read Request” (shown in red). b. T o see the[...]

  • Page 4

    CP21 12-EK 4 Rev. 0.2 10. Figure 4 shows the Pin Configuration t ab, which a llows you to configure the GPIO and S pecial Functions (TX T oggle, RX T oggle , and Clock Output). a. GPIO pins toggle between Input/Ouput and Open-Drai n/Push-Pull by clicking the corresponding GPIO b oxes in the “GPIO Configuration” section. The boxes fo r TX T oggl[...]

  • Page 5

    CP21 12-EK Rev. 0.2 5 1 1 . Figure 5 shows the Customization t ab, which allows you to program the One-T ime-Programmable (OTP) paramete rs of th e device. The parameters that ar e programmed with this tab can only be pro gr ammed once and cannot be ch anged back to their default va lues after being programmed. This t ab has the same functionality [...]

  • Page 6

    CP21 12-EK 6 Rev. 0.2 5. T arget Board The CP21 12 Evaluation Kit includes an evaluation boar d with a CP21 12 device pre-inst alled for evaluation and preliminary software de velopment. Numerous in put/output (I/O) connecti ons are provided to facilitate prototyping using the evaluation board. Refer to Figure 6 for the loca tions of the various I/[...]

  • Page 7

    CP21 12-EK Rev. 0.2 7 5.2. Universal Serial Bus (USB) Interface (P1) A Universal Serial Bus (USB) connector (P1) is provided to facilitate connections to the USB interface on the CP21 12. See T able 2 for the USB pin definitions. 5.3. SMBus Signals (TB1, H1) The SMBus interface ter minal block and access headers a re included to easily intera ce SM[...]

  • Page 8

    CP21 12-EK 8 Rev. 0.2 6. Schematic Figure 7. C P21 12 Evaluation Board Schematic[...]

  • Page 9

    CP21 12-EK Rev. 0.2 9 D OCUMENT C HANGE L IST Revision 0.1 to Revision 0.2  Updated Figu re 1.  Updated "4. CP21 12 Windows Application" on page 2.  Instructions and figures from updated PC application  Updated Figu re 7 on page 8.[...]

  • Page 10

    CP21 12-EK 10 Rev. 0.2 C ONT ACT I NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 T el: 1+(512) 416-8500 Fax: 1+(512) 416-9669 T oll Free: 1+(877) 4 44-3032 Please visit the Silicon Labs T echn ical Support web page: https://www .silabs.com/su pport/pages/contacttechnicalsupport.aspx and register to submit a technical s[...]