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Interphase Tech 4221 manual

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Table of contents for the manual

  • Page 1

    V/Ethernet 4221 Cond or User’ s Guide Document No. UG04221-000, REVB Release date: July 1994 Copyri ght 1994 Inte rpha se Corp ora tion All Rights Reserved[...]

  • Page 2

    [...]

  • Page 3

    Copyright Notice Copyright 1993, 1994 b y Interphase Corporation All rights reserved No part of this publication may be stored in a retriev al system, transmitted, or reproduced in any way , including, but not limited to photocopy , photograph, electronic, or mechanical, with out prior written permissio n of: Interphase Corporation 13800 Senlac Dal[...]

  • Page 4

    F or Assistance T o place an o rder for an I nterphase product, call: Sales S upport: (214) 919 -9000 For ass istance using this, or any other Interphase pro duct, call: Cus tomer Servi ce: (2 14) 91 9-900 0 United K ingdom: +44 -869-3212 22 T o sen d in a board for r epair or upgrade, call: RMA C oordi nato r: (2 14) 91 9-90 00 T rademark Ackno wl[...]

  • Page 5

    T ABLE OF CONTENTS vi CHAPTER 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Intended Aud ience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

  • Page 6

    vii Command Respons e Block (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Command Respons e Status Word (CRSW ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Command Tag. . . . . . . . . . . . . . . . . . . . . . . . .[...]

  • Page 7

    viii MAC status/contr ol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Intel 82596 Status/C ontrol – Transmit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Intel 82596 Status/C ontrol – Receive Functions . . . . [...]

  • Page 8

    ix Operating Enviro nment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Fuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Reliabili[...]

  • Page 9

    LIST OF FIGURES xii Figure 1-1. 4221 Co ndor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2-1. 10BaseT Cond or Motherboard Layo ut (PB04221- 000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2-2. Single Channel AUI or 10 BaseT Motherboard L ayout (PB[...]

  • Page 10

    xiii[...]

  • Page 11

    LIST OF T ABLES xiv Table 2-1. Condor Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2-2. 4221 Co ndor LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2-3. Board Status Diagnos tics[...]

  • Page 12

    xv Table 3-36. Report Network Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 3-37. Command Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 3-38. Network Statistics Block . . . . . . . . . . . .[...]

  • Page 13

    1 CHAPTER 1 INTRODUCTION Intended Audience Interphase wrote this manual for its customer s. It is intended for a highly tech nical audience, specifi cally , users who need to write their own so ftware dri ver s. Readers are assumed to hav e extens iv e knowled ge of the following: • The C programming language, including experience writing and ins[...]

  • Page 14

    Chapter 1 - Intr oduction 2 Conventions This section detail s many of the wri ting con ventions used throu ghout the manual. In addition, it giv es many of the technical con ventions. • The V/Ethernet 4221 Condor will be referred to by the nam e Condor or referenced as the controller . • Byte represen ts 8 bits ; word re presents 16 bits (2 byt[...]

  • Page 15

    Options 3 Options Interph ase Corpor ation of fers the followi ng Condor o ptions: • Dual Channel Ethernet (AUI) • Dual Channel Ethernet (1 0BaseT) • 3 Channel Ethernet ( AUI or 10BaseT) • Quad Ethernet Channe l (AUI or 10Bas eT) Physical Description The Cond or physically con forms to the 6U VMEbus bo ard standard. Th e board requ ires the[...]

  • Page 16

    Chapter 1 - Intr oduction 4 Ethernet Front End Channel (FEC) The 82596 CA ® Local Area Networ k (LAN) Co-processor is used as the FEC Ether net controller . The 82596CA ® communicates with the rest o f the board throug h the LB US. The 82596CA ® has a 804 86 ® type bus interface, which requires two P ALs to con vert the 80486 ® interface to me[...]

  • Page 17

    VMEbus Short I/O In terface 5 VMEbus Short I/O Int erface The VMEbu s Short I/O interface allows for VMEb us host and onboard CPU communications. The host issues commands to the C ondor throu gh the Short I/O interface and the CPU issues status back to the host. The Short I/O Interf ace is a Slav e-only interface to the Condor and contains tw o ind[...]

  • Page 18

    Chapter 1 - Intr oduction 6 interrupt hand ler outputs an interrupt v ector number fo r the non-DMA engine interrupt s or requests access to the LB US for a DMA engine I A CK cycles. CPU/LBUS Interface The CPU/LBUS Interface link s the CPU core with the LBUS resources. The CPU/LBUS interf ace con verts the CPU Core bus to the LBUS. The Interf ace i[...]

  • Page 19

    7 CHAPTER 2 HARDWARE INSTALLATION Overvi ew Before attemptin g installation, read this chapter thor oughly to insure the safe inst allation of the Condor into your system. If you ha ve any questions re garding installatio n, which are not answered in this chapter , please contact Interph ase Customer Service at (214 ) 919-9111 . The Condor is insta[...]

  • Page 20

    Chapter 2 - Hardware Installatio n 8 The daughter card installation procedure will vary depending on the desired configuration. V ariables include: • Single Channel AUI/10BaseT. • Dual Ethernet AUI. • Dual Ethernet 10Ba seT. The follo wing table summ arizes the Condor pr oducts that are a v ailable from Interphas e to implement v arious combi[...]

  • Page 21

    Overview 9 Figure 2-1 . 10BaseT Con dor Mothe rboard Layout (PB04 221-000) LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 LED 7 SPB SPA J14 J15 J16 J1 8 J12 J13 P2 P1 J23 J24 J26 J25 J19 J20 J21 J22 J9 J3 OPTIONAL DAUGHTER CARD J17 F E C 0 F E C 1 J10 J2 J1 J4 J8 J7 J6 J5 J11[...]

  • Page 22

    Chapter 2 - Hardware Installatio n 10 Figur e 2-2. Sin gle Channel AUI or 10Ba seT Motherboard Layout (PB0 04221-001) LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 SPB SPA J14 J15 J16 J 1 8 J12 J13 P2 P1 J23 J24 J26 J25 J19 J20 J21 J22 J9 J8 J 1 7 F E C 0 F E C 0 J11 J1 J2 J3 J4 J7 J6 J5 AUI 10BaseT[...]

  • Page 23

    Overview 11 Figure 2- 3. AUI C ondor Motherb oard Layout (P B04221-000 ) LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 SPB SPA J14 J15 J16 J1 8 J12 J13 P2 P1 J23 J24 J26 J25 J19 J20 J21 J22 J9 J7 OPTIONAL DAUGHTER CARD J17 F E C 0 F E C 1 J6 J5 F1 J2 J1 J4 J3 J8 J10 J11[...]

  • Page 24

    Chapter 2 - Hardware Installatio n 12 Figure 2-4 . 10BaseT Con dor Mothe rboard Layout (PB04 221-001) LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 LED 7 SPB SPA J 1 0 J 1 4 J16 J 1 8 J12 J 1 5 P2 P1 J23 J24 J26 J25 J19 J20 J21 J22 J9 J8 OPTIONAL DAUGHTER CARD J 1 7 F E C 0 F E C 1 J11 J1 J2 J3 J4 J7 J6 J5[...]

  • Page 25

    Overview 13 Figure 2- 5. AUI C ondor Motherb oard Layout (P B04221-001 ) LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 SPB SPA J 1 0 J 1 4 J16 J 1 8 J12 J 1 5 P2 P1 J23 J24 J26 J25 J19 J20 J21 J22 J9 J7 OPTIONAL DAUGHTER CARD J 1 7 F E C 0 F E C 1 J6 J5 F1 J8 J4 J3 J2 J1 J11[...]

  • Page 26

    Chapter 2 - Hardware Installatio n 14 4221 Condo r Hardwa re Installatio n Procedures For proper installation of the Condor, it is imperative that you use the follo wing procedures. Step 1. Visual Inspection Before attempting the in stallation of this board, make sure you are wearing an anti-static or ground ing de vice. Remove the Condor b oard fr[...]

  • Page 27

    4221 C ondor Hardwar e In stallati on Pr ocedur es 15 Board Status LEDs LEDs 1, 2, 3, and 4 are Board Status LE Ds which provide the fo llowing functions: • Power On Self Test (POST) Mode • Monitor Mode • Run Mode POST Mode: This mode provides diagnostic s for the CPU and Buffer . Refer to the following table for a list of diagnostics perform[...]

  • Page 28

    Chapter 2 - Hardware Installatio n 16 T able 2-4. Run M ode L ED Ma trix Step 3. Set Onboard Motherboard Jumpers Set all onboard jumpers so that the Condor is properly conf igured for operation within your system. The board layout as illustrated in figure 2-1 shows the location of the jumpers. Motherboar d Jumper Set tings The following are jumpers[...]

  • Page 29

    4221 C ondor Hardwar e In stallati on Pr ocedur es 17 J9 +12 VOLTS Flash Pr ogramming Protect : IN: +12 V olt po wer connected to EPR OM socket. OUT : +12 V olt po wer disconnected from EPR OM socket. J12 VME Bus Grant: Pins 1 - 12 Reserved Pins 13 - 16 VME Bus Grant: T ab le 2-5. VME Bus Grant S ettings * = Facto ry De faul t J13 Firmware Option J[...]

  • Page 30

    Chapter 2 - Hardware Installatio n 18 (Pins 5- 6) Cons ole Message Disab le IN = Disable OUT = Enable (Pins 7-8) GDB Enable Point IN = GDB Initialized On Exit OUT = GDB Initialized On Reset J14 Firmware Option Jumpers: (Pins 1-2) 16 Bit Block Enable (default = OUT) IN = 1 6 bit Blo ck Mo de Di sabl ed OUT = 16 bi t Blo ck Mod e Ena ble d (Pins 3-4)[...]

  • Page 31

    4221 C ondor Hardwar e In stallati on Pr ocedur es 19 T able 2-6. Secondary Short I/O * Facto ry Defa ult J16 Primary Short I/O Siz e / Reset Enable : T able 2-7. Primary Short I/O Size * Facto ry Defa ult (Pins 5-6) Secondary Master Control Re gister (MCR) Reset En able (default = OUT) IN = Reset Enable OUT = Reset Disable (Pins 7-8) Primary Maste[...]

  • Page 32

    Chapter 2 - Hardware Installatio n 20 J18 Prim ary Channel Addre ss Modifiers: IN = Primary Channel Address Modif iers 29 or 2 D OUT = Primary Channel Addr ess Modifier 2D only J18[...]

  • Page 33

    4221 C ondor Hardwar e In stallati on Pr ocedur es 21 J19, J20, J21 & J22 Primary Shor t I/O Base Address: Refer to the following tables when setting Prim ary Short I/O Base Address es for the following: • Primary Sho rt I/O For 2K Base Ad dress • Primary Sho rt I/O For 1K Base Ad dress • Primary Sh ort I/O For 512 Bytes Base Addr ess •[...]

  • Page 34

    Chapter 2 - Hardware Installatio n 22 T able 2-8. Primary Base Address For 2K Short I/O NO TE : 0 = IN (Log ical 0), F = OUT (Log ical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J20 J21 J22 0000 F F F 0 0 0 0 0 F F F 0800 F F F F 0 0 0 0 F F F 1000 F F F 0 F 0 0 0 F F F 1800 F F F F F 0 0 0 F F F [...]

  • Page 35

    4221 C ondor Hardwar e In stallati on Pr ocedur es 23 T able 2-9. Primary Base Address For 1K Short I/O NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J20 J21 J22 8000 F F 0 0 0 0 0 F F F 0 8400 F F F 0 0 0 0 F F F 0 8800 F F 0 F 0 0 0 F F F 0 8C00 F F F F [...]

  • Page 36

    Chapter 2 - Hardware Installatio n 24 T able 2-10. Pr imary Base Address F or 512 By te Short I /O NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J20 J21 J22 C000 F 0 0 0 0 0 F F F 0 0 C200 F F 0 0 0 0 F F F 0 0 C400 F 0 F 0 0 0 F F F 0 0 C600 F F F 0 0 0 F[...]

  • Page 37

    4221 C ondor Hardwar e In stallati on Pr ocedur es 25 T able 2-10. Primar y Base Addres s For 5 12 Byte Sh ort I/O (Con tinued) NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J20 J21 J22 0000 F 0 0 0 0 0 0 0 F 0 0 0200 F F 0 0 0 0 0 0 F 0 0 0400 F 0 F 0 0 0[...]

  • Page 38

    Chapter 2 - Hardware Installatio n 26 T able 2-11. Pr imary Base Address F or 256 By te Short I /O NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J20 J21 J22 0000 0 0 0 0 0 0 0 0 0 0 0 0100 F 0 0 0 0 0 0 0 0 0 0 0200 0 F 0 0 0 0 0 0 0 0 0 0300 F F 0 0 0 0 0[...]

  • Page 39

    4221 C ondor Hardwar e In stallati on Pr ocedur es 27 T able 2-11. Primar y Base Addres s For 2 56 Byte Sh ort I/O (Con tinued) NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J13 J14 J15 2800 0 0 0 F 0 F 0 0 0 0 0 2900 F 0 0 F 0 F 0 0 0 0 0 2 A 0 00 F 0 F 0[...]

  • Page 40

    Chapter 2 - Hardware Installatio n 28 T able 2-11. Primar y Base Addres s For 2 56 Byte Sh ort I/O (Con tinued) NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J20 J21 J22 5000 0 0 0 0 F 0 F 0 0 0 0 5100 F 0 0 0 F 0 F 0 0 0 0 5200 0 F 0 0 F 0 F 0 0 0 0 5300 [...]

  • Page 41

    4221 C ondor Hardwar e In stallati on Pr ocedur es 29 T able 2-11. Primar y Base Addres s For 2 56 Byte Sh ort I/O (Con tinued) NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J20 J21 J22 7800 0 0 0 F F F F 0 0 0 0 7900 F 0 0 F F F F 0 0 0 0 7 A 0 00 F 0 F F[...]

  • Page 42

    Chapter 2 - Hardware Installatio n 30 T able 2-11. Primar y Base Addres s For 2 56 Byte Sh ort I/O (Con tinued) NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J20 J21 J22 A 0 0 0 0 0 0 0 0F 0F 0 0 0 A 1 0 0 F 0 0 0 0F 0F 0 0 0 A 2 0 0 0 F 0 0 0F 0F 0 0 0 A [...]

  • Page 43

    4221 C ondor Hardwar e In stallati on Pr ocedur es 31 T able 2-11. Primar y Base Addres s For 2 56 Byte Sh ort I/O (Con tinued) NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J20 J21 J22 C800 0 0 0 F 0 0 F F 0 0 0 C900 F 0 0 F 0 0 F F 0 0 0 C A 0 0 0 F 0 F [...]

  • Page 44

    Chapter 2 - Hardware Installatio n 32 T able 2-11. Primar y Base Addres s For 2 56 Byte Sh ort I/O (Con tinued) NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J20 J21 J22 F 0 0 0 0 0 0 0 FF FF 0 0 0 F 1 0 0 F 0 0 0 FF FF 0 0 0 F 2 0 0 0 F 0 0 FF FF 0 0 0 F [...]

  • Page 45

    4221 C ondor Hardwar e In stallati on Pr ocedur es 33 J23, J24, J25 & J26 Secondary S hort I/O Addres s: Refer to the following tables when setting Secondary S hort I/O Base Addresses for the foll o wing: • Secondary Short I /O For 2K Base Addr ess • Secondary Short I /O For 1K Base Addr ess • Secondary Short I /O For 512 Bytes Base Add r[...]

  • Page 46

    Chapter 2 - Hardware Installatio n 34 T able 2-12. Secondary B ase Address For 2K S hort I/O NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J24 J25 J26 0000 F F F 0 0 0 0 0 F F F 0800 F F F F 0 0 0 0 F F F 1000 F F F 0 F 0 0 0 F F F 1800 F F F F F 0 0 0 F F[...]

  • Page 47

    4221 C ondor Hardwar e In stallati on Pr ocedur es 35 T able 2-13. Secondary B ase Address For 1K S hort I/O NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J24 J25 J26 0000 F F 0 0 0 0 0 0 F F 0 0400 F F F 0 0 0 0 0 F F 0 0800 F F 0 F 0 0 0 0 F F 0 0C00 F F[...]

  • Page 48

    Chapter 2 - Hardware Installatio n 36 T able 2-13. Second ary B ase A ddre ss For 1K Shor t I/O (Cont inu ed) NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J24 J25 J26 8000 F F 0 0 0 0 0 F F F 0 8400 F F F 0 0 0 0 F F F 0 8800 F F 0 F 0 0 0 F F F 0 8C00 F [...]

  • Page 49

    4221 C ondor Hardwar e In stallati on Pr ocedur es 37 T able 2- 14. Se conda ry Ba se Addr ess For 5 12 Byte Short I /O NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J24 J25 J26 0000 F 0 0 0 0 0 0 0 F 0 0 0200 F F 0 0 0 0 0 0 F 0 0 0400 F 0 F 0 0 0 0 0 F 0[...]

  • Page 50

    Chapter 2 - Hardware Installatio n 38 T able 2-14. Second ary Base Addr ess For 512 Byt e Short I/O (Continue d) NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24,J25,J26 PIN SETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J24 J25 J26 5000 F 0 0 0 F 0 F 0 F 0 0 5200 F F 0 0 F 0 F 0 F 0 0 5400 F 0 F 0 F 0 F 0 F 0 0 5600 F [...]

  • Page 51

    4221 C ondor Hardwar e In stallati on Pr ocedur es 39 T able 2-14. Second ary Base Addr ess For 512 Byt e Short I/O (Continue d) NO TE: 0 = IN (Logical 0) , F= OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J24 J25 J26 A 0 0 0 F 0 0 0 0F 0F F 0 0 A 2 0 0 F F 0 0 0F 0F F 0 0 A 4 0 0 F 0 F [...]

  • Page 52

    Chapter 2 - Hardware Installatio n 40 T able 2- 14. Sec ondar y Base Addre ss For 512 Byte Sh ort I/O (Con tinued ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J24 J25 J26 F 0 0 0 F 0 0 0 FF FF F 0 0 F 2 0 0 F F 0 0 FF FF F 0 0 F 4 0 0 F 0 F 0 FF FF F 0 0 F 6 0 0 F F F 0 FF FF F 0 0 F 8 0 0 F 0 0 F FF F[...]

  • Page 53

    4221 C ondor Hardwar e In stallati on Pr ocedur es 41 T able 2- 15. Se conda ry Ba se Addr ess For 2 56 Byte Short I /O NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J24 J25 J26 0000 0 0 0 0 0 0 0 0 0 0 0 0100 F 0 0 0 0 0 0 0 0 0 0 0200 0 F 0 0 0 0 0 0 0 0[...]

  • Page 54

    Chapter 2 - Hardware Installatio n 42 T able 2-15. Second ary Base Addr ess For 256 Byt e Short I/O (Continue d) NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J24 J25 J26 2800 0 0 0 F 0 F 0 0 0 0 0 2900 F 0 0 F 0 F 0 0 0 0 0 2 A 0 00 F 0 F 0 F 0 0 000 2B00[...]

  • Page 55

    4221 C ondor Hardwar e In stallati on Pr ocedur es 43 T able 2-15. Second ary Base Addr ess For 256 Byt e Short I/O (Continue d) NO TE: 0 = IN (Lo gical 0), F= OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J24 J25 J26 5000 0 0 0 0 F 0 F 0 0 0 0 5100 F 0 0 0 F 0 F 0 0 0 0 5200 0 F 0 0 F 0[...]

  • Page 56

    Chapter 2 - Hardware Installatio n 44 T able 2-15. Second ary Base Addr ess For 256 Byt e Short I/O (Continue d) NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J24 J25 J26 7800 0 0 0 F F F F 0 0 0 0 7900 F 0 0 F F F F 0 0 0 0 7 A 0 00 F 0 F F F F 0 000 7B00[...]

  • Page 57

    4221 C ondor Hardwar e In stallati on Pr ocedur es 45 T able 2-15. Second ary Base Addr ess For 256 Byt e Short I/O (Continue d) NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J24 J25 J26 A 0 0 0 0 0 0 0 0F 0F 0 0 0 A 1 0 0 F 0 0 0 0F 0F 0 0 0 A 2 0 0 0 F 0[...]

  • Page 58

    Chapter 2 - Hardware Installatio n 46 T able 2-15. Second ary Base Addr ess For 256 Byt e Short I/O (Continue d) NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J24 J25 J26 F 0 0 0 0 0 0 0 FF FF 0 0 0 F 1 0 0 F 0 0 0 FF FF 0 0 0 F 2 0 0 0 F 0 0 FF FF 0 0 0 F[...]

  • Page 59

    4221 C ondor Hardwar e In stallati on Pr ocedur es 47 Step 4. Set Daughter Card Jumpers And Termin ations The follo wing daughter card settin gs are discussed: • Ethernet Single Channel AUI/10 BaseT Daughter Card • Dual Channel 10BaseT Ether net Daughter Card • Ethernet Dual Channel AUI Daug hter Card[...]

  • Page 60

    Chapter 2 - Hardware Installatio n 48 Ethernet Single Channel AUI/10BaseT Daugh ter Card COMPO NENT SI DE Figure 2-6. Ethernet Single Channel AUI/10BaseT Daughter Ca rd NO TE: LED3 is located on the sold er side of the daughter card and is not shown in this illustration. The Et her net Si ngle Chan nel A UI/1 0Base T D aught er Car d provi des tw o[...]

  • Page 61

    4221 C ondor Hardwar e In stallati on Pr ocedur es 49 Dual Channel 10BaseT E thernet Daughter Card COMPO NENT SI DE Figure 2-7. Dual Channel 10BaseT Eth ernet Daughter C ard The Dual Channel 10B aseT Ethernet Daughter Car d provides two RJ45 connectors as s hown in Figure 2-7 abo ve. T able 2-17 . D ual C hann el 10Ba seT Ethe rne t Daugh ter Ca rd[...]

  • Page 62

    Chapter 2 - Hardware Installatio n 50 Ethern et Dual Channel AUI Dau ghter Card COMPO NENT SI DE Figure 2-8. Ethernet Dual Channel AUI Daughter Card NO TE: LED3 is located on the sold er side of the daughter card and is not shown in this illustration. The Dual Channel A UI Ethernet Dau ghter Card pro vides two DB15 connectors as sho wn in Figur e 2[...]

  • Page 63

    4221 C ondor Hardwar e In stallati on Pr ocedur es 51 Step 5. Power Of f System Once the board is conf igured, ensure that the ho st system and peripherals are tu rned OFF . Step 6. Cabling Procedure The cabling pr ocedure depends on ho w you wish to co nfigure the system. Y our options are summarized in T able 2-19. T able 2-19. Ethernet Cab le Op[...]

  • Page 64

    Chapter 2 - Hardware Installatio n 52 RS232 Connect ors And Cables There are two 10 pin connector s (2x5 Headers) which are used as the RS232 port cable connectors. Thes e connectors are the s ame type used for the s econd serial port I/O Extension-X.2 of PC compatible machines. The connectors are labeled "SP A" and "SPB" (refer[...]

  • Page 65

    53 CHAPTER 3 MACSI HOST INTERFACE Introduction This chapter def ines the MA CSI host interf ace for the Interphase V/Ethernet 4221 Condo r . The Condor and its MA CSI host interface are designed to be backwards compatible with the Interphase V/Ethernet 42 07 Eagle MA CSI host interface. This compatibility e xists to the extent that single port oper[...]

  • Page 66

    Chapter 3 - MACSI Host Int erface 54 Field Off set The v alue in the far left column specif ies the field of fset. This value measures incr ements of 16 bits from the begi nning of the record, and may be thoug ht of as the d isplacement to be added to a pointer to short in te ger da ta ty pe r equir ed t o di ff ere ntia te th e par ticu lar f ield[...]

  • Page 67

    System Interfac e 55 System Interface This sec tion defines how the host communicates with the controller . The shared memory interface is defi ned, and each major section descr ibed in detail. Full def initi ons for particular comm ands ( what is communicated) can be f ound in a following section. MACSI Organization Ethernet MA CSI for the Condo r[...]

  • Page 68

    Chapter 3 - MACSI Host Int erface 56 The Mas ter Command Entry (MC E) and Comm and Q ueue Entri es (CQ E) are used to queue commands from the host to the controller . A Command Queue Entry (in either the CQE or MCE) is a 12-byte block containing all of the information need ed for the 4221 to locate and execute a comman d issued by the ho st. Contro[...]

  • Page 69

    Master Control St atus Bloc k (MCSB) 57 Master Cont rol Status Block (MCSB) The MCSB consists of a Master Status Register , which is used to report information from the controller to the host, and th e Ma ster Co ntro l Regist er , w hich p rovides infr eque ntly used c ontr ol fun ctio ns to t he ho st. T able 3-2. Master Contr ol Status Block Mas[...]

  • Page 70

    Chapter 3 - MACSI Host Int erface 58 Master Control Re gister (MCR) The MCR pro vides the host with infrequently used s ervices. These bits are both set and cleared b y the host. The controller clears these bits on po wer up, and does not alter them at any other time. T able 3-4. Master Control Re gister Start queue mode ( SQM) This bit is provided[...]

  • Page 71

    Onbo ard Command Queue Ent ry 59 Onboa rd C omma nd Que ue Ent ry The host issues a command to the controller through a Command Queue Entry (CQE). T wo types are provided: the Master Command Entry (MCE) , located at offset 0x001 0 is used to issue control commands, such as Initialize Controller , Report Network Statistics, and the like. The normal [...]

  • Page 72

    Chapter 3 - MACSI Host Int erface 60 Fetch o ffb oard (FOB) Setting this bit makes the Command Queue entry an of fboard entry . Please see the follo wing section for details. Fetch o ffb oard in prog ress (FIP) This bit is used internally by the controller . It ’ s value should not be used by the host dri ver . IOPB Address This fi eld contains a[...]

  • Page 73

    Offboard Command Queue Entry 61 DMA Transfer Control Word This field specifies how the controller sho uld DMA transfer the data from host memory . This field is fully def ined in the Common IOPB Stru cture definition, in the follo wing section. Please refer there for full details. Host Add re ss This f ield contains the ph ysical address of the com[...]

  • Page 74

    Chapter 3 - MACSI Host Int erface 62 Command Response Block (C RB) The CRB is used by the controller to post completed commands back to the host. It consists of the following fields: T able 3-8. Command R esponse B lock Command Response Status Word (CRSW) The CRSW describes the nature of the resp onse, and includes a handshake bit similar to the CQ[...]

  • Page 75

    Comman d Respo nse Bloc k (CRB) 63 Error (ER) This bit is s et with Command Complete w hen a returned IOPB comp leted with an error . Errored commands are ne ver returned via the Multiple Completion mechanism . The nature of the error can be determined b y examining the Return Status fi eld in the returned IOPB. Exception (EX) This bit is set with [...]

  • Page 76

    Chapter 3 - MACSI Host Int erface 64 Multiple Completed Returned IOPB Structure When multip le commands are returned fr om the controller to the ho st with a single interru pt, the following structure is used to return individual commands, starting in th e location of Shor t I/O normally us ed for the returned IO PB, and continuing for a maximum of[...]

  • Page 77

    Configu ratio n Statu s Block ( CSB) 65 Configurat ion Status Block (CSB) The controller u ses the CSB to re port the f irmware and hardware con figur ation upon po wer up. Thes e contents are v alid from the time Board OK is asserted, to the time the controller posts b ack multiple completed returned com mands in this space. The following f ields [...]

  • Page 78

    Chapter 3 - MACSI Host Int erface 66 Firmware Revision Level The f irmware revision le vel, represe nted as a 3-dig it ASCII valu e. Firmware Revision Date The re vision date of th e installed f irmware, repres ented as 8 ASCII digits. F or e xample, a release data of J anuary 15, 1994 w ould be repres ented as 0115 1994. Ethernet MAC Addresses (Po[...]

  • Page 79

    Controller Statistic s Block 67 Controller S tatisti cs Block This space was u sed to report netw ork statistics in the origin al Eagle MA C SI implementation for single port Ethernet support. Statis tics for multi-port contro llers, or single port implemen tations not requirin g Eagle MA CSI compatibility , should be ob tained via the R eport Netw[...]

  • Page 80

    Chapter 3 - MACSI Host Int erface 68 Transmi t Command s Submitte d T otal number of attempted frame transmissi ons (successful and un successful). Transmit DMA Com pletions T otal number of DMA transfers completed as the result of a trans mit command. Transmit 82596 Completions T o tal number of frames that the Intel 82596 Ethernet chip has transm[...]

  • Page 81

    Controller Statistic s Block 69 Transmit Completions Posted to H ost T otal number of frame completio ns posted to the Comman d Response Block an d Returned IOPB. Receive Commands S ubmitted T otal number of attempted message receptions (successful and u nsuccessful). Receives Dropped - No Pending Receive C ommand Number of frame receptions lost or[...]

  • Page 82

    Chapter 3 - MACSI Host Int erface 70 IO Parameter Blocks (IOPBs) This section provides a detailed description of each of the comman ds used by the host to communicate with the controller . Each command is listed belo w , along with the code associated with each co mmand. T able 3-13. IOPB Commands Common IOPB Structures Many co mmands share a set o[...]

  • Page 83

    Common IOPB Stru ctures 71 Command Code This f ield specifies the command to be e xecuted. Particular v alues are noted for each of the indi vidual commands. Command Options This fi eld specifies operational parameters or optio ns to be associated with the execution of the command. The following subf ields are av ailable for all commands: T able 3-[...]

  • Page 84

    Chapter 3 - MACSI Host Int erface 72 Address modif ier This f ield contains the VMEbus address modif ier used for the transfer . Refer to your system document ation for possible values for this field. Memory type (MT) This 2-bit field specif ies the width of the data trans fers. Permitted v alues are: T able 3-17. Memory T ype T ransfer typ e (TT) [...]

  • Page 85

    Initialize Co ntroller 73 Initi alize C ont roll er This command allo ws the host to specify global configuration parameters, and initializes the controller for use within a particular s ystem. Conf igurable param eters include the number of C QE entries, global DMA co ntrol parameters, an d possible offboard locations for posting back retur ned co[...]

  • Page 86

    Chapter 3 - MACSI Host Int erface 74 Contro ller Initiali zati on Blo ck (CI B) The CIB contains the actual v alues to use when initializing the controller . It may be located anywhere in Short I/O, though it mak es sense to place it after the MCE and before the Command Response Block. T able 3-20. Controller Initi alization Block Number of CQE Ent[...]

  • Page 87

    Controlle r Initialization Block (CIB) 75 Spec ial Netwo rk Opt ion s Originally , this f ield allo wed the host to set s eve ral network related options, such as disabling receiv es, or disab ling transmit CRC. A multiport controller requires that this type of contr ol be associated with a particular port, rather than as a global configuration par[...]

  • Page 88

    Chapter 3 - MACSI Host Int erface 76 A value between 1 and 0x20 (40 decimal) causes the controller, after b eing granted the bu s, to t ransfer data until 1) there is no m ore data, or 2) 16 m icro seconds elapses, or 3) one of the b us request lines on the VMEb us is asserted. W ith a v alue between 0x21 and 0x80, the controller , after being gran[...]

  • Page 89

    MAC Control/S tatus 77 MAC Control/Status This command pr ovides a host dr iv er with two distinct le vels of service to an Ether net port located on the 4221. First, it prov ides a general mechanism to control the Ethern et port, without the dri ver ha ving to kno w any particulars about the actual Eth ernet interface chip being used. Driv ers wri[...]

  • Page 90

    Chapter 3 - MACSI Host Int erface 78 T able 3-22. MA C Control / Status Command Code This fi eld must contain 0x4 3 to exec ute the MA C Control IOPB. MA C Control/Statu s O f f s t 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 0x00 Command C ode 0x01 Command Opt ions 0x02 Return Status 0x03 Normal Comp letion Le vel Normal Completion V ector 0x04 Error Compl[...]

  • Page 91

    MAC Control/S tatus 79 Command Options T able 3-23. Command Options Interru pt Enable (IE) Def ined in Commo n IOPB Stru ctures. Set MA C options (SM) When this bit is set, the state of the specified MA C is updated as per those bit s ettings specified in the MA C Status/Control word. If this bit is n ot set, the current settings will be repor ted [...]

  • Page 92

    Chapter 3 - MACSI Host Int erface 80 Abort Report (A R) Setting this bit cau ses commands abort ed with either the AA or the AN bit to be reported back to the hos t with the appropriate error code set. Setting this bit has no effect on pend ing receive s for particular ports aborted via t he Abor t Pen ding b it in the MAC Status /Con trol field. S[...]

  • Page 93

    MAC Control/S tatus 81 Setting this bit r esets the port: promiscuou s mode is disabled, multicast is disabled, any supplied multiple indi vidual addresses are lost. All of the internal mem ory structures for the port are reinitialized , and the port is reinitialized with power on default v alues. Enable/Disable MA C (EM) W ith SM set, setting this[...]

  • Page 94

    Chapter 3 - MACSI Host Int erface 82 T a ble 3-25. Intel 82596 T ransmit St atus / Control Backof f method (BM) (p. 4-13 1) This parameter determines when to start th e back-of f timeout. Disabl e backof f (DB) (p. 4-141) Disables the back off algorithm implemented in the 82596. Linear pr iority (LIN PRI) (p. 4-130, 131) Specifi es the number of sl[...]

  • Page 95

    MAC Control/S tatus 83 T able 3-26. Intel 82596 Recei ve Status / Contro l Sa ve bad frames (SB) (p. 4-1 29) When set bad fr ames (CRC error , Alignment error , etc.) are sent to the host . Broadcast disable (BD) (p. 4-134) Disables reception of frames with a Broadcast destination add ress or Multicast of all 1 ’ s. Multicast all (MA) (p. 4- 140)[...]

  • Page 96

    Chapter 3 - MACSI Host Int erface 84 T ime domain reflectometry test (TDR) (p. 4-150 ) This operation acti v ates the T ime Domain Reflectometry test. The result is retu rned in the MA C returned information field. Refer to the 82596 documentation for full details of the returned values. Dump 8959 6 internal re gisters (DU) (p. 4-153) This command [...]

  • Page 97

    Change Default Node Ad dress 85 Change Default Node Address This command is used to change the 48 bit physical address associated with any of the attached ports. It also can be used to manage b oth the factory and us er addresses stored in NVRAM, either by setting them to new v alues, or b y restorin g preset v alues. This command must be issued th[...]

  • Page 98

    Chapter 3 - MACSI Host Int erface 86 Command Options T able 3-28. Command Options Interru pt enable (IE) As def ined in the Common IOP B Structures. Update user default (UUD) Setting this bit upd ates the NVRAM-stored u ser default physical node address for the specified port with the v alue provided in the Physical Node Address f ield. Restore man[...]

  • Page 99

    Transm it 87 Tran smit The T ransmit command causes the controller to DMA transfer the specif ied frame from host memory , and then transmit it (if possible) through the specified Ethernet port. T able 3-29. T ransmit Command Code This fi eld must contain 0x5 0 to exec ute the T ransmit IOPB. Tr a n s m i t O f f s t 1 5 1 4 1 3 1 2 1 1 1 0 9876543[...]

  • Page 100

    Chapter 3 - MACSI Host Int erface 88 Command Options T able 3-30. Command Options Interru pt enable (IE) As def ined in Commo n IOPB Structures . In-line gat her (IG) Setting this bit all o ws the host to define the frame location in sys tem memory as a set of address/count pairs. These gather elements ar e specified directly in the remaind er of t[...]

  • Page 101

    Transmit -- In-Line Gath ers 89 T able 3-31. T ransmit - In-Line Gathers Number of Elements This fi eld contains the number of gather elements included in the IOPB. The on ly physical limit on this v alue is that the size of the total IOPB to be processed by the controller must fit in the IOPB l ength field in the CQE. Practically , ho wev er , thi[...]

  • Page 102

    Chapter 3 - MACSI Host Int erface 90 Receive The host provides the con troller with Recei ve co mmands, which specif y the host resources to be used for incoming frames. As frames come in, the controller trans fers them to the specif ied ho st memory locations, u pdates the pro vided Recei ve comman ds, and posts them b ack to the host. Recei ve co[...]

  • Page 103

    Receive 91 Command Code This f ield must contain 0x6 0 to exec ute the Recei ve IOPB. Command Options T able 3-33. Command Options Interru pt enable As defined in the Common IOPB Structures section. Port selector This field specif ies the port to which the receiv e resources will be allocated. V alid ports range from 0 to 3. Disable multiple comple[...]

  • Page 104

    Chapter 3 - MACSI Host Int erface 92 Sourc e Addres s When so monitoring the net work, the source addres s for the incoming frame will be contained in this field. Neither this field nor the pre vious will be used for normal fr ame reception activity .[...]

  • Page 105

    Initialize Multiple Comple tions 93 Initia lize M ultiple Co mple tions This command enables the controller to return multip le completed commands to the host with a single completion via the Command Resp onse Block, with a single (op tional) interrupt. When commands are completed us ing this mechanism, the returned IOPB is rep laced with a substan[...]

  • Page 106

    Chapter 3 - MACSI Host Int erface 94 Command Options No special options ar e av ailable for this com mand. Refer to Common IOPB structures for defined options. Retu rn Status There are not p articular errors currently def ined for this IOPB. Control Flags T able 3-35. Co ntrol Flag s Enable Multiple Complet ions (MEN) Setting this bit enables posti[...]

  • Page 107

    Report Netwo rk Statistics 95 Report Net work Statis tics T ab le 3-36. Report Network Statistics The Report Network Statistics Com mand can be used to obtain network statis tics for any Ethernet p ort av ail able on the controller . These statistics are accumulated since the last controller res et. The host may also specify a fix ed duration time [...]

  • Page 108

    Chapter 3 - MACSI Host Int erface 96 Command Options T able 3-37. Command Options Interru pt enable (IE) As def ined in Commo n IOPB Structures . Port selector This field specif ies the port for which the stati stics will be reported. V alid ports range from 0 to 3. Retu rn Status This f ield will contain an y return status fro m the controller to [...]

  • Page 109

    Netwo rk Stati stics Block 97 Network Statis tics Block T able 3-38. Networ k Sta tist ics B lock Data Valid Indicator When the data is transf erred to the host, this field will contain a non-zero v alue. By cleari ng this field to zero, the host can av oid inad vertent accesses to d irty data for repeating network statistics co mmands.n Port Indic[...]

  • Page 110

    Chapter 3 - MACSI Host Int erface 98 Transmi ts Failed This field contains the number of transmit commands fo r the particular port th at could not b e transmitted out over the media, due to excessi ve collisions. Collisions This field c ontains the total number of collisions for the particular interface. Receive s Submitt ed This f ield contains t[...]

  • Page 111

    99 APPENDIX A SPECIFICATIONS VMEbus Specif ications DTB Master A16, A24, A32, D08 (EO), D16, D32: B L T , D64: BL T DTB Slav e A16, D08 (EO), D16, D32 Requester An y of R(0-3), S tatic R WD, R OR Interru pter Any o f I(1-7), Dyn amic D08 (O) Power Requirements Dual A UI Ethernet Motherboard 5.70A typical @ +5 V DC (+/- 5%) 6.20 A max imu m @ +5V DC[...]

  • Page 112

    100 Appe ndix A Mechanical (Nominal) Leng th 233 mm Wi d t h 1 6 0 m m Thicknes s 2 0 mm We i g h t . 4 5 K g Operating E nvironment T emperatur e 0-55 deg rees Centigrade Relat ive Humidit y 10% - 90% N oncon dens ing Air Flow 250 CFM Minim um Fuse The A UI ver sion of the Condor h as a 1.5 amp fuse (F1) used to protect the +12 volts po wer when p[...]

  • Page 113

    101 APPENDIX B CONNECTOR PINOUTS AND CABLING Overvi ew This chapter contains the connector pinouts and cabling infor mation needed for v arious Condor co nfiguratio ns. The tables in this chapter are listed below . VMEbus Connectors • Table C-39 P1 Connector Signal Descriptions (All Versions) • Table C-40 P2 Connector For Motherbo ards Which On[...]

  • Page 114

    102 Appe ndix B VMEbus Connectors The follo w ing tables sho w the pin numbers and sig nal description for the P1 and P2 VMEbus Connectors. • Table C-39 - P1 Connector Signal Descrip tions (All Versions) • Table C- 40 - P2 C onn ect or For Moth erbo ards Whic h Only Uses P2 R ow B P1 Connector T able C-39. P1 Conn ector Signal D escriptions (A [...]

  • Page 115

    103 VMEbus Co nnectors P2 Connector R ow B Only Versi on T able C-40. P2 Connector Fo r Motherboards Which Only Uses P2 Ro w B PIN Ro w A Signal Mnemonic Row B Signal Mnemonic Row C Signal Mnemonic 1+ 5 V D C 2 GND 3 4A 2 4 5A 2 5 6A 2 6 7A 2 7 8A 2 8 9A 2 9 10 A30 11 A31 12 GND 13 +5V DC 14 D16 15 D17 16 D18 17 D19 18 D20 19 D21 20 D22 21 D23 22 G[...]

  • Page 116

    104 Appe ndix B Ethernet Conne ctors and Pinouts The Condor suppo rts both the A UI and 10BaseT version s of the Ethernet 802.3 specification. The card will ha ve a 15 pin "D" connector us ed for the A UI signals and a RJ45 connector fo r unshielded twisted pair (10BaseT). Tr ansform- ers are used with b oth interfaces to isolate the e xt[...]

  • Page 117

    105 Ethernet Connecto rs and Pino uts AUI Connector Signals The A UI signals and connecto r pinout for the DB15 connector are sho wn in the follo wing table. T able C-42. DB15 (A UI) Connector Signals Symbol Di r Pin Descr iption GND - 1 Digital Ground CLSNx I 2 Collision TRMTx O 3 T ransmit GND - 4 Digital Ground RCVx I 5 Recei ve Data GND - 6 Pos[...]

  • Page 118

    106 Appe ndix B RS232 Connector and Cable T able C -43. Serial Connector Pinou ts (SP A and SPB) NO TE : The same cable for the second Serial P ort for PC compatible systems can be used for the 4221 Condor . This cable can be b uilt or bou ght off-the-sh elf fr om many computer stor es. The cable pinout is show n in the following table: T able C-44[...]

  • Page 119

    107 APPENDIX C ERROR CODES The Return Status word in the command respon se contains information pertaining to the status of the IOPBs returned in the Comman d Response Block. Error codes are rep orted in he xadecimal format. HEX CODE DESCRIPT ION 0x110 VMEbus Error An attempted VME b us transfer generated a system b us error . 0x115 Abor t Pending [...]

  • Page 120

    108 Appe ndix B[...]

  • Page 121

    INDEX 109 Numerics 82596 4, 8 1, 82 A AA 79 Abort ALL (AA) 79 Abort ANY (AN) 79 Abort P ending (AP) 8 1 Abort R eport (AR) 80, 81 Air Flow 100 AN 79 ANY 91 AP 81 AR 80, 81 B bina ry 2 board ok (BOK) 57 BOK 5 7 byte 2 C cabl ing 51 dual 10BaseT dau ghter card 51 dual AUI da ughter card 51 installing 52 single chann el AUI/10BaseT daug hter card 51 C[...]

  • Page 122

    110 EX 63 Exception (EX) 63 F feature list 2 fetch of fboard ent ry (FOB) 60 Fetch o ffboard in pr ogress (F IP) 60 field offset 54 FIP 60 firmware rev ision level 6 6 FOB 60 Front End C hann el (F EC) 3, 4 fuse 14, 100 G go bi t 59 groundi ng 14 H hexadecimal 2 hog mode 75 Host Address 61 I IA 81 IE 71, 86, 88 IG 88 IM 80 Initialize Controller 7 3[...]

  • Page 123

    111 P PFM 86 PM 75, 81 POST mode 15 power r equirement s 99 Product C ode 65, 68 Program factory MAC address (PFM) 86 Promiscuous mo de (PM) 75, 81 Q QECR 60 QMS 63 Queue Entr y Control Reg ister (QECR) 59, 60 Queue Mode Started (QMS) 6 3 R Receive 82, 9 0, 93, 98 Relative Humidity 100 Reliability 1 00 Report Network Statis tics 67, 95 Rese rved fi[...]

  • Page 124

    112[...]