Intel IXP2800 manual

Order Number: 278882-010 Intel ® IXP2800 Network Processor Hardware Reference Manual August 2004[...]

2 Hardware Reference Manual Revision History INFORMA TION IN THIS DOCUMENT IS PRO VIDED IN CONNECTIO N WITH INTEL ® PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LI ABILITY WHA TSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELA TING T O SALE A ND/OR USE OF INTEL PRODUCT[...]

Hardware Reference Manual 3 Contents Contents 1 Introduction . ................ ............. ............. ................ ............. ............. ................ ............. ............. ... 25 1.1 About This Document ............... ............. ................ ............. ................ ............. ................ ... 25 1.2 R[...]

4 Hardware Reference Manual Contents 2.6 Scratchpad Memory........... ............. ................ ................ ............. ................ ................ ...... .5 6 2.6.1 S cratchpad Atomic Operations ................. ................ ............. ................ ................ 57 2.6.2 Ring C ommands ............. ............. .[...]

Hardware Reference Manual 5 Contents 3.2.7 Power Management ..................... ................ ............. ................ ............. ................ 81 3.2.8 Debugging ............ ................ ............. ................. ............ ............. ................ .......... 81 3.2.9 JTAG ............... ................ ......[...]

6 Hardware Reference Manual Contents 3.6.2.3.4 Write-Back versus Write-Through ............. ................ ........... 101 3.6.2.4 Round-Robin Replacement Algorithm ................... ................ .............. 1 02 3.6.2.5 Parity Protection.... ................ ............. ................ ............. ................ ..... 102 3.6.2.[...]

Hardware Reference Manual 7 Contents 3.11.5 I/O Transaction ............ ............. ............. ................ ............. ............. ................ .... 130 3.11.6 Hash Access ... ................ ............. ............. ................ ............. ................ ............. . 130 3.11.7 Gasket Local C SR ............. ...[...]

8 Hardware Reference Manual Contents 4.3.1 B yte Align.... ............. ................ ............. ................. ............ ................. ............ ..... 174 4.3.2 C AM ............ ............. ............. ................ ............. ................ ............. ............. ........ 17 6 4.4 CRC Unit............... ....[...]

Hardware Reference Manual 9 Contents 6.2.1 Internal Interface ............. ............. ................ ............. ................ ............. ............. . 2 09 6.2.2 Number of Channels ....... ............. ................ ............. ................ ............. .............. 209 6.2.3 Coprocessor and/or SRAMs Attached to a Chan[...]

10 Hardware Reference Manual Contents 8.2.5 Rx_Thread_Freelist_Timeout_# .. ......... ....... ............. ............. ................ ............. . 256 8.2.6 R eceive Operation Summary .......... ................ ................ ............. ................ ........ 256 8.2.7 R eceive Flow Control Status ................ ............. ...[...]

Hardware Reference Manual 11 Contents 8.7.2.3 Single IXP2800 Network Processo r ............. ............. ............. .............. 289 8.8 Interface to Command and Push and Pull Bu ses ..... ............. ............. ................ ............. . 290 8.8.1 RBUF or MS F CSR to Micr oengine S_TRA NSFER_IN Re gister for In struction: . 291 [...]

12 Hardware Reference Manual Contents 9 PCI Unit . ............. ................ ............. ............. ................ ............. ............. ................ ............. ........ 319 9.1 Overview ............ ................ ............. ............. ................ ............. ................ ............. .... ....... 319 9[...]

Hardware Reference Manual 13 Contents 9.4.2 Push/Pull Command Bus Target Interface...... ................ ............. ................ ........ 345 9.4.2.1 Command Bus Master Access to Lo cal Configuration R egisters ........ 345 9.4.2.2 Command Bu s Master Acce ss to Local C ontrol and Status Registers ................. ................. .......[...]

14 Hardware Reference Manual Contents 10.3.2 PCI-Initiated Reset ....... ......... ............. ............. ................ ............. ............. ........... 366 10.3.3 Watchdog Timer-Initiate d Reset ..... ............. ............. ................ ............. ............. . 366 10.3.3.1 Slave Network Processor (Non-Cen tral Functio[...]

Hardware Reference Manual 15 Contents 11.4.6.7 ME01 Events Target ID(100001) / Design Blo ck #(1001) ... ................ . 410 11.4.6.8 ME02 Events Target ID(100010) / Design Blo ck #(1001) ... ................ . 411 11.4.6.9 ME03 Events Target ID(100011) / Design Blo ck #(1001) ... ................ . 411 11.4.6.10 ME04 Events Target ID (100100) /[...]

16 Hardware Reference Manual Contents Figures 1 IXP2800 Network Processor Functional Block Dia gram ............... ............. ............. ................ ... 28 2 IXP2800 Network Processor Deta iled Diagram ............. ................ ............. ................ ............. ... 29 3 Intel XScale® Core 4-GB (32-Bit) Address Space ...[...]

Hardware Reference Manual 17 Contents 48 An Interface Topology with Intel / AMCC* SONET/SDH Device ............................. ................ . 1 58 49 Mode 3 Second Interface Topo logy with Intel / A MCC* SONET/SDH Devic e ............... ........... 159 50 Mode 3 Single Write Transfer Followed by Read (B0) ............ ................ ......[...]

18 Hardware Reference Manual Contents 98 CSIX Flow Control Interf ace — FCIFIFO and FCEFIFO in Full Du plex Mode .............. ........... 2 77 99 CSIX Flow Control Interf ace — FCIFIFO and FCEFIFO in Simp lex Mode ...... ................ ........ 278 100 MSF to Command and Push a nd Pull Buses Interface Block Di agram ........................[...]

Hardware Reference Manual 19 Contents Tables 1 Data Terminology ................... ............. ................ ................ ............. ................ ............. .... ......... 26 2 Longword Formats ..... ................ ................ ............. ................. ............ ................. ............ .. ........ 26 3 IXP[...]

20 Hardware Reference Manual Contents 47 Byte-Enable Generation by the Intel XScale ® Core for Byte Writes in Little- and Big-Endian Systems .................. ................ ............. ................ ............. ................ ............. .... .... 123 48 Byte-Enable Generation by the Intel XScale ® Core for Word Writes in Little- a[...]

Hardware Reference Manual 21 Contents 95 Order in which Data is Transmitted from TBUF .......... ............. ............ ................. ............ ........ 263 96 Mapping of TBUF Partitions to Transmit Prot ocol ......................... ................ ............. .............. 263 97 Number of Elements per TBUF Partit ion ............[...]

22 Hardware Reference Manual Contents 138 Byte Enable Alignm ent for 64-Bit PCI Da ta In (64 Bits PCI Little-Endian to Big- Endian with Swap) ..................... ............. ................ ............. ................ ............. ................ .. ...... 355 139 Byte Enable Alignm ent for 64-Bit PCI Data In (64 Bits PCI Big-Endian to Bi[...]

Hardware Reference Manual 23 Contents 181 SRAM CH0 PMU Event List ................ ................ ................ ............. ................ ............. ........... 422 182 IXP2800 Network Processor Dram DPLA PMU Event List ............ ................ ................ ........... 423 183 IXP2800 Network Processor Dram DPSA PMU Event List[...]

24 Hardware Reference Manual Contents[...]

Hardware Reference Manual 25 Intel ® IXP2800 Network Processor Introduction Introduction 1 1.1 About This Document This document is the hardware reference manual for the Intel ® IXP2 800 Network Processor . This information is inten ded for use by developers and is organized as follows: Section 2, “T echnical Description” contains a hardware [...]

26 Hardware Reference Manual Intel ® IXP2800 Network Processor Introduction 1.3 T erminology Ta b l e 1 and Ta b l e 2 list the terminology used in this manual. T able 1. Dat a T erminology T erm Words Bytes Bits Byte ½ 1 8 Wor d 1 2 16 Longword 2 4 32 Quadword 4 8 64 T able 2. Long word Formats Endian T ype 32-Bit 64-Bit Little-Endian (0x1234567[...]

Hardware Reference Manual 27 Intel ® IXP2800 Network Proce ssor T echnical Description T echnical Description 2 2.1 Overview This section provides a brief overview of the IXP2800 N etwork Processor internal hardware. This section is intended as an overall hard ware introduction to the netwo rk processor . The major blocks are: • Intel XScale ® [...]

28 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion Figure 1. IXP2 800 Network Processor Functional Block Diagram A9226-02 Media Switch Fabric (MSF) Scratched Memory SRAM Controller 0 SRAM Controller 1 SRAM Controller 2 SRAM Controller 3 DRAM Controller 0 DRAM Controller 1 DRAM Controller 2 Hash Unit PCI Control[...]

Hardware Reference Manual 29 Intel ® IXP2800 Network Proce ssor T echnical Description Figure 2. IXP2800 Net work Processor Det ailed Diagram A9750-03 SHaC Unit Scratch Hash CAP DRAM DRAM Controller DRAM DRAM Controller DRAM DRAM Controller SRAM SRAM Controller SRAM SRAM Controller SRAM SP14/CSIX Device SRAM Controller Media Controller RBuf TBuf C[...]

30 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion 2.2 Intel XScale ® Core Microarchitecture The Intel XScale ® microarchitecture consists of a 32-bi t general p urpose RISC processor that incorporates an extensive list of architecture features that allows it to achieve high performance. 2.2.1 ARM* Comp atibi[...]

Hardware Reference Manual 31 Intel ® IXP2800 Network Proce ssor T echnical Description 2.2.2.4 Branch T arget Buffer The Intel XScale ® microarchitecture provides a Branch T ar get Buffer (BTB) to predict the outcome of branch type instructions. It provides storage for the target ad dress of branch type instructions and predicts the next address [...]

32 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion 2.2.2.7 Address Map Figure 3 shows the parti tioning of the Inte l XScale ® core microarchitecture 4-Gbyte address space. Figure 3. Inte l XScale ® Core 4-GB (32-Bit) Ad dress Space A9693-02 0X0000 0000 DRAM and Intel XScale ® Core FLASH ROM (2 Gb) SRAM (1 G[...]

Hardware Reference Manual 33 Intel ® IXP2800 Network Proce ssor T echnical Description 2.3 Microengines The Microengines do most of the programmable pre-packet processing in the IXP2800 Network Processor . There are 16 Microe ngines, connected as shown in Figure 1 . The Microengines have access to all shared resources (SRAM, DRAM, MSF , etc.) as w[...]

34 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion Figure 4. Microengine Block Diagram B1670-01 128 GPRs (A Bank) d e c o d e 128 GPRs (B Bank) 128 Next Neighbor 128 D XFER In NNData_In (from previous ME) D_Push (from DRAM) S_Push (from SRAM Scratchpad, MSF , Hash, PCI, CAP) 128 S XFER In 640 Local Mem A_Src B_[...]

Hardware Reference Manual 35 Intel ® IXP2800 Network Proce ssor T echnical Description 2.3.1 Microengine Bus Arrangement The IXP2800 Network Processor sup ports a sing le D_Push/D _Pull bus, and both Microengine clusters interface to the same bus. Also, it supports two command buses, and two sets of S_Push/S_Pull buses connected as shown in Ta b l[...]

36 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion Each of the eight Contexts is in one of four states. 1. Inactive — Some applications may not requ ire all eight contexts. A Context is in the Inact ive state when its CTX_ENABLE CSR enable bit is a 0. 2. Executing — A C ontext is in Ex ecuting state when it[...]

Hardware Reference Manual 37 Intel ® IXP2800 Network Proce ssor T echnical Description The Microengine provides the following functi onality during the Idle st ate: 1. The Microengine continuously checks if a Contex t is in Ready state. If so, a new Context begins to execute. If no Cont ext is Ready , the Microengine remains in the Idle state. 2. [...]

38 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion methods to writ e TRANSFER_IN registers, fo r example a read instruction executed by one Microengine may cause the data to be returned to a different Microengine. Details are covered in the instruction set descriptions). TRANSFER_OUT registers, when used as a d[...]

Hardware Reference Manual 39 Intel ® IXP2800 Network Proce ssor T echnical Description 2.3.4.4 Local Memory Local Memory is addressable storage within th e Microengine. Local Memory is read and written exclusively under p rogram control. Local Memory supplies o perands to the execut ion datapath as a source, and receives results as a destination. [...]

40 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion As shown in Example 1 , there is a latency in loading LM_ADDR. Unt il the new value is loaded, the old value is still usable. Example 5 shows the maximum pipelined usage of LM_ADDR. LM_ADDR can also be used as the base of a 16 32-bit word region of memory , wit[...]

Hardware Reference Manual 41 Intel ® IXP2800 Network Proce ssor T echnical Description In Example 8 , the second instruction wi ll access the Local Memory location one past the source/ destination of the first. 2.3.5 Addressing Modes GPRs can be accessed in either a context-relati ve or an absolute ad dressing mode. Some instructions can specify e[...]

42 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion 2.3.5.2 Absolute Addressing Mode W ith Absolu te addressing, any GP R can be read or written by an y of the eight Contexts in a Microengine. Absolute addressing enables register data to be shared among all of the Contexts, e.g., for global variables or for para[...]

Hardware Reference Manual 43 Intel ® IXP2800 Network Proce ssor T echnical Description 2.3.6 Local CSRs Local Control and Status registers (CSRs) are exte rnal to the Execution Datapath, and hold specifi c data. They can be read and written by special in structions (lo cal_csr_rd and local_csr_wr) and are accessed less frequently than datapath reg[...]

44 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion Example 10 shows a big-endian align sequence of instructions and the value of the various operands. Ta b l e 7 shows the data in the registers for this example. The value in BYTE_INDEX[1:0] CSR (which controls the shift amount) fo r this example is 2. Figure 6.[...]

Hardware Reference Manual 45 Intel ® IXP2800 Network Proce ssor T echnical Description Example 1 1 shows a little-end ian sequence of instructions and the value of the various operand s. Ta b l e 8 shows the data in the registers for th is example. The value in BYTE_INDEX[1:0] CSR (which controls the shift am ount) for this example is 2. As the ex[...]

46 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion Note: The S tate bits are data associated with the entr y . The use is only by software. There is no implication of ow nership of the entry by any Context. Th e State bits hardware function is: • the value is set by software (at th e time the en try is loaded[...]

Hardware Reference Manual 47 Intel ® IXP2800 Network Proce ssor T echnical Description The value in the State bits for an entry can be written, without modifying the T ag, by instruction: CAM_Write_State[entry_reg, state_ value] Note: CAM_Write_State does not modify the LRU list. One possible way to use the result of a lookup is to dispatch to th [...]

48 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion An algorithm for debug so ftware to find out the cont ents of the CAM is shown in Example 12 . The CAM can be cleared with CAM_Clear instruction. This instruction writ es 0x00000000 simultaneously to all entries tag, clears all the state bits, and puts the LRU [...]

Hardware Reference Manual 49 Intel ® IXP2800 Network Proce ssor T echnical Description 2.3.9 Event Signals Event Signals are used to coordinate a program wi th comp letion of external events. For example, when a Microengine executes an instruction to an external unit to read data (which will be written into a T ransfer_In reg ister), the program m[...]

50 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion 2.4 DRAM The IXP2800 Network Processor has controll ers for three Rambus* DRAM (RDRAM) channels. Each of the controllers independently accesses its own RDRAMs, and can operate concurrently with the other contro llers (i.e., they are not operating as a single, w[...]

Hardware Reference Manual 51 Intel ® IXP2800 Network Proce ssor T echnical Description 2.4.2 Read and Write Access The minimum DRAM physical access le ngth is 16 bytes. Software (and PCI) can read or write as little as a single byte, however the time (and bandwid th) taken at the DRAMs is the same as for an access of 16 bytes. Therefore, the best [...]

52 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion 2.5.1 QDR Clocking Scheme The controller drives out two pairs of K clock (K and K#). It also d rives out two pair s of C clock (C and C#). Both C/C# clocks externally return to the controller for reading data. Figu re 8 shows the clock diagram if the clocking s[...]

Hardware Reference Manual 53 Intel ® IXP2800 Network Proce ssor T echnical Description Each channel can be expanded by depth according to th e number of port enables available. If external decoding is used, then the number of SRAMs used is not limit ed by the number of port enables generated by the SRAM controller . Note: Doing external decoding m[...]

54 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion 2.5.4 Queue Dat a Structure Commands The ability to enqueue an d dequeue data buf fers at a fast rate is key to meeting line-rate performance. This is a difficult problem as it involves dependent memory references that must be turned around very quickly . The S[...]

Hardware Reference Manual 55 Intel ® IXP2800 Network Proce ssor T echnical Description V erification is requi red to test o nly the order rul es shown in T able 12 and T able 13 ). Note: A blank entry in T a ble 12 means that no order is enforced. T able 13 shows the architectural guara ntees of order to access to th e SAME SRAM Q_array entry betw[...]

56 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion 2.5.5.2 Microengine Software Restrictions to Maint ain Ordering It is the Micr oengine programmer’ s job to ensure order where the program flow finds order to be necessary and where the architecture does not guarantee that order . The signaling mechanism can [...]

Hardware Reference Manual 57 Intel ® IXP2800 Network Proce ssor T echnical Description 2.6.1 Scratchp ad Atomic Operations In addition to normal reads and writes, the Sc ratchpad Memory supports the follo wing atomic operations. Microengines have speci fic instructions to do each atom ic operation; the Intel XScale ® microarchitecture uses aliase[...]

58 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion Head, T ail, and Size are registers in the Scratchpad Unit. Head and T ail point to the actual ring data, which is stored in the Scratchpad RAM. The co unt of how many entries are on the Ring is determined by hardware using th e Head and T ail. For each Ring in[...]

Hardware Reference Manual 59 Intel ® IXP2800 Network Proce ssor T echnical Description 2.7 Media and Switch Fabric Interface The Media and Switch Fabric (MSF) Interface is us ed to connect the IXP2 800 Network Processor to a physical layer device (PHY) and/or to a Swit ch Fabric. the MSF consists of separate receive and transmit interfaces. Each o[...]

60 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion An alternate system configuration is shown in the block di agram in Figure 1 1 . In this case, a single IXP2800 Network Processor is used for both Ingress and Egress. The bit rate suppo rted would be less than in Figure 10 . A hypothetical Bus Converter chip, e[...]

Hardware Reference Manual 61 Intel ® IXP2800 Network Proce ssor T echnical Description 2.7.2 CSIX CSIX-L1 (Common Switch Interface) defines an interface between a T raffic Manager (TM) and a Switch Fabric (SF) for A TM , IP , MPLS, Ethernet, and similar data commun ications applications. The Network Processor Forum (NPF) www .npfor um.org, control[...]

62 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion 2.7.3.1 RBUF RBUF is a RAM that holds received data. It stores received data in sub-blocks (referred to as elements), and is accesse d by Mi croengines or the Intel XScale ® core reading the received information. Details of how RBUF elements are allocated and [...]

Hardware Reference Manual 63 Intel ® IXP2800 Network Proce ssor T echnical Description 2.7.3.1.2 CSIX and RBUF CSIX CFrames are placed into either RBUF with each CFrame allocating an el ement. Unlike SPI-4, a single CFrame must not spill over into another element. Sin ce CSIX spec specifies a maximum CFrame size of 256 bytes, this can be done by p[...]

64 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion Each RX_THREAD_FREELIST has an associated countdown timer . If the timer expires and no new receive data is available yet, the receive logi c will autopush a Null Recei ve S tatus W ord to the next thread on the RX_THREAD_FREELIST . A Null R eceive Status W ord[...]

Hardware Reference Manual 65 Intel ® IXP2800 Network Proce ssor T echnical Description 2.7.4 T ransmit Figure 13 is a simp lified Block Diagram of the MSF transmit section. 2.7.4.1 TBUF TBUF is a RAM that holds data and status to be transmitted. The data is written into sub-blocks referred to as elements, by Microengines or the Intel XScale ® cor[...]

66 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion All elements within a TBUF partition are transmitted in the order . Contro l information associated with the element defines which bytes are valid. The data from th e TBUF will be shifted and byte aligned as required to be transm itted. 2.7.4.1. 1 SPI-4 and TBU[...]

Hardware Reference Manual 67 Intel ® IXP2800 Network Proce ssor T echnical Description 2.7.4.1.2 CSIX and TBUF For CSIX, payload information is put int o the data area of the element, and Base and Extension Header information is put in to the Element Control W ord. When the Element Control W ord is written, the information is: The definitions of t[...]

68 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion There is a T ransmit V alid bit per element, that marks the element as ready to be transmitted. Microengines move all data into the element, by eit her or both of msf[write] and dram[tbuf_wr] instructions to the TBUF . Microengines also write the element T rans[...]

Hardware Reference Manual 69 Intel ® IXP2800 Network Proce ssor T echnical Description 2.8 Hash Unit The IXP2800 Network Processor contains a Hash Unit that can take 48-, 64-, or 128-bit data and produce a 48-, 64-, or a 128-bit hash index, re spectively . The Hash Unit is accessible by the Microengines and the Intel XScale ® core, and is useful [...]

70 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion Figure 14. Hash Un it Block Diagram A9367-02 128 48-bit, 64-bit or 128-bit Hash Select Data Used to Create Hash Index from S_T ransf er_Out 2-Stage Output Buffer shift 2-Stage Input Buffer Hashed Multiplicand 3 Multiplicand 1 Hash_Multiplier_48 Hash_Multiplier_[...]

Hardware Reference Manual 71 Intel ® IXP2800 Network Proce ssor T echnical Description 2.9 PCI Controller The PCI Controller provides a 64-bit, 66 MHz capable PCI Local Bus Revision 2.2 int erface, and is compatible to 32-bit or 33 MHz PCI devices. Th e PCI controller provides the following functions: • T arget Acc ess (external Bus Master acces[...]

72 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion For PCI to DRAM transfers, the PCI command is Memory Read, Memory Read line, or Memory Read Multiple. For DRAM to PCI transfers, the PCI command is Memory W rite. Memory Write Invalidate is not supported. Up to two DMA channels are running at a time with three [...]

Hardware Reference Manual 73 Intel ® IXP2800 Network Proce ssor T echnical Description 2.9.3.2 DMA Channel Operation The DMA channel can be set up to read the first de scriptor in SRAM, or with the first descriptor written directly to the DMA channel registers. Wh en descriptors and the descriptor li st are in SRAM, the procedure is as follows: 1.[...]

74 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion 2.9.3.3 DMA Channel End Operation 1. Channel owned by PCI: If not masked via the PCI Outbound Interrupt Mask register , the DMA channel interrupts the PCI host after the setting of the DMA done bit in the CHAN_X_C ONTROL register , which is readable in the PCI [...]

Hardware Reference Manual 75 Intel ® IXP2800 Network Proce ssor T echnical Description (either a PCI interrupt or an Intel XScale ® core interrupt). When an interrupt is received, the DOORBELL registers can be read and the bit mask can be interpreted. If a lar ger bit mask is required than that is provided b y the DOORBELL register , the MAILBOX [...]

76 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion 2.10 Control and S t atus Register Access Proxy The Control and Status Register Access Proxy (C AP) contains a number of chip-wide control and status registers. Some provide miscellaneous cont rol and status, while others are used for inter- Microengine or Micr[...]

Hardware Reference Manual 77 Intel ® IXP2800 Network Proce ssor T echnical Description 2.1 1.2 T imers The IXP2800 Network Processor contains four program mable 32-bit timers, which can be used for software support. Each timer can be clocked by the internal clock, by a divided versio n of the clock, or by a signal on an external GPIO pi n. Each ti[...]

78 Hardware Reference Manual Intel ® IXP2800 Network Proce ssor T echnical Descrip tion The access is asynchronous. Insertion of delay cycles for both data setup and hold time is programmable via internal Cont rol registers. The transfer can also wait for a handshake acknowledge signal from the external device. 2.12 I/O Latency Ta b l e 1 9 shows [...]

Hardware Reference Manual 79 Intel ® IXP2800 Network Processor Intel XScale ® Core Intel XScale ® Core 3 This section contains info rmation describing th e Intel XScale ® core, Intel XScale ® core gasket, and Intel XScale ® core Peripherals (XPI). For additional information about the In tel XScale ® architecture refer to the Intel XScale ® [...]

80 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.2 Features Figure 16 shows the major fun ctional blocks of the Intel XScale ® core. 3.2.1 Multiply/ACcumulate (MA C) The MAC unit supports early termin ation of multip lies/accumulates in two cycles and can sustain a throughput of a MAC operation every cy cle. A[...]

Hardware Reference Manual 81 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.2.3 Instruction Cache The Intel XScale ® core implements a 32-Kbyt e, 32-way set associativ e instruction cache with a line size of 32 bytes. All requests that “miss” the instruction cache generate a 32-byte read request to external memory . A mechanism to l[...]

82 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.3 Memory Management The Intel XScale ® core implements the Memory Management Unit (MMU) Arch itecture specified in the ARM Architectur e Reference Manual . T o accelerate virtual to phys ical address translation, the Intel XScale ® core uses both an instruction[...]

Hardware Reference Manual 83 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.3.1.2.2 Instruction Cache When examining these bits in a descriptor , the Instruction Cache only utilizes the C bit. If th e C bit is clear , the Instruction Cache considers a code fetch from that memory to be non-cacheable, and will not fill a cache entry . If t[...]

84 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core If the Line Allocation Policy is rea d-allocate, all load operatio ns that miss the cache request a 32-byte cache line from external memory and allocate it into either the data cache or mini-data cache (this is assuming the cache is enabled). S tor e operations tha[...]

Hardware Reference Manual 85 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.3.3 Interaction of the MMU, In struction Cache, and Data Cache The MMU, instruction cache, and da ta/mini-data cache may be enabled/disabled independently . The instruction cache can be enabled with the MMU enabled or disabled. However , the data cache can only b[...]

86 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.3.4.3 Locking Entries Individual entries can b e locked into the inst ruction and data TLBs. If a lock operation finds the virtual address translation already resident in th e TLB, the results are unpred ictable. An invalidate by entry comm and before the lo ck c[...]

Hardware Reference Manual 87 Intel ® IXP2800 Network Processor Intel XScale ® Core The proper procedure for locking entr ies into the data TLB is shown in Example 16 . Note: Care must be exercised here wh en allowing exceptions to occur during this routine wh ose handlers may have data that lies in a page that is trying to be locked into the TLB.[...]

88 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core Figure 17 illustrates locked entries in TLB. 3.4 Instruction Cache The Intel XScale ® core instruction cache enhances pe rformance by reducing the number of instruction fetches from external memory . The cache provides fast execution of cached code. Code can also [...]

Hardware Reference Manual 89 Intel ® IXP2800 Network Processor Intel XScale ® Core The instruction cache is vi rtually addressed and virtually tagged . The virtual addr ess presented to the instruction cache may be remapped by the PID register . 3.4.1 Instruction Cache Operation 3.4.1.1 Operation when Instruction Cache is Enabled When the cache i[...]

90 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.4.1.2 Operation when Inst ruction Cache is Disabled Disabling the cache prevents any lin es from being written into th e instruction cach e. Although the cache is disabled, it is still accessed and may genera te a “hit” if the data is already in the cache. Di[...]

Hardware Reference Manual 91 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.4.1.5 Parity Protection The instruction cache is pr otected by parity to ensu re data integrity . Each instruction cache word has 1 parity bit. (The instruction cache tag is not parity protected.) W hen a parity erro r is detected on an instruction cache access, [...]

92 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.4.2 Instruction Cache Control 3.4.2.1 Instruction Cache St ate at Reset After reset, the instructio n cache is alwa ys disabled, unlocked, and in validated (flushed). 3.4.2.2 Enabling/Disabling The instruction cache is enabled by setting bit 12 in coprocessor 15,[...]

Hardware Reference Manual 93 Intel ® IXP2800 Network Processor Intel XScale ® Core There are several requirements for locking down co de: 1. The routine used to lock lin es down in the cache must be placed in non-cacheable memory , which means the MMU is enabled. As a corollar y: no fetches of cacheable code should occur while locking instruction[...]

94 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core Example 20 shows how a routine, called “lockMe” in th is example, might be locked into the instruction cache. Note that it is possible to receive an exception while locking code. 3.4.2.5 Unlocking Instructions in the Instruction Cache The Intel XScale ® core p[...]

Hardware Reference Manual 95 Intel ® IXP2800 Network Processor Intel XScale ® Core The BTB takes the cu rrent instructio n address and checks to see if this address is a branch that was previously seen. It uses bits [8:2 ] of the current address to read ou t the tag and then compares this tag to bits [31:9,1] of the current instruct ion addr ess.[...]

96 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.5.2 Up date Policy A new entry is stored into the BTB when the following condi tions are met: • The branch instruction has executed • The branch was taken • The branch is not currently in the BTB The entry is then marked valid and the history bits are set t[...]

Hardware Reference Manual 97 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.6.1 Overviews 3.6.1.1 Dat a Cache Overview The data cache is a 32-Kbyt e, 32-way set associative cache, i. e., there are 32 sets and each set has 32 ways. Each way of a set contains 32 bytes (one cache line) and one valid bit. There also exist two dirt y bits for[...]

98 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.6.1.2 Mini-Dat a Cache Overview The mini-data cache is a 2-Kbyte, 2-way set associ ative cac he; this means there are 32 sets with each set containing 2 ways. Each way of a set cont ains 32 bytes (one cache line) and one valid bit. There also exist 2 dirty bits f[...]

Hardware Reference Manual 99 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.6.1.3 Write Buffer an d Fill Buffer Overview The Intel XScale ® core employs an eight en try write buffer , each entry containing 16 bytes. Stores to external memory are first placed in the write buf fer and subsequently taken out when the bus is available. The [...]

100 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.6.2.3 Cache Policies 3.6.2.3. 1 Cacheab ility Data at a specified address is cacheable given the following: • The MMU is enabled • The cacheable attribute is set in th e descriptor for the accessed address • The data/mini-data cache is enabled 3.6.2.3. 2 R[...]

Hardware Reference Manual 101 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.6.2.3.3 Write Miss Policy A write operation that misses the cache, requests a 32-byte cache line from external memory if the access is cacheable and write alloca tion is specified in the page; th en, the following events occur: 1. The fill buf fer is checked to [...]

102 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.6.2.4 Round-Robin Replacement Algorithm The line replacement algorithm for the data cache is round-robin. Each set in the data cache has a round-robin pointer that keeps track of the next line (in that set) to replace. The next line to replace in a set is the ne[...]

Hardware Reference Manual 103 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.6.3 Dat a Cache and Mi ni-Dat a Cache Control 3.6.3.1 Dat a Memory St ate Af ter Reset After processor reset, both the da ta cache and mini-data cache are disa bled, all valid bits are set to 0 (invalid), and the round-robin bit points to way 31. Any lines in th[...]

104 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.6.3.3.1 Global Clean and Invalida te Operation A simple software routine is used to globally cl ean the data cache. It takes advantage of the line- allocate data cache operation, which allocates a line into the data cache. This allocation evicts any cache dirty [...]

Hardware Reference Manual 105 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.6.4 Reconfiguring the Da t a Cache as Dat a RAM Software has the ability to lock tags associated with 32-byte lines in the data cache, thus creating the appearance of data RAM. Any subsequent access to this line will always hit the cache unless it is invalidated[...]

106 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.6.5 Write Buffer/Fill Buff er Operation and Control The write buffer is always enabled, which means stores to external memory will be buffered. The K bit in the Auxiliary Control register (CP15, register 1) is a global enable/disable for allowin g coalescing in [...]

Hardware Reference Manual 107 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.8 Performance Monitoring The Intel XScale ® core hardware provides two 32-bi t pe rformance counters that allow two unique events to b e monitored simult aneously . In addition, the Intel XScale ® core implements a 32-bit clock counter that can be used in conj[...]

108 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core Some typical combination of counted events are listed in th is section and summarized in T able 25 . In this section, we call such an event combination a mode . 3.8.1.1 Instruction Cache Efficiency Mode PMN0 totals the number of instructions that we re execut ed, [...]

Hardware Reference Manual 109 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.8.1.2 Dat a Cache Efficiency Mode PMN0 totals the number of data cache accesse s, which includes cacheable and non-cacheable accesses, mini-data cache access and accesses made to locations configured as data RAM. Note that STM and LDM will each count as several [...]

110 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core Statistics derived from these two events: • The average number of cycles the pr ocessor stalle d on a data-cache access that may overflow the data-cache bu ffers . This is calculated by dividing PMN0 by PMN1. This st atistic lets you know if the duration event c[...]

Hardware Reference Manual 111 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.8.1.6 Instruction TLB Efficiency Mode PMN0 totals the n umber of instructio ns that we re executed, which does not include instructions that were translated by the instruction TLB a nd never executed. This can happen if a branch instruction changes the program f[...]

112 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.9.1 Interrupt Latency Minimum Interrupt Latency is defined as the minimum number of cycles from the assertion of any interrupt signal (IRQ or FIQ) to the execution of the inst ruction at the vector for that interrupt. The point at which the assertion begins is T[...]

Hardware Reference Manual 113 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.9.3 Addressing Modes All load and store addressing mode s implemented in the Intel XScale ® core do not add to the instruction latencies numbers. 3.9.4 Instruction Latencies The latencies for all the instruct ions are shown in the following sections with respec[...]

114 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core Minimum Issue Latency (wit hout Branch Misprediction) to the min imum branch late ncy penalty numb er from Ta b l e 2 6 , which is four cycles. • Minimum Resource Latency The minimum cycle distance from the issue clock of the current multiply instructi on to the[...]

Hardware Reference Manual 115 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.9.4.2 Branch Instruction Timings ( 3.9.4.3 Dat a Processing Instructio n Timings T able 28. Branch Instruction T imings (Predicted by the BTB) Mnemonic Minimum Issue Laten cy when Correctly Predicted by the BTB Minimum Issue Latency with Branch Misprediction B1 [...]

116 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.9.4.4 Multiply Instruction Timings T able 31. Multiply Instruct ion Timings (Shee t 1 of 2) Mnemonic Rs V alue (Early T erminat ion) S-Bit Va l u e Minimum Issue Latency Minimum Result Latency 1 Minimum Resource Latency (Through put) MLA Rs[31:15] = 0x00000 or R[...]

Hardware Reference Manual 117 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.9.4.5 Saturated Arit hmetic Instructions h UMULL Rs[31:15] = 0x00000 0 1 RdLo = 2; RdHi = 3 2 13 3 3 Rs[31:27] = 0x00 0 1 RdLo = 3; RdHi = 4 3 14 4 4 all others 0 1 RdLo = 4; RdHi = 5 4 15 5 5 1. If the next instruction needs to use the result of the multiply fo[...]

118 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.9.4.6 St atus Register Access Instructions 3.9.4.7 Load/Store Instructions 3.9.4.8 Semaphore Instructions T able 35. Stat us Register Access Instruction T imings Mnemonic Minimum Issue Latency Minimum Result Latency MRS 1 2 MSR 2 (6 if updating mode bits) 1 T ab[...]

Hardware Reference Manual 119 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.9.4.9 Coprocessor Instructions 3.9.4.10 Miscellaneous Instruction Timing 3.9.4.1 1 Thumb Instructions The timing of Thu mb instructio ns are the same as their equivalent ARM* instructions. This mapping can be fo und in the ARM* Ar chitectur e Reference Manual . [...]

120 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.10.1 IXP2800 Network Processor Endianness Endianness defines the way bytes are addressed with in a word. A little-endi an system is one in which byte 0 is the least significant byte (LSB) in the word and byte 3 is the most significant byte (MSB). A big-endian sy[...]

Hardware Reference Manual 121 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.10.1.1 Read and Write T ransactions Initiated by the Intel XScale ® Core The Intel XScale ® core may be used in either a little-e ndian or big-endian configuration. The configuration affects the entire sy stem in which the Intel XScale ® core microarchitectur[...]

122 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 16-Bit (Word ) Read When reading a word, the Intel XScale ® core generates the byte_enabl e that corresponds to the proper byte lane as defi ne d by the endianness setting. Figure 25 summarizes byte enable generation for this mode. The 4-to-1 multiplexer steers b[...]

Hardware Reference Manual 123 Intel ® IXP2800 Network Processor Intel XScale ® Core 32-Bit (Lon gword) Read 32-bit (longword) reads are independent of endianness. Byte l ane 0 from the Intel XScale ® core’ s data bus gets into the byte 0 location of the read register insid e the Intel XScale ® core, byte lane 1 from the Intel XScale ® core?[...]

124 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core Word W rite (16-Bit s Write) When the Intel XScale ® core writes a 16-bit word to external memory , it puts the bytes in the byte lanes where it intends to w rite them along with t he byte enables for those bytes turned ON based on the endian setting of th e syst[...]

Hardware Reference Manual 125 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.1 1 Intel XScale ® Core Gasket Unit 3.1 1.1 Overview The Intel XScale ® core uses the Core Memory Bus (CMB ) to communicate with the functional blocks. The r est of the IXP2800 N etwork Processor fu nctional blocks us e the Command Push Pull (CPP) as the globa[...]

126 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core The Intel XScale ® core coprocessor bus is not us ed in the IXP2800 Net work Processors, therefore all accesses are only through the Command Me mory Bus. Figure 27 shows the block diagram of the global bus connections to the gasket. The gasket unit has th e follo[...]

Hardware Reference Manual 127 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.1 1.2 Intel XScale ® Core Gasket Functional Description 3.1 1.2.1 Command Memory Bus to Command Push/Pull Conversion The primary function of the Intel XScale ® core gasket unit is to tran slate commands initiated from the Intel XScale ® core in the Intel XSca[...]

128 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.1 1.4 Atomic Operations The Intel XScale ® core has Swap (SWP ) and Swap Byte (S WPB) instructions that generate an atomic read-write pair to a si ngle address. These instructions are supported for t he SRAM and Scratch space, and also to any other address spac[...]

Hardware Reference Manual 129 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.1 1.4.1 Summary of Rules for th e Atomic Command Regarding I/O The following rules summarize the Atomic comm and, regarding I/O. • SWP to SRAM/Scratch and Not cbiIO, Xscale_ IF generates an Atomic operation command. • SWP to all other Addresses that are not [...]

130 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.1 1.5 I/O T ransaction The Intel XScale ® core can request an I/O tr ansaction by asserting xsoCBI_IO concurrently with xsoCBI_Req. The value of xsoCBI_IO is undefined when xsoCBI_Req is not asserted. When the gasket sees an I/O request with xsoCBI_IO a sserted[...]

Hardware Reference Manual 131 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.1 1.7 Gasket Local CSR There are two sets of Control a nd S tatus registers resi ding in the gasket Local CSR space. ICSR refers to the Interrupt CSR. The ICSR address range is 0xd600_0000 – 0xd6ff_f fff. The Gasket CSR (GCSR) refers to the Hash CSRs and debug[...]

132 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.1 1.8 Interrupt The Intel XScale ® core CSR controller contains local CSR( s) and interrupts inputs from multiple sources. The diagram in Figure 28 shows the flow through the control ler . W ithin the Interrupt/CSR reg ister block there are ra w status register[...]

Hardware Reference Manual 133 Intel ® IXP2800 Network Processor Intel XScale ® Core Figure 29. Interrupt Mask Block Diagram A9699-01 {Error ,Thread}RawStatus IRQ{Error ,Thread}Status FIQ{Error ,Thread}Status RawStatusReg {Error ,Thread}RQEnReg {Error ,Thread}FIQEnReg Interrupt{Error ,Thread}RawStatus Interrupts,IRQ{Error ,Thread}Status IRQEnReg {[...]

134 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12 Intel XScale ® Core Peripheral Interface This section describes the Intel XScale ® core Peripheral Interface unit (X PI). The XPI is the block that connects to all the slow and serial in terfaces that communicat e with the Intel XScale ® core through the A[...]

Hardware Reference Manual 135 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.1.1 Data T ransfers The current rate for data transf ers is four bytes, except for the Slowport. The 8-bit and 16-bit accesses are only available in the Slowport bus. Th e devices connecte d to th e Slowport dictate this data width. The user h as to configure[...]

136 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.1.3 Address Sp aces for XPI Internal Devices Ta b l e 5 3 shows the address space assignment for XPI devices. T able 52. Data T ransaction Alignment Interface Units APB Bus Read Write GRegs 32 bits 32 bit s 32 bit s UART 32 bits 32 bits 32 bits GPIO 32 bits 3[...]

Hardware Reference Manual 137 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.2 UART Overview The UAR T performs serial -to-parallel conversion on data characters received from a peripheral device and parallel-to-serial conversion on data characters receive d from the network processor . The processor can read the complete status of th[...]

138 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.3 UART Operation The format of a UAR T data frame is shown in Figure 31 . Figure 31. UART Data Frame Each data frame is between 7 bits and 12 bits lo ng depending on the size of data programmed, if parity is enabled and if two stop bits i s selected. Th e fra[...]

Hardware Reference Manual 139 Intel ® IXP2800 Network Processor Intel XScale ® Core Character Time-out Interrupt When the receiver FIFO and receive r time-out interrupt are enabled, a character time-out interrupt occurs when all of the following cond itions exist: • At least one character is in the FIFO. • The last received character was long[...]

140 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.5 General Purpose I/O (GPIO) The IXP2800 Network Processor has eight General Purpose Input/Ou tput (GPIO) port pins fo r use in generating and capturing application-specific input and ou tput signals. Each pi n is programmable as an input or output or as an i[...]

Hardware Reference Manual 141 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.6 T imers The IXP2800 Network Processor sup ports four tim ers. These timers are clocke d by the Advanced Peripheral/Bus Clock (APB-CLK), which runs at 50 MHz to produce the PLPL_APB_CLK, PLPL_APB_CLK/16, or PLPL_APB_CLK/ 256 signals. The counters are loaded [...]

142 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core Figure 34 shows the Timer Internal logic. 3.12.7 Slowport Unit The IXP2800 Network Processor Sl owport Unit supports b asic PROM access and 8 -, 16-, and 32-bit microprocessor device access. It allows a master, (Intel XScale ® core or Microengine), to do a read/ [...]

Hardware Reference Manual 143 Intel ® IXP2800 Network Processor Intel XScale ® Core The Flash memory interface is used for the PR OM device. The micropro cessor interface can be used for SONET/SDH Framer microproces sor access. There are two ports in the Slowpo rt unit. The first is dedicated to the flash memory device while the second to the mic[...]

144 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.7.3 Slowport Unit Interfaces Figure 35 shows the Slowport unit interface diagram. PMC-Sierra* PM5355 8 bits 0x2 0x0 PMC-Sierra* PM5356 8 bits 0x2 0x0 PMC-Sierra* PM5357 8 bits 0x2 0x0 PMC-Sierra* PM5358 1 6 bits 0x2 0x1 PMC-Sierra* PM5381 1 6 bits 0x2 0x1 PMC[...]

Hardware Reference Manual 145 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.7.4 Address Sp ace The total address space is defined as 64 Mbytes, wh ich is further divided into two segments of 32 Mbytes each. T wo devices can be connect to this bus. If these peripheral devices have a density of 256 Mbits (32 Mbytes) each, all the addre[...]

146 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.7.6 Slowport 8-Bit Device Bus Protocols The write/read transfer protocols are discussed in the following sections. The burst transfers are going to be broken down into single mode transfer . For each single write/read transaction, it can be either fixed-timed[...]

Hardware Reference Manual 147 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.7.6.1 Mode 0 Single Write T ransfer for Fixed-T imed Device Figure 38 , shows th e single write transfer for a fixe d-timed device with th e CSR programmed to a value of setup=4, pulse width=0, and ho ld=2, followed by anot her read transfer . The transaction[...]

148 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.7.6.2 Mode 0 Single Write T ransfer for Self-T iming Device Figure 39 depicts the single write transfer for a se lf-timing device with the C SR programmed to setup=4, pulse width=0, and hold=3. Similarly , a read transaction is attached behind. Similar to the[...]

Hardware Reference Manual 149 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.7.6.3 Mode 0 Single Read T ransfer for Fixed-T imed Device Figure 40 demonstrates the single read transfer issued to a fixed- timed PROM device follow ed by another write transaction. The CSR is assume d to be configured to the value setup=2, pulse widt h=10,[...]

150 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.7.6.4 Sin gle Read T ransfer fo r a Self-Timing Device Figure 41 demonstrates the single read transfer issu ed to a self-timing PROM device followed by another write transaction. The CSR assumed to b e programmed to the value of setup=4, pulse width=0, and ho[...]

Hardware Reference Manual 151 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.7.7.1 Mode 1: 16-Bit Microprocessor Interface Support with 16-Bit Addr ess Lines The address size control register is programmed to 16-bit address sp ace for this case. This mode is designated for the devices with the similar protocol with th e Lucent* TDA T0[...]

152 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core Figure 42. An Interface T opology with Lucent* TDA T042G5 SONET/SDH A9370-03 R/W# CS# DT# ADS# ADDR[16:0] DATA[15:0] Lucent TDAT042G5* CE# CP D[7:0] ADDR[16] ADDR[7:1] VCC Q[7:0] 74F377 CE# CP D[7:0] Q[7:0] 74F377 D[7:0] CPAB CPBA DIR OE# SAB O[7:0] SBA 74F646 D[7[...]

Hardware Reference Manual 153 Intel ® IXP2800 Network Processor Intel XScale ® Core 16-Bit Mic roprocessor Writ e Interface Protoco l Figure 43 uses the Lucent* TDA T042G5 device. In th is case, the user should program the P_PCR register to mode 1 and also program the writ e ti ming control register to setup=7, pu lse width=5, and hold=1, which r[...]

154 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core 16-Bit Microprocessor Re ad Interface Protocol Figure 44 , likewise depicts a singl e read transaction launched from the IXP2 800 Network Processor to the Lucent* TDA T042G 5 device followed by a single r ead transaction. However , in this case the read timing con[...]

Hardware Reference Manual 155 Intel ® IXP2800 Network Processor Intel XScale ® Core 3.12.7.7.2 Mode 2: Interface with 8 Dat a Bits and 1 1 Address Bit s This application is designed for the PMC- Sierra* PM5351 S/UNI-TETRA * device. For the PMC-Sierra* PM5351, the address space is programmed to 1 1 bits; otherwise, other address space should be sp[...]

156 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core PMC-Sierra* PM5351 S/UNI-TETRA* W rite Interface Protocol Figure 46 depicts a single write transaction launched from the IXP2 800 to the PMC-Sierra* PM5351 device followed by single read transaction. The write transaction for the PMC- Sierra* component has six clo[...]

Hardware Reference Manual 157 Intel ® IXP2800 Network Processor Intel XScale ® Core Figure 47 , depicts a single read transaction launched from the IXP2800 Network Processor to the PMC-Sierra* PM5351 device, followed by a single writ e transaction. In this case, there are ten clock cycles of access time, or 200 ns in tota l, with three turnaround[...]

158 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core For a write, SP_CP loads the data onto the 74 F646 (or equivalent) tri-stat e buffers, using two clock cycles. T o reduce the pin count, the 16-bit data is latched wi th the same pin (SP_CS_L[1]), assuming that a turnaround cycle is in serted between the transacti[...]

Hardware Reference Manual 159 Intel ® IXP2800 Network Processor Intel XScale ® Core Figure 49. Mode 3 Se cond Interface T opology with In tel / AMCC* SONET/SDH Device A9715-02 SP_RD_L SP_CS_L[1] SP_ACK_L SP_AD[7:0] CE# CP D[7:0] Q[7:0] 74F377 SP_WR_L E CSB INT RWB MCUTYPE ADDR[9:0] DATA[15:0] Intel ® IXP2800 Network Processor Intel ® or AMCC* S[...]

160 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core Mode 3 Wr ite Interface Protocol Figure 50 depicts a single write transaction launched from the IXP2800 Network Processor to the Intel and AMCC* SONET/SDH device, follow ed by two consecutive reads. Compared with the Lucent* TDA T042G5, this de v ice has a shorter[...]

Hardware Reference Manual 161 Intel ® IXP2800 Network Processor Intel XScale ® Core Mode 3 Read Interface Protocol Figure 51 depicts a single read transaction launched from the IXP2800 to the Intel and AMCC* SONET/SDH device, followed by two consecutive writes. Similarly , the access time is much better than the Lucent* TDA T042G5. The access tim[...]

162 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core It employs the same way to pack and unpack the data between the IXP2800 Netw ork Processor Slowport interface and the Intel an d AMCC* microprocessor interface. For a write, W2B loads the data onto t he 74F646 or equivalent tri-state buffers, using two clock cycle[...]

Hardware Reference Manual 163 Intel ® IXP2800 Network Processor Intel XScale ® Core Figure 53. Second Interfa ce T opology with Intel / AMCC* SONET/SDH Device A9719-02 SP_RD_L SP_CS_L[1] SP_ACK_L SP_AD[7:0] CE# CP D[7:0] Q[7:0] 74F377 SP_WR_L E CSB INT RWB MCUTYPE ADDR[9:0] DATA[15:0] Intel ® IXP2800 Network Processor Intel ® or AMCC* SONET/SDH[...]

164 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core Mode 4 Wr ite Interface Protocol Figure 54 depicts a single write transaction launched from the IXP2800 Network Processor to the Intel and AMCC* SONET/SDH device, follow ed by two consecutive reads. Compared with the Lucent* TDA T042G5, this de v ice has a shorter[...]

Hardware Reference Manual 165 Intel ® IXP2800 Network Processor Intel XScale ® Core Mode 4 Read Interface Protocol Figure 55 shows a single read transaction launched from th e IXP2800 Network Processor to the Intel and AMCC* SONET/SDH device, followed by two consecut ive writes. Similarly , the access time is much better than the Lucent* TDA T 04[...]

166 Hardware Reference Manual Intel ® IXP2800 Network Processor Intel XScale ® Core[...]

Hardware Reference Manual 167 Intel ® IXP2800 Network Processor Microengines Microengines 4 This section defines the Network Processor Microe ngine (ME). This is the second version of the Microengine, and is often referred to as the MEv2 (Microengine V ersion 2). 4.1 Overview The following section s describe the programmer ’ s view of the Microe[...]

168 Hardware Reference Manual Intel ® IXP2800 Network Processor Microengines Figure 56. Microengine Block Diagram B1670-01 128 GPRs (A Bank) d e c o d e 128 GPRs (B Bank) 128 Next Neighbor 128 D XFER In NNData_In (from previous ME) D_Push (from DRAM) S_Push (from SRAM Scratchpad, MSF , Hash, PCI, CAP) 128 S XFER In 640 Local Mem A_Src B_Src Immed [...]

Hardware Reference Manual 169 Intel ® IXP2800 Network Processor Microengines 4.1.1 Control Store The Control Store is a static RA M that holds the program that th e Microengine executes. It holds 8192 instructions, each of which is 40 bits wide. It is initialized by an external device that writes to Ustore_Addr and Ustore_Data Local CSRs. The Cont[...]

170 Hardware Reference Manual Intel ® IXP2800 Network Processor Microengines The Microengine is in Idle state wh enever no Context is running (all Contexts are in either Inactive or Sleep states). This state is entered: 1. After reset (because CTX_Enable Local CSR is clear, putting all Contexts into Inactive states). 2. When a context swap is exec[...]

Hardware Reference Manual 171 Intel ® IXP2800 Network Processor Microengines 4.1.3 Dat ap ath Registers As shown in the block diagram in Figure 5 6 , each Microengine contains four types of 32-bit datapath registers: • 256 General Purpose registers • 512 T ransfer registers • 128 Next Neighbor registers • 640 32-bit words of Local Memory 4[...]

172 Hardware Reference Manual Intel ® IXP2800 Network Processor Microengines T ypically , the external units access the T ransfer registers in response to commands sent by the Microengines. The commands are sent in response to instructi ons executed by the Microengine (for example, the command instru cts a SRAM controller to read from external SRA[...]

Hardware Reference Manual 173 Intel ® IXP2800 Network Processor Microengines It is also possible to make use of both or one LM_Addrs as global by setting CTX_Enable[LM_Addr_0_Glob al] and/or CTX_ Enable[LM_Addr_ 1_Global]. When used globally , all Contexts use the working copy of LM_Addr in pl ace of their own Context specific one; the Context sp [...]

174 Hardware Reference Manual Intel ® IXP2800 Network Processor Microengines 4.1.4.2 Absolute Addressing Mode W ith Absolu te addressing, any GPR can be read or wri tten by any one of the eight Context s in a Microengine. Absolute addressing enables register data to be shared among all of the Contexts, e.g., for global variables or for parameter p[...]

Hardware Reference Manual 175 Intel ® IXP2800 Network Processor Microengines Example 24 sh ows an align sequence of instructions and the value of the vari ous operands. T able 59 shows the data in the reg isters for this example. The value in Byte_Index [1:0] CSR (which controls the shift am ount) for this example is 2. Figure 58. Byte Align Block[...]

176 Hardware Reference Manual Intel ® IXP2800 Network Processor Microengines Example 25 shows another sequence of instructions and the value of the various operands. Ta b l e 6 0 , shows the data in the registers for this examp le. The value in Byte_Index[1:0] CS R (which controls the s hift am ount) for this example is 2. As the examples show , b[...]

Hardware Reference Manual 177 Intel ® IXP2800 Network Processor Microengines Note: The State bits are data associated with the entry . State bits are only used by software. There is no implication of ownership of the entry by any Co ntext. The State bits hardware function is: • the value is set by software (when the entry is lo aded or changed i[...]

178 Hardware Reference Manual Intel ® IXP2800 Network Processor Microengines One possible way t o use the result of a lo okup is to dispat ch to the proper code u sing instruction : jump[register, label#],defer [3] where the register holds the result of the lookup. The Stat e bits can be used to differentiate cases where the data associated with t[...]

Hardware Reference Manual 179 Intel ® IXP2800 Network Processor Microengines The CAM can be cleared with CAM_Clear instruction . This instruction writes 0x00000000 simultaneously to all entries t ag, clears all the state bits, and put s the LRU into an initial state (where entry 0 is LRU, ..., entry 15 is MRU). 4.4 CRC Unit The CRC Unit operates i[...]

180 Hardware Reference Manual Intel ® IXP2800 Network Processor Microengines 4.5 Event Signals Event Signals are used to coordi nate a program with completion o f external events. For example, when a Microengine issues a command to an external unit t o read data (which wil l be written into a T ransfer_In register), the program mu st insure that i[...]

Hardware Reference Manual 181 Intel ® IXP2800 Network Processor Microengines 4.5.1 Microengine Endianness Microengine op eration from an “endian” point o f view can be di vided into followi ng categories: • Read from RBUF ( 64 bits) • W rite to TBUF (64 bits) • Read/write from/to SRAM • Read/write from/to DRAM • Read/write from/to SH[...]

182 Hardware Reference Manual Intel ® IXP2800 Network Processor Microengines 4.5.1.2 Write to TBUF Data in TBUF is arranged in L WBE order . When writing from th e Microengine transfer registers to TBUF , treg0 goes into LDW0, treg1 goes into LDW1, etc. See Figure 61 . 4.5.1.3 Read/Write from/to SRAM Data inside SRAM is in big-endian order . W hil[...]

Hardware Reference Manual 183 Intel ® IXP2800 Network Processor Microengines 4.5.1.6 Write to Hash Unit Figure 62 explains 48-, 64-, and 12 8-bit hash operat ions. When the Microeng ine transfers a 48-bit hash operand to the hash unit, the operand resides in two transfer registers and is transferred, as shown in Figure 62 . In the second longword [...]

184 Hardware Reference Manual Intel ® IXP2800 Network Processor Microengines 4.5.2.1 Read from RBUF T o analyze the endianness on the media-receive in terface and the way in wh ich bytes are arranged inside RBUF , a brief introduction of how bytes are generated from the serial interface is provided here. Pipe A denotes the serial stream of data r [...]

Hardware Reference Manual 185 Intel ® IXP2800 Network Processor Microengines 4.5.2.2 Write to TBUF For writing to TBUF , the header comes from the Microengine and data comes from RBUF or DRAM. Since the Microengine to TBUF header tran sfer happened in 8-byte chunks, it is possib le that the first longword that is inside tr0 may not con tain any da[...]

186 Hardware Reference Manual Intel ® IXP2800 Network Processor Microengines Since data in RBUF or DRAM is arranged in L WBE order , it is swapped o n the way into the TBUF to make it t ruly big-endian, as shown in Figure 64 . Again, the inval id bytes at the beg inning of the payload that starts at of fset 3 a nd at the end-of-header at offset 2 [...]

Hardware Reference Manual 187 Intel ® IXP2800 Network Processor DRAM DRAM 5 This section describes R ambus* DRAM operatio n. 5.1 Overview The IXP2800 Network Processor has controllers for three Rambus* DRAM (R DRAM) channels. Either one, two, o r thr ee channels can be enabled. When more than one channel is enabled, the channels are interleaved (a[...]

188 Hardware Reference Manual Intel ® IXP2800 Network Processor DRAM 5.2 Size Configuration Each channel can be populated with 1 – 4 R DRA Ms (Short Channel Mode). For supported loading configurations, refer to T a ble 61 . The RAM technology used dete rmines the increment size and maximum memory per channel as shown in T able 62 . Note: One or [...]

Hardware Reference Manual 189 Intel ® IXP2800 Network Processor DRAM 5.3 DRAM Clocking Figure 66 shows the clock generati on for one channel (this descriptio n is just for reference; for more information, refer to Ramb us* design literature). The ot her channels use the sam e configuration. Note: Refer to Section 10 for additional information on c[...]

190 Hardware Reference Manual Intel ® IXP2800 Network Processor DRAM 5.4 Bank Policy The RDRAM Controller uses a “closed bank” polic y . Banks are activated long enough to do an access and then closed and precharged. They are not left open in anticipation of another a ccess to the same page. This is unlike many CPU applicat ions, where there i[...]

Hardware Reference Manual 191 Intel ® IXP2800 Network Processor DRAM 5.5 Interleaving The RDRAM channels are interleaved on 128-byte boundaries in hardware to improv e concurrency and bandwidth util ization. Contiguo us addresses are directed to dif ferent channels by rearranging the physical address bits in a programm able manner described in Sec[...]

192 Hardware Reference Manual Intel ® IXP2800 Network Processor DRAM T able 63. Address Rearrangement for 3-W ay Interleave (She et 1 of 2) When these bits of address are all “1”s… 1 Shift 30:7 right by this many bit s Add this amount to shifted 30:7 (based on amount of m emory on the chan nel) Address within channel is {30:7+table_value), 6[...]

Hardware Reference Manual 193 Intel ® IXP2800 Network Processor DRAM T able 64. Address Rearrangement for 3-W ay Interleave (Sheet 2 of 2) (Rev B) 5.5.2 T wo Channels Active (2-W ay Interleave) It is possible to have only two channels populated for system cost and ar ea savings. If only two channels are desired, than channels 0 and 1 s h ould be p[...]

194 Hardware Reference Manual Intel ® IXP2800 Network Processor DRAM 5.5.4 Interleaving Acro ss RDRAMs and Banks In addition to interleaving acros s the different RDRAM channels, addresses are also interleaved across RDRAM chips and internal banks. This imp r oves utilization since cer tain operations to different banks can be performed concurrent[...]

Hardware Reference Manual 195 Intel ® IXP2800 Network Processor DRAM 5.6.2 Parity Enabled On writes, odd byte parity is computed for each byt e and written into the co rresponding parity bit. Partial writes (writes of less than eight bytes) are done as masked writes. On reads, odd byte parity is computed on each by te of data and compared to the c[...]

196 Hardware Reference Manual Intel ® IXP2800 Network Processor DRAM T o avoid the detection of fals e ECC errors, the RDRAM ECC mode must be initialized using the procedure described below: 1. Ensure that parity/ECC is not enabled: program DRAM_CTRL[15:14] = 00 2. W rite all zeros (0x00000000) to all the m emory locations. By default, this initia[...]

Hardware Reference Manual 197 Intel ® IXP2800 Network Processor DRAM 5.8 Microengine Signals Upon completion of a read or wr ite, the RDRAM controller can signal a Microengine context, when enabled. It does so using the sig_done token; see Example 27 . Because the RDRAM address space is interleav ed, consecutive accesses can go to different RDRAM [...]

198 Hardware Reference Manual Intel ® IXP2800 Network Processor DRAM Serial r eads are done by the followin g steps: 1. Read RDRAM_Serial_Comma nd; test Busy bit until i t is a 0. 2. W rite RDRAM_Serial_Command to start the read. 3. Read RDRAM_Serial_Comma nd; test Busy bit until i t is a 0. 4. Read RDRAM_Serial_Data to co llect the serial re ad d[...]

Hardware Reference Manual 199 Intel ® IXP2800 Network Processor DRAM 5.10.1 Commands When a valid command is placed on the command bus, the co ntrol logic checks to see if the address matches the channel’ s address range, based on interleaving as described in Section 5.5 . The command, address, length, etc. are enqueued into the command Inlet FI[...]

200 Hardware Reference Manual Intel ® IXP2800 Network Processor DRAM 5.10.3 DRAM Read When a read (or TBUF_WR, which does a DRAM read) command is at the head of the Command Inlet FIFO, it is moved to the proper Bank CMD FIFO if there is room. If there is not enough room in the Bank’ s CMD FIFO, the read command wait s at the head of th e Command[...]

Hardware Reference Manual 201 Intel ® IXP2800 Network Processor DRAM 5.10.6 Arbitration The channel needs to arbitrate am ong several dif ferent operations at RMC. Arbitration rules are given here for those cases: from highest to lowest priori ty: • Refresh RDRAM. • Current calibrate RDRAM. • Bank operations. When there are multiple bank ope[...]

202 Hardware Reference Manual Intel ® IXP2800 Network Processor DRAM • Supports chaining for bu rst DRAM push operations t o tell the arbiter to grant co nsecutive push requests. • Supports data error bit handling and delivery . Figure 71 shows the functional blocks for the DRAM Push /Pull Arbiter . 5.1 1.1 Arbiter Push/Pull Operation W ithin [...]

Hardware Reference Manual 203 Intel ® IXP2800 Network Processor DRAM 5.1 1.2 DRAM Push Arbiter Description The general data flow for a push operation is as shown in T able 68 . The DRAM Push Arbiter functional blocks are shown in Figure 72 . The push arbiter takes push requests from any reque stors. Each requestor has a dedicated request FIFO. A r[...]

204 Hardware Reference Manual Intel ® IXP2800 Network Processor DRAM The DRM Push Arbiter boundary conditions are: • Make sure each of the push_request queues as sert the full signal and back pressure the requesting unit. • Maintain 100% bus utilization, i.e., no holes. 5.12 DRAM Pull Arbiter Description The general data flow for a push operat[...]

Hardware Reference Manual 205 Intel ® IXP2800 Network Processor DRAM When a requestor gets a pull command on the CMD_ BUS, the requestor sends the command to the pull arbiter . This is enqueued into a requestor -dedicated FIFO. The pull request FIFOs are much smaller than the push request FIFOs because pull reques ts can request up to 1 28 bytes o[...]

206 Hardware Reference Manual Intel ® IXP2800 Network Processor DRAM[...]

Hardware Reference Manual 207 Intel ® IXP2800 Network Processor SRAM Interface SRAM Interface 6 6.1 Overview The IXP2800 Network Processor c ontains four i ndependent SRAM controllers. SRAM controllers support pipelined QDR synchron ous static RAM (S RAM) and a coprocessor that adheres to QDR signaling. Any or all controllers can be left unpo pula[...]

208 Hardware Reference Manual Intel ® IXP2800 Network Processor SRAM Interface 6.2 SRAM Interface Configurations Memory is logically four bytes (one longword ) wide while physically , the data pins are tw o bytes wide and double-clocked. Byte parity is supported. Each of the four bytes ha s a parity bit, which is written when the byte is written a[...]

Hardware Reference Manual 209 Intel ® IXP2800 Network Processor SRAM Interface In general, QDR and QDR II bursts of two SRAMs are supported at speeds up to 233 MHz. As other (larger) QDR SRAMs are introdu ced, they will also be supported. The SRAM controller can also be configured to inte rface to an external coprocessor that adheres to the QDR or[...]

210 Hardware Reference Manual Intel ® IXP2800 Network Processor SRAM Interface Each channel can be expanded in depth according to the number of port enables available. If external decoding is used, then the number of SRAMs is not limited by the number of port enables generated by the SRAM control ler . Note: External decoding may re quire external[...]

Hardware Reference Manual 211 Intel ® IXP2800 Network Processor SRAM Interface A side-effect of the pipeline registers is to add latency to reads, and the SRAM controller must account for that delay by waiting extra cycles (relat ive to no external pipeline reg isters) before it registers the read data. The number of ex tra pipeline delays is pro [...]

212 Hardware Reference Manual Intel ® IXP2800 Network Processor SRAM Interface Up to two Microengine signals are assigned to each read-modify -write reference. Microcode should always tag the read-modify-write referen ce with an e ven-numbered signal. If the operation requires a pull, the requested signal is sent on the pull . If the pre-modified [...]

Hardware Reference Manual 213 Intel ® IXP2800 Network Processor SRAM Interface 6.4.3 Queue Dat a Structure Commands The ability to enqueue and dequeue data buffers at a fast rate is key to meeting chip performance goals. This is a difficult problem as it involves dependent memory references that must be turned around ver y quickly . The SRAM cont [...]

214 Hardware Reference Manual Intel ® IXP2800 Network Processor SRAM Interface The ENQ_tail_and_link command followed by ENQ_tail enqueue a pr eviously linked string of buffers. The string of buffers is used in the case where one packet is too la rge to fit in one buffer . Instead, it is divided among multiple buffers. Figure 79 is an example of a[...]

Hardware Reference Manual 215 Intel ® IXP2800 Network Processor SRAM Interface There are two different modes for the dequeue command. One mode re moves an entire buf fer from the queue. The second mode removes a piece of the buf fer (referred to as a cell). The mode (cell dequeue or buffer dequeue) is selectable on a buffer -by-buffer basis by set[...]

216 Hardware Reference Manual Intel ® IXP2800 Network Processor SRAM Interface Note: For a Ring or Journal, Head and Tail must be initialized to the same address. Journals/Rings can be configured to be one of eight sizes, as shown in T abl e 75 . The following sections contain pseudo-co de to describe the operation of the various queue and rin g i[...]

Hardware Reference Manual 217 Intel ® IXP2800 Network Processor SRAM Interface 6.4.3.3 ENQ and DEQ Commands These commands add or remove element s from the queue structure while updating the Q_array registers. Refer to the sections, “SRAM (En queue)” and “SRAM (Dequeue)”, in the IXP2400 and IXP2800 Network Pr ocessor Programmer ’ s Ref e[...]

218 Hardware Reference Manual Intel ® IXP2800 Network Processor SRAM Interface Note: If incorrect parity is detected on the read portion of an atomic read-modify-write , the incorrect parity is preserved after the w rite (that is, the byte(s) wi th bad parity during the read will have incorrect parity writt en during the write). When parity is use[...]

Hardware Reference Manual 219 Intel ® IXP2800 Network Processor SRAM Interface 6.7 Reference Ordering This section describes the or dering between accesses to any one SRAM controller . V arious mechanisms are used to guarantee order — for ex ample, references that always go to the same FIFOs remain in order . Ther e is a CAM associated with writ[...]

220 Hardware Reference Manual Intel ® IXP2800 Network Processor SRAM Interface 6.7.2 Microcode Restriction s to Maint a in Ordering The microcode programmer must ensure order wher e the program flow requires order and where the architecture does not guarantee that order . On e mechanism that can be used to do this is signaling. For example, if the[...]

Hardware Reference Manual 221 Intel ® IXP2800 Network Processor SRAM Interface Other microcode rules: • All access to atomic variables should be through read-modify- write instructions. • If the flow must know that a write is completed (actually in the SRAM itself), follow the write with a read to the same address. The write is gua ranteed to [...]

222 Hardware Reference Manual Intel ® IXP2800 Network Processor SRAM Interface The external coprocesso r interface is based on FIFO communication. A thread can send parameters to the coprocesso r by doi ng a normal SR AM write instructio n: sram[write, $sram_xfer_reg, src1, src2, ref_count], optional_token The number of parameters (longwords) pass[...]

Hardware Reference Manual 223 Intel ® IXP2800 Network Processor SRAM Interface There can be multiple operatio ns in progress in the coprocessor . The SRAM cont roller sends parameters to the coprocessor in response to each SRAM write instruc tion without waiting for return results of previous writes. If the coproces so r is capable of re-o rd erin[...]

224 Hardware Reference Manual Intel ® IXP2800 Network Processor SRAM Interface[...]

Hardware Reference Manual 225 Intel ® IXP2800 Network Processor SHaC — Unit Expansion SHaC — Unit Expansion 7 This section covers the operation of the Scratchpad, Hash Unit, and CSRs (SHaC). 7.1 Overview The SHaC unit is a multifunction block contai ning Scratchpad memory and logic bl ocks used to perform hashing operations and interface with [...]

226 Hardware Reference Manual Intel ® IXP2800 Network Processor SHaC — Unit Expansion Figure 84. SHaC T op Level Diagram A9751-03 Scratch RAM (4 K x 32) Scratch/CAP Control Logic Intel XScale ® Core SH_APB_CTL SH_APB_WR_DATA XP_RD_DATA TAXX_CMD_BUS_B SH_CMDQ_FULL SH_PULL_CMD SP0_PULL_DATA SP1_PULL_DATA SP0_PULLQ_FULL SP1_PULLQ_FULL SP0_TAKE_DAT[...]

Hardware Reference Manual 227 Intel ® IXP2800 Network Processor SHaC — Unit Expansion 7.1.2 Scratchp ad 7.1.2.1 Scratchp ad Description The SHaC Unit contains a 16-Kbyte Scratchpad memory , or ganized as 4K 32-bit words, that is accessible by the Intel XScale ® core and Microengines. The Scra tchpad connects to the internal Command, S_Push and [...]

228 Hardware Reference Manual Intel ® IXP2800 Network Processor SHaC — Unit Expansion Figure 85. Scratchp ad Block Diagram A9756-02 Scratchpad State Machine CSR_CONTROL_SIGNALS APB_CONTROL_SIGNALS SH_PUSH_ID SH_PULL_ID CSR_FAST_WR_DATA TA_CMD_ BUS_B SH_PULL_LEN SP0_PULLQ_FULL SP1_PULLQ_FULL APB_READ_DATA (from Intel XScale ® Core CSR_READ_DATA [...]

Hardware Reference Manual 229 Intel ® IXP2800 Network Processor SHaC — Unit Expansion 7.1.2.2 Scratchp ad Interface Note: The Scratchpad command and S_Push and S_Pull bus interfaces actually are shared with the Hash Unit. Only one command, to either of those units, can be accepted per cycle. The CSR and APB buses are described in detail in the f[...]

230 Hardware Reference Manual Intel ® IXP2800 Network Processor SHaC — Unit Expansion If the Command Inlet FIFO becomes fu ll, the Scratchpad controller sends a full signal to the command arbiter that prevents it from sen ding further Scratchpad commands. 7.1.2.3. 1 Scratchpad Commands The basic read and write commands transfer from 1 – 16 l o[...]

Hardware Reference Manual 231 Intel ® IXP2800 Network Processor SHaC — Unit Expansion When the RMW command reaches the head of the Command pipe, the Scratchpad reads the memory location in the RAM . If the source requests the pre-mo dified data (T oken[0] set), it is sent to the Push Arbiter at the time of the read. If the RMW requires pull da t[...]

232 Hardware Reference Manual Intel ® IXP2800 Network Processor SHaC — Unit Expansion Head, T ail, Base, and Size are registers in the Sc ratchpad Unit. Head and T ail point to the actual ring data, which is stored in th e Scratchpad RAM. For each ring in use, a region of Scratchpad RAM must be reserved for t he ring data. The reservati on is by[...]

Hardware Reference Manual 233 Intel ® IXP2800 Network Processor SHaC — Unit Expansion The ring commands operate as outlined in th e pseudo-code in Example 32 . The operations are atomic, meaning that mult i-word “Gets” and “Puts” do all the reads and writes, with no other intervening Scratchpad accesses. Prior to using the Scratchpad rin[...]

234 Hardware Reference Manual Intel ® IXP2800 Network Processor SHaC — Unit Expansion For writes using the Reflector mode , Scratchpad arbitrates for the S_ Pull_Bus, pull s the write data from the source identified in the instruction (either a Microengine transfer register or an Intel XScale ® core write buffer), and puts it into one of the Pu[...]

Hardware Reference Manual 235 Intel ® IXP2800 Network Processor SHaC — Unit Expansion 7.1.2.3.3 Clocks and Rese t Clock generation and distributi on is handled outside of CAP and is dependent on the specific chip implementation. Separate clock rates are required for CAP CSRs/Push/Pull Buses and ARB since APB devices tend to run slower . CAP prov[...]

236 Hardware Reference Manual Intel ® IXP2800 Network Processor SHaC — Unit Expansion 7.1.3 Hash Unit The SHaC unit contains a Hash Unit that can take 48-, 64-, or 128-bit data and pro duce a 48-, 64-, or a 128-bit hash index, respectively . The Hash Unit is accessible by the Microengines and the Intel XScale ® core. Figure 87 is a block diagra[...]

Hardware Reference Manual 237 Intel ® IXP2800 Network Processor SHaC — Unit Expansion 7.1.3.1 Hashing Operation Up to three hash indexes (see Example 33 ) can be created by using one Microengine instruction. A Microengine initiates a hash op eration by writi ng a contiguous set of SRA M T ransfer registers and then executing the hash instru ctio[...]

238 Hardware Reference Manual Intel ® IXP2800 Network Processor SHaC — Unit Expansion The Intel XScale ® core initiates a hash operation by writing a set of memory- mapped Hash Operand registers (which ar e built into the Intel XScale ® core gasket) with the data to be used to generate the hash index. There are separate registers for 48-, 64-,[...]

Hardware Reference Manual 239 Intel ® IXP2800 Network Processor SHaC — Unit Expansion The Hash Unit shares the Scratchp ad’ s Push Data FIFO. After each hash index is completed, the index is placed into a three-stage output pipe and the Hash Unit sends a PUSH_DA T A_REQ to the Scratchpad to indicate that it has a valid h ash index to put into [...]

240 Hardware Reference Manual Intel ® IXP2800 Network Processor SHaC — Unit Expansion Equation 7. (48-bi t hash oper ation) Equation 8. (64-bi t hash oper ation) Equation 9. (128-bit h ash operation) The division results in a quotient Q(x), a polyno mial of order-46, order -62, or order-126, and a remainder R(x), and a polynomial of order-47, or[...]

Hardware Reference Manual 241 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface Media and Switch Fabric Interface 8 8.1 Overview The Media and Switch Fabric (MSF) Interface c onnects the IXP2800 Netw ork Processor to a physical layer device (PHY) and/or to a Switch Fa bric. The MSF co nsists of separate receive and transmit inter[...]

242 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The use of some of the receive and transmit pins is based on protocol, SPI-4 or CS IX. For the L VDS pins, only the active high name is given (f or L VDS, there are two pins per signal). The definitions of the pi ns can be found in the SPI-4 and CSIX [...]

Hardware Reference Manual 243 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.1.1 SPI-4 SPI-4 is an interface for packet and cell transfer between a physi cal layer (PHY) device and a link layer device (the IXP2800 N etwork Processor), for aggregate b andwidths of OC-1 92 A TM an d Packet over SONET/SDH (POS), as well as 10 G[...]

244 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface Control words are inserted only between burst tran sfers; once a transfer has begun, data words are sent uninterrupted until eith er End of Packet or a multipl e of 16 bytes is reached. The ord er of bytes within the SPI-4 data burst is shown in T abl[...]

Hardware Reference Manual 245 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface T able 84 shows th e order of bytes on SPI-4; this example shows a 43-byte packet. Figure 90 shows two wa ys in which the SPI-4 clockin g can be done. Note that it is also possible to use an internally-supp lied clock and leave TCLK_REF unused. T able[...]

246 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.1.2 CSIX CSIX_L1 (Common Switch Interface) defines an interface between a Traf fic Manager (TM) and a Switch Fabric (SF) for A TM, IP , MPLS, Ethernet , and similar data comm unications applications. The Network Processo r Forum (NPF) www .npfor um.[...]

Hardware Reference Manual 247 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.2 Receive The receive section consists of: • Receive Pins ( Section 8.2.1 ) • Checksum ( Section 8 .2.2 ) • Receive Buffer (RBUF) ( Section 8.2.2 ) • Full Element List ( Section 8.2.3 ) • Rx_Thread_Freelist ( Section 8.2.4 ) • Flow Contr[...]

248 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.2.1 Receive Pins The use of the receive pins is a f unction of RPROT input, as shown in Ta b l e 8 6 . In general, hardware does framing, parity checking, and flow control message handling. Interpretation of frame header and payload data is done by [...]

Hardware Reference Manual 249 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The data in each partition is further broken up into elemen ts, based on MSF_Rx_Control[RBU F_Element_Size_#] (n = 0, 1, 2). There are three choices of element size – 64, 128, or 256 b ytes. T able 89 shows the RBUF partition options. Not e that the[...]

250 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The src_op_1 and src_op_2 operands are added together to fo rm the addres s in RBUF (note that the base address of the RBUF is 0x2000). The ref_cnt operand is the num ber of 32-bit words or word pairs, that are pushed into t wo sequent ial S_TRANSFER_[...]

Hardware Reference Manual 251 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface Section 8.2.7.1 ). The SPI-4 Control W ord T ype, EO PS, SOP , and ADR fields are placed into a temporary status register . The Byte_Count field of the el ement status i s set to 0x0. As each Data W ord is received, the data is wr itten into the eleme[...]

252 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The status contains th e following information: The definitions of the fields are shown in T able 90 . 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RPROT Element Byte Count SOP EOP Err Len Err Par [...]

Hardware Reference Manual 253 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.2.2.2 CSIX CSIX CFrames are placed into eith er RBUF or FCEFIFO as follows: At chip reset, all RBUF elem ents are marked invalid (ava ilable) and FCEFIFO is empty . When a Base Header is sent (i.e., when RxSof is asserted) it is placed in a temporar[...]

254 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface Note: In CSIX protocol, an RBUF element is alloca ted only on RxSof assertion. Therefore, the element size must be programmed based on the Switch Fabric usage. For example, if the switch never sends a payload greater than 128 bytes, then 128-byte elem[...]

Hardware Reference Manual 255 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.2.3 Full Element List Receive control hardware maintains the Full El ement List to hold th e status of valid RBUF elements, in the order in which they were received. When an element is marked valid (as described in Section 8.2.2.1 for SPI-4 and Sect[...]

256 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.2.5 Rx_Thread_Freelist_Timeout_# Each Rx_Thread_Fr eelist_# has an associated countdown timer . If the timer expires and no new receive data is available yet, the receive logic will autopush a Null Receive S tatus W ord to the next thread on the Rx_[...]

Hardware Reference Manual 257 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface When an mpacket becomes valid as described in Section 8.2.2.1 for SPI-4 and Section 8.2.2.2 for CSIX, receive control logic will autopush eight bytes of information for the element to the Microengine/Context/S_Transfer registers at the head of Rx_Thre[...]

258 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface Ta b l e 9 3 summarizes the dif ferences in RBUF operation betw een th e SPI-4 and CSIX protocols. 8.2.7 Receive Flow Control St atus Flow control is handled in hardware. Ther e are specific functions for SPI-4 and CSIX. 8.2.7.1 SPI-4 SPI-4, FIFO stat[...]

Hardware Reference Manual 259 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface When MSF_RX_CONTROL[RX_Calendar_Mode] is set to Force_Override , the value of RX_POR T_CALENDAR_ST A TUS_# is used to determine which statu s value is sent. If RX_POR T_CALENDAR_ST A TUS_# is set to 0x3, then the global status value set in MSF_RX_CONT[...]

260 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.2.7.2. 2 Virtual Output Queue CSIX protocol provides V irtual Ou tput Queue Flow Control via Flow Control CFrames. CFrames that were mapped to FCEFIFO (via the CSIX_T ype_Ma p CSR) are parsed by the receive control logic and placed into FCEFIFO, whi[...]

Hardware Reference Manual 261 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.2.8.2 CSIX 8.2.8.2.1 Horizont al Parity The receive logic computes Horizo ntal Parity on each 16 bits of each received Cword (there is a separate parity for data received on ri sing and falling edge of the clock). There is an internal HP Error Flag [...]

262 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.3 T ransmit The transmit section consists of: • Tr a n sm i t P i ns ( Section 8.3.1 ) • T ransmit Buffer ( Section 8.3.2 ) • Byte Aligner ( Section 8.3.2 ) Each of these is described below . Figure 94 is a simplified block diagra m of the MSF[...]

Hardware Reference Manual 263 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.3.2 TBUF The TBUF is a RAM that holds data and status to be transmitted. The data is written into sub- blocks referred to as elements, by Microengine or the Intel XScal e ® core. TBUF contains a total of 8 Kbytes of data, an d associated control. T[...]

264 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface Ta b l e 9 7 shows the TBUF partition options. Not e that the choice of element size is independent for each partition. The Microengine can write data from Microengine S_TRANSFER_OUT registers to the TBUF using the msf[write] instruction, where they s[...]

Hardware Reference Manual 265 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface Payload Offset — Number of bytes to skip from th e last 64-bit word of the Prepend to the start of Payload. The absolute byte number of the first byt e of Payload in the element is: ((Prepend Offset + Prepend Length + 0x7) && 0xF8) + Payload[...]

266 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.3.2.1 SPI-4 For SPI-4, data is put into the data portion of the element, and informat ion for the SPI-4 Control W ord that will precede the data is put into the Element Control W ord. When the Element Control W ord is written the informati on is (th[...]

Hardware Reference Manual 267 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.3.2.2 CSIX For CSIX protocol, the TBUF should be set to two partitions in MSF_Tx_Contr ol[TBUF_Partition] , one for Data traffic and one for Control traffic. Payload information is put into the Payload area of the element, and Base and Extension Hea[...]

268 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.3.3 T ransmit Operation Summary During transmit processing data to be transmi tted is placed into the TBUF under Microengine control, which allocates an elem ent in software. The transmit hard ware processes TBUF elements within a partition, in stri[...]

Hardware Reference Manual 269 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface If the next sequential element is not valid wh en its turn comes up: 1. Send an idle Control W ord with SOP set to 0, and EOPS set to the val ues determined from the most recently sent el ement, ADR field 0x00, correct parity . 2. Until an element bec[...]

270 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface Note: A Dead Cycle is any cycle after the end of a CFrame, and prior to the start of another CFrame (i.e., SOF is not asserted). The end of a CFrame is defined as after the V ertical Parity has been transmitted. This in turn is found by count ing the [...]

Hardware Reference Manual 271 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.3.4.1 SPI-4 FIFO status inform ation is sent pe riodically over the TST A T si gnals from the PHY to the Link Layer device, which is the IXP2800 Network Processor . (The RXCDA T pins can act as TST A T based on the MSF_Tx_Control[TST A T_Select] bit[...]

272 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The TX_Port_S tatus_# or the TX_Multiple_Port_S tatus_# registers must be read by the software to determine the status of each port a nd send data to them accord ingly . The MSF hardware does not check these registers for port status before sending da[...]

Hardware Reference Manual 273 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.3.4.2 CSIX There are two types of CSIX flow control: • Link-level • V irtual Output Queue (V OQ) 8.3.4.2.1 Link-Level The Link-level fl ow control function is done via hard ware and consists o f two parts: 1. Enable/disable transmissi on of vali[...]

274 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.3.5.2 CSIX 8.3.5.2. 1 Horizon tal Parity The transmit logic computes odd Horizontal Parity for each tr ansmitted 16-bits of each Cword, and transmits it on TxPar . 8.3.5.2. 2 V ertical Parity The transmit logic computes V e rtical Parity on CFrames.[...]

Hardware Reference Manual 275 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.5 CSIX Flow Control Interface This section describes th e Flow Control Interface. Section 8.2 and Section 8.3 of this chapter also contain descriptio ns of how those functions in teract with Flow Co ntrol. There are two modes — Full Duplex, where [...]

276 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The information transmitted on TXCSRB can be read in FC_Egress_S tatus CSR, and the information received on RXCSRB can be read in FC_Ingress_S tatus CSR. The TXCSRB or RXCSRB signals carry the Ready inform ation in a serial stream. Four bits of data a[...]

Hardware Reference Manual 277 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.5.2.1 Full Duplex CSIX In Full Duplex Mode, the inform ation from the Switch Fabric is sen t to the Egress IXP2800 Network Processor and must be communicated to the Ingress IXP2800 Netw ork Processor via TXCSRB or RXCSRB. CSIX CFrames received fr om[...]

278 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The FCIFIFO supplies two signals to Microe ngines, which can be tested using the BR_ST A T E instruction: 1. FCI_Not_Empty — indicates that there is at least one CW ord in the FCIFIFO. This signal stays asserted until all CW ords ha ve been read. (N[...]

Hardware Reference Manual 279 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The TXCSRB and RXCSRB pins are not used in Simplex Mode. The RXCFC and TXCFC pins are used for flow control in both Simplex and Duplex Modes. The Egress IXP2800 Network Processor uses the TXCSOF , TXCDA T , and TXCP AR pins to send CFrames to the Swit[...]

280 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.5.3 TXCDA T/RXCDA T , TXCSOF /RXCSOF , TXCP AR/RXCP AR, and TXCFC/RXCFC Signals TXCDA T and RXCDA T , along with TXCSOF/RXCSOF and TXCP AR/RXCP AR are used to send CSIX Flow Control in formation from the Egre ss IXP28 00 Network Pro cessor to the In[...]

Hardware Reference Manual 281 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The IXP2800 Network Processor suppo rts all three methods. There are thr ee group s of high-speed pins to which this applies, as shown in Ta b l e 1 0 4 , Ta b l e 1 0 5 , and Ta b l e 1 0 6 . The groups are defined by the clock signal that is used. T[...]

282 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.6.1 Dat a T raining Pattern The data pin training sequence is show n in T able 107 . This is a superset of SPI-4 training sequence, because it includes the TP AR/R P AR and TPROT/RPOT pins, which are not included in SPI-4. 8.6.2 Flow Control T raini[...]

Hardware Reference Manual 283 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The training sequence when the pins are used for SPI-4 Status Channel is shown in Ta b l e 1 0 9 . This is compatible to SPI-4 training sequence. 8.6.3 Use of Dynamic T raining Dynamic training is done by cooperation of hardware and software as define[...]

284 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The second case is when the Switch Fabric or SPI-4 framing device indicates it needs Data training. T a bl e 111 lists that sequence. T able 1 10. IXP2800 Network Processor Requires Dat a T raining Step SPI-4 (IXP2800 Network Processor is Ingress Devi[...]

Hardware Reference Manual 285 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The IXP2800 Network Processor need s training at re set, or whenever it loses train ing. Loss of training is typically detect ed by parity errors on recei ved flow control information. T able 1 1 1. Switch Fabric or SPI-4 Framer Req uires Data T raini[...]

286 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface Ta b l e 1 1 2 lists the steps to initiate the traini ng. CSIX Full Duplex and CSIX Simplex cases follow similar , but slightly different sequences. The last case is when the Switch Fabric i ndicates it needs Flow Control train ing. T able 1 13 lists [...]

Hardware Reference Manual 287 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.7 CSIX St artup Sequence This section defines the sequence requ ired to startup the CSIX interface. 8.7.1 CSIX Full Duplex 8.7.1.1 Ingress IXP2 800 Network Processor 1. On reset, FC_ST A TUS_OVERRIDE[Egress_Force_En ] is set to force the Ingress IXP[...]

288 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.7.1.3 Single IXP 2800 Network Processor 1. The Microengine or the Intel XScale ® core writes a 1 to MSF_Tx_Control [T ransmit_Idle] and MSF_Tx_Control[T ransmit_En able] so that Id l e CFrames with low CReady and DReady bits are sent over TDA T . 2[...]

Hardware Reference Manual 289 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.7.2.2 Egress IXP2800 Network Processor 1. On reset, FC_ST A TUS_OVERRI DE[Ingress_Force_En] is set. 2. The Microengine or the Intel XScale ® core writes a 1 to MSF_Tx_Control[Transmit_Idle] and MSF_Tx_Control[Transmit_Enable] so that Idle CFrames w[...]

290 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.8 Interface to Command and Push and Pull Buses Figure 100 shows the interface of the MSF to the comm and and push and pull buses. Data transfers to and from the TBUF/RBUF are done in the following cases (refer to section): • RBUF or MSF CSR to Mic[...]

Hardware Reference Manual 291 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.8.1 RBUF or MSF CSR to Microengine S_TRANSFER_IN Register for Instruction: msf[read, $s_xfer_reg, src_op_1, src_op_2, ref_cnt], optional_token For transfers to a Microengine, the MSF acts as a tar get. Commands from Microengines and the Intel XScale[...]

292 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.8.5 From DRAM to TBUF for Instruction: dram[tbuf_wr, --, src_op1, src_op2, ref_cnt], indirect_ref For the transfers from DRAM, the TB UF acts like a slave. The address of the data to be written is given in D_PUSH_ID . The data is registered an d ass[...]

Hardware Reference Manual 293 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface SPI-4.2 supports up to 256 port a ddresses, with independent flow control for each. For dat a received by the PHY and passed to the link layer devi ce, flow control is optional. The flow control mechanism is based upon independe nt pools of credits, c[...]

294 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The SPI-4.2 mode of the simplex configuration supports an L VTTL reverse path or status interface clocked at up to 125 MHz or a DDR L VDS reverse path or status interface clocked at up to 500 MHz. The SPI-4.2 mode status interface consists of a clock [...]

Hardware Reference Manual 295 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.1.3 Dual Network Processo r Full Duplex Configuration In the dual Network Processor, full dupl ex conf iguration, an ingress Network Processo r and an egress Network Processor are integr ated to offer a single full duplex interface to a fabric, si[...]

296 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.1.4 Single Network Pr ocessor Full Duplex Co nfiguration (SPI-4.2) The single Network Processor , full duplex conf iguratio n (SPI-4.2 only) allows a single Network Processor to interface to multiple discrete devices, processing both the receiver [...]

Hardware Reference Manual 297 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.1.5 Single Network Processo r , Full Duplex Configuration (SPI-4.2 and CSIX-L1) The Single Network Processor, Full Duplex Config uration (SPI-4.2 and CSIX-L1 Protoc ol) allows a single Network Processor to interface to a fabr ic via a CSIX-L1 inte[...]

298 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.2.1 Framer , Single Network Pr ocessor Ingress and Egress, an d Fabric Interface Chip Figure 107 illustrates the baseli ne system configuration con sisting of the dual chip, ful l-duplex fabric configuration of network processors with a framer chi[...]

Hardware Reference Manual 299 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.2.3 Framer , Single Network Pr ocessor Ingress and Egress, and CSIX-L1 Chip s for T ranslation and Fabric Interface T o interface to existing standard CSIX-L1 fabric interface chips, a translation bridge can be employed, as shown in Figure 109 . T[...]

300 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.2.5 Framer , Single Networ k Processor , Co-Processor , and Fabric Interface Chip The network processor support s multiplexing t he SPI-4.2 and CSIX-L1 protocols over it s physical interface via a protocol signal. This capability enables using a b[...]

Hardware Reference Manual 301 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.3 SPI-4.2 Support Data is transferred across the SPI-4.2 interface in variously-sized bursts and encapsulated with a leading and trailing control word . The control words provide annotation of the data with port address (0-255) in formation, start[...]

302 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface As threads complete processing of the data in a buffer , the buffer is returned to a free list. Subsequently , the thread also returns to a separate free list. The return of buf fers and threads to the free lists may occur in a dif ferent or der than [...]

Hardware Reference Manual 303 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.4 CSIX-L1 Protocol Support 8.9.4.1 CSIX-L1 Interface Reference Model: T raffic Manager and Fabric Interface Chip The CSIX-L1 protocol operates between a T raffic Manger and a Fabric Interface Chip(s) across a full-duplex interface. It supports mec[...]

304 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface Information is passed across the interface in CFrames. CFrames are padded out to an integer multiple of CW ords. CFrames consist of a 2- byte base header, an optional 4-byte ext ension header , a payload of 1 to 256 bytes, padding, and a 2-byte vertic[...]

Hardware Reference Manual 305 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The network processor supports a vari ation of the standard CSIX-L1 vertical parity . Instead of a single vertical XOR for the calculation of the vertical parity , the network processor can be configured to calculate as DI P-16 code, as docume nted wi[...]

306 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The backpressure signal (TXCFC, RXCFC) is an asynchronous signal and is asserted by the ingress network processor to prevent overfl ow of the ingress network p rocessor ingress flow control FIFO. If the egress network processor is so optionally con fi[...]

Hardware Reference Manual 307 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The transfer time of CFrames acros s the RPCI is fo ur times that of the da ta interface. The latency of link-level flow control notifi cations depends on the frequency of sending new CFrame base headers. As such, the maximum size of CFrames suppo rte[...]

308 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The SPI-4.2 interface does not support a virtua l output queue (VOQ) flow control mechanism. The Intel ® IXP2800 Network Processor supports use of the CSIX-L1 protocol-based flow contro l interface (as used in the dual chip, full-duplex co nfiguratio[...]

Hardware Reference Manual 309 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface The training pattern for the flow control data signals consists of 10 nibbles of 0xc followed by 10 nibbles of 0x3. The parity and serial “ready bits” signal is de-asserted for the fi rst 10 nibbles and asserted for the second 10 nibbles. The star[...]

310 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.4.4 CSIX-L1 Protoc ol T ransmitter Support The Intel ® IXP2800 Network Processor transmitter suppo rt for the CSIX-L1 protoco l is similar to that for SPI-4.2. The transmitter fet ches CFrames from transmitter buffers. An entire CFrame must fit w[...]

Hardware Reference Manual 311 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.4.5 Implement ation of a Bridge Chip to CSIX-L1 The Intel ® IXP2800 Network Processor support fo r the CSIX-L1 protocol in the dual chip, full- duplex configuration minimi zes the difficulty in implementing a brid ge chip to a standard CSIX-L1 in[...]

312 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.5 Dual Protocol (SPI and CSIX-L1) Support In many system designs that ar e less bandwidth-intensive, a singl e network processor can forward and process data from the framer to the fabric and from the fabr ic to the framer . A bridge chip must pas[...]

Hardware Reference Manual 313 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.5.3 Implement ation of a Bridge Chip to CSIX-L1 and SPI-4.2 A bridge chip can provide support for bot h standard CSIX-L1 and standard physical layer device interfaces such as SPI-3 or UTOPIA Level 3. The bridge chip must implem ent the functionali[...]

314 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.6 T ransmit St ate Mach ine Ta b l e 1 1 4 describes the transmit ter state machine by providin g guidance in interfacing to the network processor . The state machine is described as three separate state machines for SPI-4.2, training, and CSIX-L1[...]

Hardware Reference Manual 315 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.6.2 T raining T ransm itter St ate Machine The T raining State Machine makes st ate transitions on each bus transfer of 16 bits, as described in T able 1 15 . 8.9.6.3 CSIX-L1 T ransmitter St ate Machine The CSIX-L1 T ransmit State Machine makes st[...]

316 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.7 Dynamic De-Skew The Intel ® IXP2800 Network Processor supports optiona l dynamic de-skew for the signals of th e 16-bit data interface and th e signals of the 4-bit flow control interface or the signals of the 2-bit SPI-4.2 L VDS status in terf[...]

Hardware Reference Manual 317 Intel ® IXP2800 Network Processor Media and Switch Fabric Interface 8.9.8 Summary of Receiver and T ransmitter Signals Figure 1 1 7 summarizes the Receiver and T ransmitter Signals. Figure 1 17. Summary of Receiver and T ransmitter Signaling B2755-01 RXCCLK or TSCLK RXCDAT[1:0] or TSTAT[1:0] RXCDAT[3:2] RXCPAR RXCSOF [...]

318 Hardware Reference Manual Intel ® IXP2800 Network Processor Media and Switch Fabric Interface[...]

Hardware Reference Manual 319 Intel ® IXP2800 Network Processor PCI Unit PCI Unit 9 This section contains information on the IXP2800 Network Processor PCI Unit. 9.1 Overview The PCI Unit allo ws PCI target tr ansactions to internal regist ers, SRAM, and DRAM. It also generates PCI initiat or transactions from the DMA Engine, Inte l XScale ® core,[...]

320 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit Figure 1 18. PCI Functional Blocks A9765-01 Initiator Address FIFO Initiator Read FIFO Initiator Write FIFO Target Read FIFO Target Write FIFO Target Address FIFO PCI Configuration PCI Bus Host Functions 64-bit PCI Bus (@ 33 / 66 MHz) Core Interface PCI UNIT Master Address Re[...]

Hardware Reference Manual 321 Intel ® IXP2800 Network Processor PCI Unit 9.2 PCI Pin Protocol Interface Block This block generates the PCI compliant protoco l logic. It operates either as an initiator or a target device on the PCI Bus. A s an initiator, all bus cycles are generated by the core. As a PCI t arget, the core responds to bus cycles tha[...]

322 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit If a read address is latched, the subs equent cy cles will be retried and no address will be latch ed until the read completes. The in itiator addres s FIFO can accumulate up to four addresses that can be PCI reads or writes. These FIFOs are inside the PCI Core, which stores [...]

Hardware Reference Manual 323 Intel ® IXP2800 Network Processor PCI Unit PCI functions not supported by t he PCI Unit i nclude: • IO Space response as a tar get • Cacheable memory • VGA palette snooping • PCI Lock Cycle • Multi-function devices • Dual Address cycle 9.2.2 IXP2800 Network Proc essor Initialization When the IXP2800 Networ[...]

324 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit 9.2.2.1 Initialization by the Intel XScale ® Core The PCI unit is initialized to an inactive, disabled state until th e Intel XScale ® core has set the Initialize Complete bit in the Control register . This bit is set after the In tel XScale ® core has initialized the vari[...]

Hardware Reference Manual 325 Intel ® IXP2800 Network Processor PCI Unit 9.2.3 PCI T ype 0 Configuration Cycles A PCI access to a configuration re gister occurs when the follow ing conditions are satisfied: • PCI_IDSEL is assert ed. (PCI_IDSEL only supports PCI_A D[23:16] bits). • The PCI command is a conf iguration write or read. • The PCI_[...]

326 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit 9.2.5 PCI T arget Cycles The following PCI transact ions are not supported by the PCI Unit as a target: • IO read or write • T ype 1 configuratio n read or writ e • Special cycle • IACK cycle • PCI Lock cycle • Multi-function devi ces • Dual Address cycle 9.2.5.[...]

Hardware Reference Manual 327 Intel ® IXP2800 Network Processor PCI Unit 9.2.5.5 T arget Read A ccesses from the PCI Bus A PCI read occurs if the PCI a ddress matches one of the base address registers and the PCI command is either a Memory Read, Memory Read Line, or Memory Read Multip le. The read is completed as a PCI delayed read. That is, on th[...]

328 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit never de-asserts it prior to recei ving gnt_l[0] or de-asse rts it after receiving gnt_l[0] without doing a transaction. PCI Unit de-asserts req_l[0] for two cycles when it receives a retry or disconnect response from the target. 9.2.6.2 PCI Commands The following PCI transac[...]

Hardware Reference Manual 329 Intel ® IXP2800 Network Processor PCI Unit 9.2.6.6 Special Cycle As an initiator , special cycles ar e broadcast to all PCI agents, so DEVSEL_L is not asserted and no error can be received. 9.2.7 PCI Fast Back-to-Back Cycles The core supports fast back-to-back target cycles on the PCI Bus. The core does not generate i[...]

330 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit 9.2.1 1 PCI Central Functions The CFG_RSTDIR pin is active high fo r enabling the PCI Unit central function. The CFG_PCI_ARB(GPIO[2]) pin is the strap pin for the internal arbiter . When this strap pin is high during reset then the XPI Unit owns the arbitration. The CFG_PCI_B[...]

Hardware Reference Manual 331 Intel ® IXP2800 Network Processor PCI Unit 9.2.1 1.3 PCI Internal Arbiter The PCI unit contains a PCI bus arbiter that supports two external masters in additio n to the PCI Unit’ s initiator interface. T o enable the PCI arbiter , the CFG_PCI_ARB(GPIO[2]) strapping pin must be 1 during reset. As shown in Figure 120 [...]

332 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit 9.3 Slave Interface Block The slave interface logic supports internal slave de vices interfacing to the target port of the FBus. • CSR — register access cycles to local CSRs. • DRAM — memory access cycles to the DRAM push/pull Bus. • SRAM — memory access cycles to[...]

Hardware Reference Manual 333 Intel ® IXP2800 Network Processor PCI Unit 9.3.2 SRAM Interface The SRAM interface connects the FBus to the in ternal push/pull comm and bus and the SRAM push/pull data buses. Request to me mory is sent on the command bu s. Data request is received as valid push/pull ID sent by the SRAM push/pull data bus. If the PCI_[...]

334 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit 9.3.2.2 SRAM Slave Reads For a slave read from SRAM, a 32-bit DWORD is fetched from the memory for memory read command, one cache line is fetched for memory read line command, and two cache lines are read for memory read multipl e comm and. Cache line size is programm able in[...]

Hardware Reference Manual 335 Intel ® IXP2800 Network Processor PCI Unit 9.3.3.2 DRAM Slave Reads For target reads from IXP2800 Network Processo r memory , the entire 64 -byte block is fetched from DRAM. For target reads from IXP2800/IXP 2850 Network Processor memory , the b lock size is 16 bytes. Depending on the ad dress for the target request, [...]

336 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit Note: The IXP2800/IXP2850 always disconnects after tran sferring 16-bytes fo r DR AM target reads. The PCI core will also d isconnect at a 64-byte address boundary . The PCI core resets the read FIFO before is su ing a memory read data request on FBus. The PCI core will disco[...]

Hardware Reference Manual 337 Intel ® IXP2800 Network Processor PCI Unit The doorbell interrupt s are controlled through the registers sh own in T able 124 . The Intel XScale ® core and PCI devices write to the corresponding DOORBELL register to generate up to 32 doorbe ll interrupts. Each bit in the DOORBELL register is implemented as an SR flip[...]

338 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit The Doorbell Setup register allows the Intel XScale ® core and a PCI device to perform two functions that are not po ssible using the D oorbell register . This register is used during setup and diagnostics and is not used during normal oper ations. First, it allows the Intel[...]

Hardware Reference Manual 339 Intel ® IXP2800 Network Processor PCI Unit 9.3.5 PCI Interrupt Pin An external PCI interrupt can be generated in the following way: • The Intel XScale ® core initiates a Doorbell i nterrupt XSCALE_INT_ ENABLE. • One or more of the DMA channels have completed the DM A transfers. • The PNI bit is cleared by the I[...]

340 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit 9.4 Master Interface Block The Master Interface consists of the DMA engine and the Push/pull tar g et interface. Both can generate initiator PCI transactions. 9.4.1 DMA Interface There are two DMA channels, each of which can move blocks of data from DRAM to the PCI or from th[...]

Hardware Reference Manual 341 Intel ® IXP2800 Network Processor PCI Unit 9.4.1.1 Allocation of the DMA Channels Static allocation are employed su ch that the DMA resources are cont rolled exclusively by a single device for each channel. The Intel XScale ® core, a Microengine and the external PCI host can access the two DMA channels. The first two[...]

342 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit 9.4.1.3 DMA Descriptor Each descriptor occupies four 32-bit Dword s and is aligned on a 16-byte boundary . The DMA channels read the descriptors fr om local SRAM into the four DMA working registers once the control register has been set to initiate the transaction. This contr[...]

Hardware Reference Manual 343 Intel ® IXP2800 Network Processor PCI Unit 9.4.1.4 DMA Channel Operation Since a PCI device, Microeng ine, or the Intel XScale ® core can access the internal CSRs and memory in a similar way , the DMA chan nel operation description that follows will apply to all channels. CHAN_1_, CHAN_2_, or CHAN_3_ can be placed be[...]

344 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit 9.4.1.5 DMA Channel End Operation 1. Channel owned by PCI: If not masked via the PCI Outbound Interrupt Mask register , the DMA channel interrupts the PCI host after the setting of the DMA done bit in the CHAN_X_C ONTROL register , which is readable in the PCI Outbound Interr[...]

Hardware Reference Manual 345 Intel ® IXP2800 Network Processor PCI Unit A 64-bit double Dword with byte enables is pushed into the FBus FIFO from the DMA buffers as soon as there is data available in the buf fer and there is space in the FBus FIFO. The Core logic will transfer the exact number of bytes to the PCI Bus. The maximum burst size on th[...]

346 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit 9.4.2.2 Command Bus Master Access to Local Control and St atus Registers These are CSRs within the PCI Un it that are acces sible from push /pull bus masters. The masters include the Intel XScale ® core, Microengines. There is no PCI bus cycles generated. The CSRs within the[...]

Hardware Reference Manual 347 Intel ® IXP2800 Network Processor PCI Unit 9.4.2.3.2 PCI Address Generati on for Conf iguration Cycles When a push/pull command bus mast er is accessing the PCI Bus to ge nerate a configuration cycle, the PCI address is generated based on the a Command Bus Master address as shown in T a ble 128 and Figure 129 : 9.4.2.[...]

348 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit 9.5 PCI Unit Error Behavior 9.5.1 PCI T arget Error Behavior 9.5.1.1 T arget Access Has an Address Parity Error 1. If PCI_CMD_ST A T[P ERR_RESP] is not set, PCI Uni t will ignore the parity error . 2. If PCI_CMD_ST A T[PERR_RESP] is set: a. PCI core will not claim the cycle r[...]

Hardware Reference Manual 349 Intel ® IXP2800 Network Processor PCI Unit 9.5.1.5 T arget W rite Access Receives Ba d Parity PCI_P A R with the Dat a 1. If PCI_CMD_ST A T[PERR_RESP] is not set, PCI Unit will ignore the parit y error . 2. If PCI_CMD_ST A T [PERR_RESP] is set: a. core asserts PCI_PERR_L and sets PCI_CMD_ST A T[PERR]. b. Slave Interfa[...]

350 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit 9.5.2.2 DMA Read from SRAM (Descr iptor Read) Gets a Memory Error 1. Set PCI_CONTROL[DMA_SRAM_ERR] whic h will interrupt the Intel XScale ® core if enabled. 2. Master Interface clears the Channe l Enable bit in CHAN_X_CONTROL. 3. Master Interface sets DMA channel error bit i[...]

Hardware Reference Manual 351 Intel ® IXP2800 Network Processor PCI Unit 9.5.2.5 DMA T ransfer Experiences a Master Abort (Time-Out) on PCI Note: That is, nobody asserts DEVSEL during the DEVSEL window . 1. Master Interface sets PCI_CONTROL[RMA] which will interrupt the Intel XScale ® core if enabled . 2. Master Interface clears the Chan nel Enab[...]

352 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit 9.5.3.3 Master from the Intel XSc ale ® Core or Microengine T ransfer (Write to PCI) Receiv es PCI_PERR_L on PCI Bus 1. If PCI_CMD_ST A T[P ERR_RESP] is not set, PCI Uni t will ignore the parity error . 2. If PCI_CMD_ST A T[PERR_RESP] is set: a. Core sets PCI_CMD_ST A T[PERR[...]

Hardware Reference Manual 353 Intel ® IXP2800 Network Processor PCI Unit -- T able 130. Byte Lane Alignment for 64-Bit PCI Da ta In (64 Bit s PCI Little-Endian to Big-Endian with Swap) PCI Data IN[63:56] IN[5 5:48] IN[47:40] I N[39:32] IN[31:24] IN[23:16] IN[15:8] IN[7:0] SRAM Data OUT[7:0] OUT[15:8] OUT[23:16] OUT[ 31:24] OUT[7:0] OUT[15:8] OUT[2[...]

354 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit T able 134. Byte Lane Alignment for 64-Bit PC I Data Out (Big-Endia n to 64 Bits PCI Little Endian with Swap) SRAM Data IN[7:0] IN[15:8] IN[23:16] IN[31:24] IN[7:0] IN[15:8] IN[23:16] IN[31:24] Longword1 (3 2 bits) LW1 drive af ter LW0 Longword0 ((32 bits) LW0 drive fir st DR[...]

Hardware Reference Manual 355 Intel ® IXP2800 Network Processor PCI Unit The BE_DEMI bit of the PCI_CONTROL register can be set to enable big-endian on the incoming data from the PCI Bus to both the SRAM an d DRAM. The BE_DEMO bit of the PC I_CONTROL register can be set to enable big-endian on the outgoin g data to the PCI Bus from both the SRAM a[...]

356 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit T able 141. Byte Enable Alignment for 32-Bit PCI Dat a In (32 Bits PCI Big-Endian to Big-Endian without Swap) PCI Add[2 ]=1 PCI Add[2 ]=0 Longword1byte enable LW1 byte enable drive after LW0 byte enable Longword0 byte enable LW0 byte enable drive first PCI Data IN_BE[0] IN_BE[...]

Hardware Reference Manual 357 Intel ® IXP2800 Network Processor PCI Unit The BE_BEMI bit of the PCI_CONTROL register can be set to enable big-endian on the incoming byte enable from the PCI Bus to both th e SRAM and DRAM. The BE_BEMO bit of the PCI_CONTROL register can be set to enable big- endian on the outgoing by te enable to the PCI Bus from b[...]

358 Hardware Reference Manual Intel ® IXP2800 Network Processor PCI Unit T able 146. PCI I/O Cycles with Dat a Swap Enable Stepping Des cription A Ste pping A PCI IO cycle is treated like CSR where the data bytes are not sw apped. It is sent in the same byte order whether the PCI bus is configured in Big-Endian or Little-Endian mode. B Ste pping W[...]

Hardware Reference Manual 359 Intel ® IXP2800 Network Processor Clocks and Reset Clocks and Reset 10 This section describes the IXP2800 Network Processo r clocks and reset. Refer to the Intel ® IXP2800 Network Pr ocessor Hardwar e Initia lization Refer ence Manua l for information about the initialization of all units of the IXP2800 Netwo rk Proc[...]

360 Hardware Reference Manual Intel ® IXP2800 Network Processor Clocks and Reset Figure 130. Overall Clock Generatio n and Distribution A9777-02 Scratch, Hash, CSR PCI Slow P or t Devices , i.e., Flash, ROM P eripherals (Timers, U ART , etc.) External Oscillator Constant (Multiplier) SRAM2 SRAM3 SRAM1 SRAM0 S_clk2 S_clk3 S_clk1 S_clk0 Media and Sw[...]

Hardware Reference Manual 361 Intel ® IXP2800 Network Processor Clocks and Reset The fast frequency on the IXP2800 Network Pro cessor is generated by an on-chip PLL that multiplies a reference frequency provided by an on -board L VDS oscillator (frequency 10 0 MHz) by a selectable multiplier . The multiplier is selected by using external strap pi [...]

362 Hardware Reference Manual Intel ® IXP2800 Network Processor Clocks and Reset Figure 131 shows the clocks generation circuitry for the IX P2800 Network Pr ocessor . When the chip is powered up, bypass clock will be sent to all the units. After the PLL is locked, clock unit will switch all units from bypass clock to a fixed frequency clo ck whic[...]

Hardware Reference Manual 363 Intel ® IXP2800 Network Processor Clocks and Reset 10.2 Synchronization Betw een Frequency Domains Due to the internal design architecture o f the IXP2800 Netwo rk Processor , it is guaranteed that one of the clock domains of an asynchronous tr ansfer will be the Push/Pull domain (PLL/4). Additionally , all other cloc[...]

364 Hardware Reference Manual Intel ® IXP2800 Network Processor Clocks and Reset 10.3 Reset The IXP2800 Network Processor can be reset fo ur ways. • Hardware Reset Using nRESET or PCI_RST_L. • PCI-Initiated Reset. • W atchdog T imer Initiated Reset. • Software Initiated Reset. 10.3.1 Hardware Reset Usin g nRESET or PCI_RST_L The IXP2800 Ne[...]

Hardware Reference Manual 365 Intel ® IXP2800 Network Processor Clocks and Reset “reset_out_strap” is sampled as 0 on the trailing edge of reset, nRESET_OUT is de-asserted based on the value of IXP_RESET_0[15] which i s written by software. If “reset_out_strap” is sampled as 1 on the trailing edge of reset, nRES ET_OUT is de-asserted after[...]

366 Hardware Reference Manual Intel ® IXP2800 Network Processor Clocks and Reset 10.3.2 PCI-Initiated Reset CFG_RST_DIR is not asserted and PCI_RST_L is asserted. When the CFG_RST_DIR strap pin is not assert ed (sampled 0), PCI_RST_L is input to the IXP2800 Network Processor an d is used to reset all the internal functions. Its behavi or is the sa[...]

Hardware Reference Manual 367 Intel ® IXP2800 Network Processor Clocks and Reset 10.3.3.1 Slave Network Pro cessor (Non-Central Function) • If the W atchd og timer reset enable bit set to 1, W atchdog reset will trigger the soft reset • If the W atchdog time r reset enable bit set to 0, W atchdog reset will trig ger the PCI interrup t to exter[...]

368 Hardware Reference Manual Intel ® IXP2800 Network Processor Clocks and Reset Once in operation, if the watchdog timer expires with watchdog timer enable bit WDE from Timer W atchdog Enable register set, a reset pulse from the watchdog ti mer logic goes to PLL unit after passing through a counter to guarantee minimum assertion time, which in tu[...]

Hardware Reference Manual 369 Intel ® IXP2800 Network Processor Clocks and Reset T able 149. IXP2800 Network Processor St rap Pins Signal Name Description CFG_RST_DIR RST_DIR PCI_RST direction pin: (Also called PCI_HOST) Need to be a dedicated pin. 1—IXP2800 Network Processor is the host supporting central function. PCI_RST_L is output. 0—IXP2[...]

370 Hardware Reference Manual Intel ® IXP2800 Network Processor Clocks and Reset Ta b l e 1 5 0 lists the supported Strap combinations of CFG_PROM_BOOT , CFG_RST_DIR, and CFG_PCI_BOOT_HIST . One more restriction in the PCI unit is that, if the IXP2800 Network Processor is a PCI_HOST or PCI_ARBITER, it should also be PCI_CENTRAL_FUNCTION. 10.3.7 Po[...]

Hardware Reference Manual 371 Intel ® IXP2800 Network Processor Clocks and Reset Figure 135. Boot Pro cess A9782-03 No Yes Reset Signal asserted (hardware, software, PCI or Watchdog) CFG_PROM_BOOT- Boot From Present START Yes No CFG_PROM_ BOOT_HOST START START START START 1. Intel XScale ® Core is held in reset. 2. PCI BAR window sizes are config[...]

372 Hardware Reference Manual Intel ® IXP2800 Network Processor Clocks and Reset 10.4.1 Flash ROM At power up, if FLA SH_ROM is present, strap pin CFG_PROM_BOOT should be sample d 1 (should be pulled up). Therefore after reset being remov ed by the PLL logic from the IXP_RESET0 register , the Intel XScale ® core reset is automatical ly removed. F[...]

Hardware Reference Manual 373 Intel ® IXP2800 Network Processor Clocks and Reset code is written in DRAM, PCI ho st writes 1 at bi t [8] of Misc_Control register called Flash Alias Disable (Reset value 0). The Alias Disabl e bit can be wired to the Intel XScale ® core gasket directly so that gasket knows how to transform address 0 from the Intel [...]

374 Hardware Reference Manual Intel ® IXP2800 Network Processor Clocks and Reset[...]

Hardware Reference Manual 375 Intel ® IXP2800 Network Processor Performance Monitor Unit Performance Monitor Unit 11 1 1.1 Introduction The Performance Monito r Unit (PMU) is a hardware bl ock consisting of counters and comparators that can be programmed and controlled by u sing a set of configured registers to moni tor and to fine tune performanc[...]

376 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.1.2 Motivation for Choosing CHAP Counters The Chipset Hardware Architect ure Performance (C HAP) counters enabl e statistics gathering of internal hardware events in r eal-time. This implementation prov ides users with direct event counting and timing fo [...]

Hardware Reference Manual 377 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.1.3 Functional Overvi ew of CHAP Counters At the heart of the CHA P counter ’ s functionality ar e counters, each with asso ciated registers. Each counter has a corresponding co mmand, event, status, and da ta register . The smallest implementation has t[...]

378 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.1.4 Basic Operation of the Performance Monitor Unit At power-up, the Intel XScale ® core i nvokes the performance monit oring software code. The PMU software has the application code to generate di fferent types of data, such as histograms and graphs. It[...]

Hardware Reference Manual 379 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.1.5 Definition of CHAP T erminology Figure 138. Basic Block Diag ram of IXP2800 Network Processor with PMU Duration Count The counter is incremented for each clock for which the event signal is asserted as logic high. MMR Memory Mapped register . OA Observ[...]

380 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.1.6 Definition of Clock Domains The following abbreviati ons are used in the events table under clock domain. 1 1.2 Interface and CSR Description CAP is a standard lo gic block provided as part of the Network Processor that provides a meth od of interfaci[...]

Hardware Reference Manual 381 Intel ® IXP2800 Network Processor Performance Monitor Unit 11 . 2 . 1 A P B P e r i p h e r a l The APB is part of the AMD* co ntroller Bus Architecture (AMBA) hierarchy of buses that is optimized for minimal p ower consumption and reduced design comp lexity . The PMU needs to operate as an APB peripheral, in terfacin[...]

382 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit acknowledge signal (CAP_CSR_RD_RDY). When the data is returned, CAP puts the read data into the Push Data FIFO, arbitrates for the S_Push_Bus, and then the Push/Pull Arbiter pushes the data to the destination identified in PP_ID. 1 1.2.3 Configuration Registe[...]

Hardware Reference Manual 383 Intel ® IXP2800 Network Processor Performance Monitor Unit T able 152. Hardware Blocks and Their Performance Measurement Events (She et 1 of 2) Hardware Block Performance Measurement Event Description Intel XScale ® Core DRAM Read Head of Queue Latency Histogram The Intel XScale ® core generates a read or write comm[...]

384 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit Chassis/Push-Pull Command Bus Utilization These statistics give the number of the command requ ests issued by the different Masters in a particular period of time. This measurement also indicates how long it takes to issue the grant from the request being iss[...]

Hardware Reference Manual 385 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.4 Event s Monitored in Hardware T ables in this section describe the events that can be measured, including th e name of the event and the Event Selection Code (ESC). Refer to Section 1 1.4 for tables showing event selectio n codes. The acronyms in the eve[...]

386 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.4.3 Design Block Select Definitions Once an event is d efined, its defin ition must remain consistent between p roducts. If the definitio n changes, it should have a new ev ent selection code. This document contains the master list of all ESCs in all CHAP[...]

Hardware Reference Manual 387 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.4.4 Null Event Not an actual event. When used as an increment or decrement event, no action takes plac e. When used as a Command Tr igger, it causes the command to be triggered immediately aft er the command register is written to by the software. Also cal[...]

388 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.4.5 Threshold Event s These are the outputs of the threshol d comparators. When the value in a data register is compared to its corresponding counter valu e and the condition is true, a threshold event is generated. This results in: • A pulse on the sig[...]

Hardware Reference Manual 389 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.4.6 External Input E vent s 1 1.4.6.1 XPI Event s T arget ID(000001) / Design Block #(0100) T able 155. XPI PMU Event List (Sheet 1 of 4) Event Number Event Name Clock Domain Single pulse/ Long pulse Burst Description 0 XPI_RD_P APB_CLK single separate It [...]

390 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 26 TURNA0_C_P APB_CLK single separate It enters the ter mination state of the state machine 0 for the mode 0 of Slowport. 27 IDLE1_0_P APB_CLK single separate It displays the idle state of the state machine 1 for the mode 1 of Slowport. 28 ST ART1_1_P APB_CLK[...]

Hardware Reference Manual 391 Intel ® IXP2800 Network Processor Performance Monitor Unit 48 SETUP2_4_P APB_CLK single s eparate It enters the pulse width of the data transaction cycle for the state machine 2 for the mode 2 of Slowport. 49 PUL W2_C_P APB_CLK single separate It enters the pulse width of the data transaction cycle for the state machi[...]

392 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 70 TURNA3_8_P APB_CLK single separate It enters the turnaround state of the transaction when the state machine 3 is active for the mode 3 of Slowport. 71 IDLE4_0_P APB_CLK single separate It displays the idle state of the state machine 4 for the mode 4 of Slo[...]

Hardware Reference Manual 393 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.4.6.2 SHaC Event s T arget ID(000010) / Design Block #(0101) T able 156. SHaC PMU Event List (Sheet 1 of 4) Event Number Event Name Clock Domain Single pulse/ Long pulse Burst Description 0 Scratch Cmd_Inlet_Fifo Not_Empty P_CLK single separate Scratch Com[...]

394 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 22 Scratch Ring_1 Status P_CLK s ingle separate If SCRA TCH_RING_BASE_x[26] = 1, RING_1_ST A TUS indicates empty . If SCRA TCH_RING_BASE_x[26] = 0, RING_1_ST A TUS indicates full. 23 Scratch Ring_2 Status P_CLK s ingle separate If SCRA TCH_RING_BASE_x[26] = 1[...]

Hardware Reference Manual 395 Intel ® IXP2800 Network Processor Performance Monitor Unit 35 Scratch Ring_14 St atus P_CLK single separate If SCRA TCH_RING_BASE_x[26] = 1, RING_14_ST A TUS indicates empty . If SCRA TCH_RING_BASE_x[26] = 0, RING_14_ST A TUS indicates full. 36 Scratch Ring_15 St atus P_CLK single separate If SCRA TCH_RING_BASE_x[26] [...]

396 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.4.6.3 IXP2800 Network Processor MS F Event s T arget ID(00001 1) / Design Block #(01 10) 63 Hash Cmd_Pipe F ull P_CLK single separate Hash Command Pipe Full 64 Hash Push_Data_Pipe Not_Empty P_CLK single sep arate Hash Push Data Pipe Not Empty 65 Hash Push[...]

Hardware Reference Manual 397 Intel ® IXP2800 Network Processor Performance Monitor Unit 19 reserv ed 20 S_PULL data FIFO 1 enqueue P_CLK pulse separate 21 S_PULL data FIFO 1 dequeue P_CLK pulse separate 22 S_PULL data FIFO 1 full P_CLK level separate 23 S_PULL data FIFO 1 not empty P_CLK level separate 24 Tbuf fer Partition 0 full P_CLK level sep[...]

398 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 45 Detect FC_DEAD MRX_CLK level separate Indicates that a dead cycle has been received on the RXCDA T inputs for greater than 2 clock cycles; the valid signal from the MTS_CLK domain is synchronized; as such , it yields an approximate value. 46 Detect C_IDLE [...]

Hardware Reference Manual 399 Intel ® IXP2800 Network Processor Performance Monitor Unit 70 SPI-4 Packet received P_CLK pulse separate Indicates that the SPI-4 state machine after the Receive input FIFO has received an SPI-4 packet. 71 reserv ed 72 Data CFrame transmitted P_CLK level separate Indicates that the transmit buffer state machine is wri[...]

400 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 97 Rx null autopush P_CLK pulse separate 98 Tx skip P_CLK pulse separate An mpacket was dropped due to the Tx_Skip bit being set in the T ransmit Control Wor d. 99 SF_CRDY P_CLK level separate Only valid in CSIX receive mode and indicates how much of the time[...]

Hardware Reference Manual 401 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 15 FCE receive active MR_CLK level separate Indicates a valid Flow Control Packet received on the RX_DA T A bus and may be used to measure bus util ization; the act ive signal from the MR_CLK domain is synchronized; as such, it yield s an approximate value. [...]

402 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.4.6.4 Intel XScale ® Core Even t s T arget ID(000100) / Design Block #(01 1 1) T able 158. Intel XScale ® Core Gasket PMU Event List (Shee t 1 of 4) Event Number Event Name Clock Domain Single pulse/ Long pulse Burst Description 0 XG_CFIFO_WR _EVEN_XS P[...]

Hardware Reference Manual 403 Intel ® IXP2800 Network Processor Performance Monitor Unit 32 reserved 33 reserved 34 XG_CFIFO_EMPTYN_CPP P_C LK single separate XG command F IFO empty flag 35 XG_DFIFO_EMPTYN_CPP P_C LK single separate XG DR AM data FIFO empty flag 36 XG_SFIFO_EMPTYN_CPP P_CLK single separate XG SRAM data FIFO empty flag 37 XG_LCFIFO[...]

404 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 71 XG_SRAM_WR_2_CPP P_CLK single separate XG SRAM write length=2 on cpp bus 72 XG_SRAM_WR_3_CPP P_CLK single separate XG SRAM write length=3 on cpp bus 73 XG_SRAM_WR_4_CPP P_CLK single separate XG SRAM write length=4 on cpp bus 74 XG_SRAM_CSR_RD_CPP P_CLK sin[...]

Hardware Reference Manual 405 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.4.6.5 PCI Event s T arget ID(000101) / Design Block #(1000) 1 10 XG_MSF_WR_3_CPP P_CLK single separate XG msf write length=3 on cpp bus 1 1 1 XG_MSF_WR_4_CPP P_CLK single separate XG msf write length=4 on cpp bus 1 12 XG_PCI_RD_CPP P_CLK single separate XG[...]

406 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 13 PCI_TG T_WBUF_NEMPTY P_CLK single separate P CI T arget W rite Buffer Not Empty 14 PCI_TG T_WBUF_WR P_C LK single separate PCI T arget W rite Buffer Write 15 PCI_TG T_WBUF_RD P _CLK single separate PCI T arget W rite Buffer Read 16 PCI_MST_AFIFO_FULL P_C L[...]

Hardware Reference Manual 407 Intel ® IXP2800 Network Processor Performance Monitor Unit 52 PCI_DRAM_BURST_WRITE P_CLK single separate PCI Burst Write to PCI_CSR_BAR 53 PCI_DRAM_BURST_READ P_CLK sin gle separate PCI Burst Read to PCI_CSR_BAR 54 PCI_SRAM_WRITE P_CLK single separate PCI Write to PCI_SRAM_BAR 55 PCI_SRAM_READ P_CLK sin gle separate 5[...]

408 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 89 PCI_XS_CFG_RD P_CLK single separate PCI Intel XScale ® Core Read PCI Bus Config S pace 90 PCI_XS_CFG_WR P_CLK single separate 91 PCI_XS_MEM_RD P_CLK single separate PCI Intel XScale ® Core Read PCI Bus Memory S pace 92 PCI_XS_MEM_WR P_CLK single separate[...]

Hardware Reference Manual 409 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.4.6.6 ME00 Event s T arget ID(100000) / Design Block #(1001) 1 18 PCI_ ARB_GNT[2] PCI_CLK single separate Interna l Arbiter PCI Bus Grant 2 1 19 PCI_ ARB_REQ[1] PCI_CLK single separate 120 PCI_ ARB_GNT[1] PCI_CLK single separate 121 PCI_ ARB_REQ[0] PCI_CLK[...]

410 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.4.6.7 ME01 Event s T arget ID(100001) / Desi gn Block #(1001) 12 ME_FIFO_DEQ P_CLK single separate Command FIFO Dequeue 13 ME_FIFO_NOT_EMPTY P_CLK single separate Command FIF O not empty Note: 1. All the Microengine have the same event list. 2. CC_Enable [...]

Hardware Reference Manual 411 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.4.6.8 ME02 Event s T arget ID(100010) / Design Block #(1001) 1 1.4.6.9 ME03 Event s T arget ID(10001 1) / Design Block #(1001) T able 162. ME02 PMU Ev ent List Event Number Event Name Clock Domain Pulse/ Level Burst Description Note: 1. All the Microengine[...]

412 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.4.6.10 M E04 Event s T arget ID(100100) / Desi gn Block #(1001) 1 1.4.6.1 1 M E05 Event s T arget ID(100101) / Desi gn Block #(1001) T able 164. ME04 PMU Event List Event Number Event Name Clock Domain Pulse/ Level Burs t Desc riptio n Note: 1. All the Mi[...]

Hardware Reference Manual 413 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.4.6.12 ME06 Events T arget ID(1001 10) / Design Block #(1001) 1 1.4.6.13 ME07 Events T arget ID(1001 1 1) / Design Block #(1001) T able 166. ME06 PMU Ev ent List Event Number Event Name Clock Domain Pulse/ Level Burst Description Note: 1. All the Microengi[...]

414 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.4.6.14 M E10 Event s T arget ID(1 10000) / Design Block #(1010) 1 1.4.6.15 ME1 1 Events T arget ID(1 10001) / Design Block #(1010) T able 168. ME10 PMU Event List Event Number Event Name Clock Domain Pulse/ Level Burs t Desc riptio n Note: 1. All the Micr[...]

Hardware Reference Manual 415 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.4.6.16 ME12 Events T arget ID(1 10010) / Design Block #(1010) 1 1.4.6.17 ME13 Events T arget ID(1 1001 1) / Design Block #(1010) T able 170. ME12 PMU Ev ent List Event Number Event Name Clock Domain Pulse/ Level Burst Description Note: 1. All the Microengi[...]

416 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.4.6.18 M E14 Event s T arget ID(1 10100) / Design Block #(1010) 1 1.4.6.19 M E15 Event s T arget ID(1 10101) / Design Block #(1010) T able 172. ME14 PMU Event List Event Number Event Name Clock Domain Pulse/ Level Burs t Desc riptio n Note: 1. All the Mic[...]

Hardware Reference Manual 417 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.4.6.20 ME16 Events T arget ID(1001 10) / Design Block #(1010) 1 1.4.6.21 ME17 Events T arget ID(1 101 1 1) / Design Block #(1010) T able 174. ME16 PMU Ev ent List Event Number Event Name Clock Domain Pulse/ Level Burst Description Note: 1. All the Microeng[...]

418 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.4.6.22 S RAM DP1 Event s T arget ID(001001) / Desi gn Block #(0010) 1 1.4.6.23 S RAM DP0 Event s T arget ID(001010) / Desi gn Block #(0010) T able 176. SRAM DP1 PMU Event List Event Number Event Name Clock Domain Pulse/ Level Burs t Desc riptio n Note: 1.[...]

Hardware Reference Manual 419 Intel ® IXP2800 Network Processor Performance Monitor Unit 13 sps_s0_enq_wph P_CLK single separate SRAM0 Push Command Queue FIFO Enqueue 14 sps_s0_deq_wph P_CLK single separate SRAM0 Push Command Queue FIFO Dequeue 15 sps_s0_push_q_full_wph P_CLK Long separate SRAM0 Push Command Queu e FIFO Full 16 sps_s1_cmd_valid_rp[...]

420 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.4.6.24 SRAM CH3 Events T arge t ID(00101 1) / Desi gn Block #(0010) 45 spl_s1_enq_cmd_wph P_CLK single separate SRAM1 Pull Command Queue FIFO Enqueue 46 spl_s1_deq_wph P_CLK single separate SRAM1 Pull Command Queue FIFO Dequeue 47 spl_s1_cmd_que_full_wph [...]

Hardware Reference Manual 421 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.4.6.25 SRAM CH2 Events T arget ID(001 100) / Design Block #(0010) 1 1.4.6.26 SRAM CH1 Events T arget ID(001 101) / Design Block #(0010) T able 179. SRAM CH3 PMU Event List Event Number Event Name Clock Domain Pulse/ Level Burst Description Note: 1. All the[...]

422 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.4.6.27 SRAM CH0 Events T arge t ID(001 1 10) / Design Block #(0010) T able 181. SRAM CH0 PMU Event List (She et 1 of 2) Event Number Event Name Clock Domain Single pulse/ Long pulse Burst Description 0 QDR I/O Re ad S_CLK single separate QDR I/O R ead 1 Q[...]

Hardware Reference Manual 423 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.4.6.28 DRAM DPLA Event s T arget ID(010010) / Design Block #(001 1) 33 FIFO Full – Queue Cmd Q P_CLK long separate FIF O Full – Queue Cmd Q 34 FIFO Dequeue – Rd Cmd Q S_CLK single separate FIFO Dequeue – Rd Cmd Q 35 FIFO Enqueue – Rd Cmd Q P_CLK [...]

424 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 1 1.4.6.29 D RAM DPSA Even ts T arget ID(01001 1) / Design Block #(001 1) 9 d2_deq_id_wph P_CLK single separate Dequeue d2 cmd 10 dram_req_rph[2] P_CLK single separate d2 has a valid req 1 1 next_d2_f ull_wph P_CLK single separate d2 FIFO hit the full thresho[...]

Hardware Reference Manual 425 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.4.6.30 IXP2800 Netwo rk Processor DRAM CH2 Events T arget ID(010100) / Design Block #(001 1) 17 cr1_deq_id_wph P_CLK single separate Dequeue cr1 cmd/data 18 dram_req_rph[4] P_CLK single separate cr1 has a valid req 19 next_cr1_full_wph P_CLK single separat[...]

426 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 14 deq_push_ctrl_wph P_CLK single separate Active when dequeueing from the push control FIFO; occurs on the last cycle of a burst or on the only cycle of a single transfer . 15 d_push_ctrl_fsm/ single_xfer_wph P_CLK single separate Active if the data is about[...]

Hardware Reference Manual 427 Intel ® IXP2800 Network Processor Performance Monitor Unit 33 DAP_DEQ_B3_DA T A_RPH P_CLK single separate Indicates pull data and command are being dequeued from the data and command bank FIFOs to the RMC (the command and data FIFOs used in tandem for pulls to supply the address and data respectively). 34 DAP_DEQ_B2_D[...]

428 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit 57 reserved 58 reserved 59 deq_split_cmd_fifo_wph P_CLK single separate Act ive when dequeueing from the split inlet FIFO. 60 de q_inlet_fifo1_wph P_CLK single separate Active when dequeueing from the inlet FI FO. 61 de q_inlet_fifo_wph P_CLK s ingle s eparat[...]

Hardware Reference Manual 429 Intel ® IXP2800 Network Processor Performance Monitor Unit 1 1.4.6.31 IXP2800 Netwo rk Processor DRAM CH1 Events T arget ID(010101) / Design Block #(001 1) 1 1.4.6.32 IXP2800 Netwo rk Processor DRAM CH0 Events T arget ID(0101 10) / Design Block #(001 1) 80 bank2_enq_wph P_CLK single separate Indicates this channel is [...]

430 Hardware Reference Manual Intel ® IXP2800 Network Processor Performance Monito r Unit[...]