Intel BX80637I53350P manual

Reference Number: 32676 6 Desktop 3rd Generation Intel ® Core™ Processor Family Specification Update September 2013 Revision 015[...]

2 Specification Update INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WI TH INTEL PRODUCTS. NO LICENSE, EXP RESS OR IMPLIED, BY ESTOPPEL OR OTHER WISE, TO ANY INTELLECTUAL PROPERTY RI GHTS IS GRANTED BY THIS DOCUMENT . EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FO R SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHA TSOEVER[...]

Contents Specification Update 3 Contents Revision History ................ ............ ................. ............. ............ ................. ............ ............ 5 Preface .................. ............. ................ ............. ............. ................ ............. ................ ........ 6 Summary Tables of Change s[...]

Contents 4 Specification Update[...]

Specification Update 5 Revision History Revision Description Date 001 • Initial Release. April 2012 002 • Added Err ata BV68–BV83 • Updated Proc essor Identi fication T able May 2012 003 • Added L -1 and N-0 steppings to errata summary tab le • Added L -1 and N-0 steppings to Component Identificatio n using Programming Interface table ?[...]

6 Specification Update Preface This document is an update to the specifications contained in the Affected Documents table below . This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications , operating system s, [...]

Specification Update 7 Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and softw are designed to b e used with any giv en stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to[...]

8 Specification Update Summary Tables of Changes The following tables indicate the errata , specification changes, specification clarifications, or documentation changes which apply to the processor . Intel may fix some of the errata in a fu ture stepping of the component, and account for the other outstanding issues through documentation or specif[...]

Specification Update 9 BV7 XX X N o F i x General Protection Fault (#GP) for Inst ructions Greater th an 15 Bytes May be Preempted BV8 XX X N o F i x LBR, BTS, BTM May Report a Wrong Address when an Excep tion/Interrupt Occurs in 64-bit Mode BV9 XX X N o F i x Incorrect Address Computed For Last Byte of FXSA VE/FXRSTOR or XSA VE/ XRSTOR Image Leads[...]

10 Specification Update BV33 XX X N o F i x Clock Modulation Duty Cycle Cannot be Progra mmed to 6.25% BV34 XX X N o F i x Processor May Fail to Acknowledge a TLP Req uest BV35 XX X N o F i x An Unexpected PMI May Occur After Writing a Large V alue to IA32_FIXED_CTR2 BV36 XX X N o F i x A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect V a[...]

Specification Update 11 BV60 XX X N o F i x The Processor May Not Comply With PCIe* Equalization Preset Reflection Requirements for 8 GT/s Mode of Operation BV61 XX X N o F i x Processor May Issue PCIe* EIEOS at Incorrect Rat e BV62 XX X N o F i x Reduced Swing Output Mode Needs Zero De-emphasis to be Supported in PCIe* 5GT/s S peed BV63 XX X N o F[...]

12 Specification Update BV90 XX X N o F i x During Package Power St ates Repeate d PCIe* and/or DMI L1 Transitions May Cause a System BV91 XX X N o F i x Instruction Fetches Page-T able Walks Ma y be Made S peculatively to Uncacheable Memory BV92 XX X N o F i x The Processor May Not Properly Execute Code Mo dified Using A Floating-Point St o r e BV[...]

Specification Update 13 § § Documentation Changes Number DOCUMENTAT ION CH AN GES BU1 On-Demand Clock Modulation Feature Clarification[...]

14 Specification Update Identification Information Component Identification us ing Programmin g Interface The processor stepping can be identified by the following register contents: Notes: 1. The Extended F amily , bits [27:20] are used in conjunction with the F amily Co de, specified in bits [11:8], to indicate whether the processor belongs to th[...]

Specification Update 15 Component Marking Information The processor stepping can be identified by the following component markings. Figure 1. Processor Production Top-side Markings (Example) Table 1. Processor Identification (Sheet 1 of 6) Number Processor Number Stepping Processor Signat ure Core Frequency (GHz) / DDR3 (MHz) / Processor Graphics F[...]

16 Specification Update SR0P3 i5-3550S E-1 000306A9h 3 / 1600 / 650 4 core: 3.3 3 core: 3.4 2 core: 3.6 1 core: 3.7 6 3,4,5,6 SR0PM i5-3570K E-1 000306A9h 3.4 / 1600 / 650 4 core: 3.6 3 core: 3.7 2 core: 3.8 1 core: 3.8 64 , 6 SR0P0 i5-3550 E-1 000306A9h 3.3 / 1600 / 650 4 core: 3.5 3 core: 3.6 2 core: 3.7 1 core: 3.7 6 3,4,5,6 SR0PP i5-3475S E-1 0[...]

Specification Update 17 SR0PC E3-1290V2 E-1 000306A9h 3.7 / 1600 / 0 4 core: 3.8 3 core: 3.9 2 core: 4 1 core: 4.1 8 2,3,4,5,6 SR0P7 E3-1280V2 E-1 000306A9h 3.6 / 160 0 / 0 4 core: 3.7 3 core: 3.8 2 core: 3.9 1 core: 4 8 2,3,4,5,6 SR0PA E3-1275V2 E-1 000306A9h 3.5 / 1600 / 650 4 core: 3.7 3 core: 3.8 2 core: 3.9 1 core: 3.9 8 2,3,4,5,6 SR0P6 E3-127[...]

18 Specification Update SR0RG i3-3220 L -1 00 0306A9h 3.3 / 1600 / 650 4 core: N/A 3 core: N/A 2 core: N/A 1 core: 3.3 32 , 4 SR0RE i3-3220T L -1 000306A9h 2.8 / 1600 /650 4 core: N/A 3 core: N/A 2 core: N/A 1 core: 2.8 32 , 4 SR0RF i3-3225 L -1 000306A9h 3.3 / 1600/ 650 4 core: N/A 3 core: N/A 2 core: N/A 1 core: 3.3 32 , 4 SR0RH i3-3240 L -1 0003[...]

Specification Update 19 SR0PL i7-3770K E-1 000306A9h 3.5/ 1600/ 650 4 core: 3.7 3 core: 3.8 2 core: 3.9 1 core: 3.9 82 , 4 , 6 SR0PN i7-3770S E-1 000306A9h 3.1/ 1600/ 650 4 core: 3.5 3 core: 3.6 2 core: 3.8 1 core: 3.9 8 2,3,4,5,6 SR0PQ i7-3770T E-1 000306A9h 2.5/ 1600/ 650 4 core: 3.1 3 core: 3.4 2 core: 3.6 1 core: 3.7 8 2,3,4,5,6 SR0YU G2130 P-0[...]

20 Specification Update Notes: 1. This column indic ates max imum I ntel ® T urbo Boost T echnology 2.0 fr equency (GHz) for 4,3, 2 or 1 cores active respectiv ely . 2. Intel ® Hyper- Threading T echnology enabled. 3. Intel ® T rusted Ex ecution T echnology (Intel ® TXT) enabled. 4. Intel ® Virtualization T echnology for IA-32, Intel ® 64 and[...]

Specification Update 21 Errata BV1. The Processor May Report a #TS Instead of a #GP Fault Problem: A jump to a busy TSS (T ask -State Segment) ma y cause a #TS (inv alid TSS ex ception) instead of a #GP f ault (gener al protection exception). Implication: Operation systems that access a busy T SS may get in valid T SS fault instead of a #GP fault. [...]

22 Specification Update BV4. Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: Performance Monitoring counter SIMD_INST_RETIRED (Event: C 7H) is used to tr ack retired SSE instructions. Due to this erratum, the processor may also count other types of instructions resulting in higher than expected values. Implication:[...]

Specification Update 23 BV8. LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode Problem: An exception/interrupt ev ent should be transparent to the LBR (Last Branch R ecord), B T S (Branch T race Store) and B TM (Branch T r ace Message) mechanisms. However , during a specific boundary condition where the ex [...]

24 Specification Update BV11. EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change Problem: This erratum is regarding the case where pa ging structu res are modifi ed to change a linear address from writable to non-writable without software perfo rming an appropriate TLB inv alidation. When a subseque nt access t[...]

Specification Update 25 BV13. MCi_Status Overflow Bit May Be In correctly Set on a Single Instance of a DTLB Error Problem: A single Data T ranslation Look Aside Buffer (D TLB) error can incorrectly set the Overflow (bit [62]) in the MCi_Status regist er . A D TLB error is indicated by MCA error code (bits [15:0]) appearing as binary value, 000x 00[...]

26 Specification Update BV17. PEBS Record not Upda ted when in Probe Mode Problem: When a performance monitoring counter is configured for PEBS (Precise Ev e nt Based Sampling), overflows of the counter can result in stor age of a PEBS record in the PEBS buffer . Due to this erra tum, if the ov erfl ow occurs during prob e mode, it ma y be ignored [...]

Specification Update 27 BV21. #GP on Segment Selector Desc riptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code Problem: During a #GP (General Protection Exception), the processor pushes an error code on to the exception handler’s stack. If the segment selector descriptor str addle s the canonical boundary , the e[...]

28 Specification Update BV24. Chang ing the Memory Type f or an In-Use Page Translation May Lead to Memory-Ordering Violations Problem: Under complex microarchitectural conditions, if softw are changes the me mory type for data being actively used and shared by mult iple threads without the use of semaphores or barriers, software may see load opera[...]

Specification Update 29 BV27. Fault Not Reported Wh en Setting Reserved Bits of Intel® VT-d Queued Invalidation Descriptors Problem: Reserv ed bits in the Queued Inv alidation descriptors of Intel VT -d (Virtualization T echnology for Directed I/O) are expected to be z ero, mean ing that software must program them as zero while the processor ch ec[...]

30 Specification Update BV30. Spurious Interrupts M ay be Gene rated From the Intel® VT-d Remap Engine Problem: If software clears the F (F ault) bit 127 of the F ault Recording Register (FRCD_REG at offset 0x208 in Remap Engine BAR) by wr iting 1b through RW1C command (R ead Write 1 to Clear) when the F bit is already clear then a spurious interr[...]

Specification Update 31 BV34. Processor May Fail to Acknowledge a TLP Request Problem: When a PCIe root port’s receiver is in R e ceiver L0s power state and the port initiates a Re covery event, it will issue T raining Sets to the link partner . The link partner will respond by initiating an L0s exit sequence. Prior to transmitting its own T rain[...]

32 Specification Update BV38. PerfMon Overflo w Status Can Not be Cle ared After Certain Condition s Have Occurred Problem: Under very specific timing conditions, if software tries to disable a P erfMon counter through MSR IA32_PERF_GLOBAL_CTRL (0x38F) or through the per-counter event- select (e.g. MSR 0x186) and the counter reached its overflow st[...]

Specification Update 33 BV41. PCI Express * Differential Peak-Peak Tx Vo ltage Swing May Violate the Specification Problem: Under certain conditions, including extrem e voltage and temperature, the peak -peak voltage may be higher than the specification. Implication: Violation of PCI Express® Base Specificatio n of the VTX --DIFF-PP voltage. No fa[...]

34 Specification Update BV44. IA32_FEAT URE_C ONTROL MSR May be Uninitialized on a Cold Reset Problem: IA32_FEA TURE_CONTROL MSR (3Ah) may have random v alues after RESET (including the reserved and Lock bits), and th e read-mod ify -write of the reserved bits and/or the Lock bit being incorrectly set may cause an unexpected GP fault. Implication: [...]

Specification Update 35 BV48. 64-bit REP MOVSB/STOSB May Clea r The Upper 32-bits of RCX, RDI And RSI Before Any Data is Transferred Problem: If a REP MOVSB/STOSB is executed in 64-bit mode with an address size of 32 bits, and if an interrupt is being recognized at the start of the instruction oper ation, the upper 32-bits of RCX, RDI and RSI ma y [...]

36 Specification Update BV52. Instructions Retired Event Ma y Over Count Execution of IRE T Instructions Problem: Under certain conditions, the performance monitoring event Instructions Retired (Event C0H, Unmask 00H) may over count the ex ecution of IRET instruction. Implication: Due to this err atum, performance monitoring ev ent Instructions R e[...]

Specification Update 37 BV56. PCI Express* Gen3 Receiver Re turn Loss May Exce ed Specifications Problem: The PCIe Base Specification includes a graph that sets requirements for maximum receiver return loss v ersus frequency . Due to this err atum, the receiver return loss for common mode and differential mode may ex ceed those requirements at cert[...]

38 Specification Update BV59. PCIe* May Associate Lanes That Are Not Part of Initial Link Training to L0 During Upconfiguration Problem: The processor should not associate any lane s that were not part o f the initial link training in subsequ ent upconfiguration requests from an endpoint. Due to this erratum, the processor may associate any Lane th[...]

Specification Update 39 BV63. PCIe* Root-port Initiated Comp liance State Transmitter Equalization Settings May be Incorrect Problem: If the processor is directed to enter PCIe P olling.Compliance at 5.0 GT/s or 8.0 GT/s transfer r ates, it should use the Link Control 2 Compliance Preset/De-emphasis field (bits [15:12]) to determine the correct de-[...]

40 Specification Update BV67. MSR_PKG_C x_ RESIDENCY MSRs May Not be Accurate Problem: If the processor is in a package C-state fo r an extended period of time (greater than 40 seconds) with no wak e events, the value in the MSR_PKG_C{2,3,6,7}_RESIDENCY MSRs (60D H and 3F8H–3F AH) will not be accurate. Implication: Utilities that report C-state r[...]

Specification Update 41 BV71. PCIe* Root Port May No t Initiate Link Speed Change Problem: The PCIe Base specification requires the up stream component to maintain the PCIe link at the target link speed or the highest sp eed supported by both components on the link, whichever is lower . PCIe root port w ill not initiate the link speed change withou[...]

42 Specification Update BV74. VM Exits Due to “NMI-Window Exit ing” May Not Occur Following a VM Entry to the Shutdown State Problem: If VM entry is made with the “virtual NM Is” and “NMI -window exiting” , VM-execution controls set to 1, and if there is no virtual-NMI blocking after VM entry , a VM exit with exit reason “NMI window?[...]

Specification Update 43 BV77. PCIe* Controller May Not Enter Loopback Problem: The PCIe controller is expected to enter loo pback if any lane in the link receives two consecutive TS1 ordered sets with the Loopba ck bit set. Due to this erratum, if two consecutive TS1 ordered sets are received only on certain lanes, the controller may not enter loop[...]

44 Specification Update BV81. PCIe* Link May Fail Li nk Width Upconfiguration Problem: The processor supports PCIe Hardware Au tonomous Width management, in which a PCIe link can autonomously vary its width. Du e to this erratum, a link that performs a speed change while in a reduced width may no longer be able to return to a wider link width. Impl[...]

Specification Update 45 BV85. Performance-C ounter Overflow Ind ication May Cause Und esire d Behavior Problem: Under certain conditions (listed below) when a performance counter ov erflows, its overflow indication ma y remain set indefinitely . This erratum affects the general- purpose performance counters IA32_PMC{0- 7} and the fixed-function per[...]

46 Specification Update BV88. Concurrently Changing the Memory Type and Page Size May Lead to a System Hang Problem: Under a complex set of microarchitectural conditions, the system may hang if software changes the memory type and pag e size used to translate a linear address while a TLB (T ranslation Lookaside Buffer) holds a v alid translation fo[...]

Specification Update 47 BV92. The Processor May No t Properly Execute Code Modif ied Using A Floati ng- Point Sto r e Problem: Under complex internal conditions, a floating-point store used to modify the next sequential instruction may result in the old instruction being ex ecuted instead of the new instruction. Implication: Self- or cross-modifyin[...]

48 Specification Update BV96. IA32_MC5_C TL2 is Not C leared by a W arm Rese t Problem: IA32_MC5_CTL2 MS R (285H) is documented to be cleared on any reset. Due to this erratum this MSR is only cleared upon a cold reset. Implication: The algorithm documented in Softw are Deve loper's Manual, V olume 3, section titled "CMCI Initialization?[...]

Specification Update 49 BV98. Performan ce Monitor Cou n ter s May Produce Incorrect Results Problem: When operating with SMT enabled, a memory at-retirement performance monitoring event (from the list below) may be dropped or may increment an enabled event on the corresponding counter with the same number on the physical core’ s other thread rat[...]

50 Specification Update BV100. Spurious VT-d Interrupts Ma y Occur When the PFO Bit is Set Problem: When the PFO (Primary F ault Overflow) field (bit [0] in the VT -d FSTS [Fault Status] register) is set to 1, further faults sho u ld not gener ate an interrupt. Due to this erratum, further interrupts may still occur . Implication: Unexpected Invali[...]

Specification Update 51 BV104. EPT Violations Ma y Report Bi ts 11:0 of Guest Linear Address Incorrectly Problem: If a memory access to a linear address requires the processo r to update an accessed or dirty flag in a pagin g-structure entry and if that update causes an EPT violation, the processor sh ould store the linear ad dress into th e “gue[...]

52 Specification Update BV108. Virtual-APIC Page Accesses Wi th 32-Bit PAE Paging May Cause a System Crash Problem: If a logical proc essor has EPT (Extended Pa ge T ables) enabled, is using 32-bit P AE paging, and accesses the virtua l-APIC page then a complex se quence of internal processor micro-architectur al eve nts may cause an incorrect ad d[...]

Specification Update 53 Specification Changes The Specification Changes listed in this section apply to the following documents: •I n t e l ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture •I n t e l ® 64 and IA-32 Arch i tec tu res Softwa re Developer’s Manual, Volume 2A: Instruction Set Reference Ma[...]

54 Specification Update Specification Clarifications The Specification Clarifications listed in this section may apply to the following documents: •I n t e l ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture •I n t e l ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set[...]

Specification Update 55 Documentation Changes The Documentation Changes listed in this section apply to the following documents: •I n t e l ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture •I n t e l ® 64 and IA-32 Arch i tec tu res Softwa re Developer’s Manual, Volume 2A: Instruction Set Reference Ma[...]

56 Specification Update § § DisplayFamily_Displa yModel DisplayFamily_Display Model DisplayFamily_Displa yModel DisplayFamily_Display Model 0F_xx 06_1C 06_1A 06_1E 06_1F 06_25 06_26 06_27 06_2C 06_2E 06_2F 06_35 06_36[...]