Intel 8XC196Jx manual

8XC196L x Supplement to 8XC196K x , 8XC196J x , 87C196CA User ’ s Manual August 2004 Order Numbe r: 272973-003[...]

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iii CONTENTS CHAPTER 1 GUIDE TO THIS M ANUAL 1.1 MANUAL CONTENTS ................ ............................ ............................ ........................... 1-1 1.2 RELATED DOCUMENTS ........... ................. ................ ................. ............................ ..... 1-2 CHAPTER 2 ARCHITECTURAL OVERVIEW 2.1 MICROCONTROLLER[...]

8XC196 L X SUPPLEMENT iv CHAPTER 6 SYNCHRONOUS SERIAL I/O PORT 6.1 SSIO 0 CLOC K REGISTER............. ................. ............................ ............................ ..... 6-1 6.2 SSIO 1 CLOC K REGISTER............. ................. ............................ ............................ ..... 6-2 CHAPTER 7 EVENT PROCESSOR ARRAY 7.1[...]

v CONTENTS 8.6 PROGRAMM ING THE J1850 CONTRO LLER ............ ............................ .................... 8-16 8.6.1 Programming the J1850 Co mmand (J_CMD) Registe r .......... ................. ...............8-16 8.6.2 Programming the J1850 Co nfiguration (J_CFG) Reg ister . ................ ................. .... 8-18 8.6.3 Programming th[...]

8XC196 L X SUPPLEMENT vi FIGURES Figure Page 2-1 8XC 196L x Block Diagram ........ ................. ................ ................. ................. .................2-2 2-2 Clock Ci rcuitry (87C196 LA, LB Only) ............. ................. ............................ ................. 2-3 2-3 Intern al Clock Phas es (Assu mes PLL i s Bypa[...]

vii CONTENTS FIGURES Figure Page 11-1 Slave Program ming Circui t ............ ............................ ............................ .....................11-3 11-2 Serial Port Programming C ircu it ..................... ................. ................. ................. ......... 11-4 A-1 87C196LA 52-p in PLCC Package .................. ....[...]

8XC196 L X SUPPLEMENT viii TA B L E S Ta b l e Page 1-1 Related Do cuments .................. ................. ................ ................. ................. .................1-2 2-1 Featu res of the 8XC196L x and 8X C196K x Product Famiies ................ .......................2-1 2-2 State Times at Various Freque nc ies .............. ..[...]

1 Guide to This Manual[...]

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1-1 CHAPTER 1 GUIDE TO TH IS MANUAL This docume nt is a supp lement to the 8XC196Kx, 8 XC196Jx, 8 7C196CA Micr ocont r oller Family User ’ s Manua l . It describes the dif ferences between the 8XC196L x and t he 8XC196 K x fami ly of microcontrollers. For inform ation not found in this su pplement, please cons ult the 8XC196 Kx, 8XC196Jx, 87C196C[...]

8XC196 L X SUPPLEMENT 1-2 Appendix A — Sign al Descript ions — pro vides reference inf o rmation for the 8 XC196L x de- vice pins, includ ing descri ption s of the pin functi ons, reset stat us of the I/O and contr ol pins, and package pin assignments. Glos sary — defines terms with special meaning used th rou gho ut this supplement. Index ?[...]

2 Ar chitectural Overview[...]

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2-1 CHAPTER 2 ARCHITECTURAL OVERVIEW This chapter describes architectural dif ferences between the 8XC196L x (8 7C196LA, 87C1 96LB, and 83C196 LD) and the 8XC196K x ( 8XC196K x , 8XC196J x , and 87 C196CA) microcon troller famili es. Both the 8XC196L x an d the 8XC1 96K x are designed fo r high-speed calculation s and fast I/O, and s hare a common [...]

8XC196 L X SUPPLEMENT 2-2 2.2 BLOCK DIAGRAM Figure 2-1 is a simplified block di agram that shows the major blo cks within the microcontro ller . Observe that the slave port peripheral does not exist o n the 8XC196L x . Figure 2-1. 8XC1 96L x Block Diagram 2.3 INTERNAL TIMING The 87C196LA, LB clock circu itry (Figure 2-2) imp lements a phase-locked [...]

2-3 ARCHITECTURAL OVERVIEW Figure 2-2. Clock Circuitry (87C196LA, L B Only) The rising edges of PH1 and PH2 generate the in ternal CLKOUT signal (Figure 2-3). The clock circuitry ro utes s eparat e internal cl ock sign als to the CPU an d the peri pherals to provi de flexi bil- ity in power man agement. It also outputs the CLKOUT signal on the CLKO[...]

8XC196 L X SUPPLEMENT 2-4 Figure 2-3. Internal C lock Phas es (Assumes PLL is Byp assed) The combined pe riod of phase 1 and ph ase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state . T able 2-2 lists state time durations at various frequencies. The following formu las calculate the frequency of PH1 and PH2,[...]

2-5 ARCHITECTURAL OVERVIEW Figure 2-4 . Effect of Clock Mo de on Internal CLKOUT Frequency 2.4 EXTERNAL TIMING Y ou can con trol the outpu t frequen cy on the CLKOUT pin by programming two uneraseable PROM bits. Figure 2-5 illustrates the read-only USFR1, which reflects the state of the unerasable PROM bits. Y ou can select one of three frequenci e[...]

8XC196 L X SUPPLEMENT 2-6 T o program these bits, write the correct value to the locations sho wn in T able 2-4 using slave pr o- gramming mode. During no rmal operation , you can determ ine the values of these bits by read ing the UPR OM SFR (Fi gure 2-5). Y ou can verify a UPROM bit to make sure it programmed, bu t you cannot erase it. For this r[...]

2-7 ARCHITECTURAL OVERVIEW 2.5.1 I/O P orts The I/O por ts of the 8XC196 L x are functionall y identical to those of the 8XC196J x . However , o n the 87C 196LA and LB th e reset st ate level of all 41 gener al-purpos e I/O pins h as changed fr om a weak logic “1” (wk 1) to a weak logic “0” (wk0). 2.5.2 Synchronous Serial I/O Port The synch[...]

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3 Addr ess Space[...]

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3-1 CHAPTER 3 ADDRESS SPACE This chapter describes the dif ferences in the address space of the 8XC196 L x from that of t he 8XC1 96K x . 3.1 ADDRESS PARTITIONS T able 3-1 is an address map of the 8XC196L x and 8X C1 96K x microcontr oller family members. T able 3-1. Addr ess Map Device and Hex Address Range Description Addressing Mode s CA JR, KR [...]

8XC196 L X SUPPLEMENT 3-2 3.2 REGISTER FILE Figure 3-1 compares the register file addresses of the 8XC196L x an d 8XC1 96K x . The register file i n Figu re 3-1 is divi ded int o an upper register f ile and a lower regi ster fi le. The u pper reg ister file co nsists of gen eral-purpose regi ster RAM. The lower r egister fi le contains general-pu r[...]

3-3 ADDRESS SPACE Figure 3-1. Register File Address M ap T able 3-2 . Register File Memory Addres ses Device and Hex Address Range Description Addr essing Modes JV CA,JT ,KT LA, LB JR, KR LD 1DFF 1C00 — — — — Register RAM Indirect, indexed, or windowed direct 03FF 0100 03FF 0100 02FF 0100 01FF 0100 017F 0100 Upper register file (register RA[...]

8XC196 L X SUPPLEMENT 3-4 3.3 PERIPHERAL SPECIAL-FUNCTION REGISTERS T able 3-3 li sts the pe ripheral SFR address es. Hi ghlig hted addr esses are un ique to th e 8XC19 6L x . T able 3-3. 8XC196L x Peripheral SFRs Ports 3, 4, 5, and UPROM SFRs Ports 0, 1, 2, and 6 SFRs Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte L ow (Even) Byte[...]

3-5 ADDRESS SPACE SIO and SSIO SFRs EP A SFRs (C ontinued) Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte L ow (Even) Byte 1FBEH Re served Reserved † 1F7EH EP A7_TIME (H) EP A7_TIME (L) 1FBCH S P_B AUD (H) SP_BAUD (L) 1F7CH Reserved EP A7_CON 1FBAH SP_CON SBUF_TX † 1F7AH EP A6_TIME (H) EP A 6_TIME (L) 1FB8H SP_ST A TUS SBUF_RX [...]

8XC196 L X SUPPLEMENT 3-6 3.4 WINDOWING W indowing maps a segment of high er memory (the u pper regist er file or periph eral SFRs) int o the lower r egister fi le. The window se lection register (WSR) selects a 32-, 64- or 128-byte seg- ment of higher memory to be windowed into the top of th e lower register file space. T able 3-4 lists the W SR v[...]

3-7 ADDRESS SPACE Register RAM (87C196JV Only; Continued) 1CE0H 67H 33H 19H 1CC0H 66H 1CA0H 65H 32H 1C80H 64H 1C60H 63H 31H 18H 1C40H 62H 1C20H 61H 30H 1C00H 60H Upper Register File (CA, JT , JV , KT) 03E0H 5FH 2FH 17H 03C0H 5EH 03A0H 5DH 2EH 038 0H 5CH 0360H 5BH 2DH 16H 0340H 5AH 0320H 59H 2CH 0300H 5 8H Upper Register File (CA, JT , JV , KT , LA,[...]

8XC196 L X SUPPLEMENT 3-8 Upper Register File (CA, JR, JT , JV , KR, KT , LA, LB, LD) 0160H 4BH 25H 12H 0140H 4AH 0120H 49H 24H 0100H 48H T able 3-4. Windows (Continue d) Base Address WSR V alue for 32-byt e Window (00E0–00FFH) WSR V alue for 64- byte Window (00C0–00FFH) WSR V al ue for 128-byte Window (0080–00FFH) NOTE: Locations 1FE0–1FFF[...]

4 Standard and P TS Interrupts[...]

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4-1 CHAPTER 4 STANDARD AND PTS IN TERRUPTS The interru pt structure of th e 8XC196L x is the same as that of the 8XC196J x . The o nly difference is that t he slave port in terrupts (INT08:06) now suppor t the J1850 co ntroller peripheral. 4.1 INTERRUPT SO URCES, V ECTORS, AND PRIORITIES Ta b l e 4 - 1 lists the 8XC 196Lx’ s int errupts s ources,[...]

8XC196 L X SUPPLEMENT 4-2 4.2 INTERRUPT R EGISTERS This sectio n describ es the chan ges in the inter rupt regi ster bit def initions for the 8XC1 96L x fam- ily . T able 4-1. Interrupt Source s, V ectors, and Priorities Interrupt Source Mnemonic Interrupt Controller Service PTS Ser vice Name V ector Prio rity † Name V ector Priority Nonmaskable [...]

4-3 STANDARD AND PTS INTERRUPTS 4.2.1 Interrupt Mask Registers Figures 4-1 and 4-2 illu strate the i nterrupt mas k registers for the 8XC196L x microcont rollers. INT_MASK Address: Reset State: 0008H 00H The interrupt mask (INT_MA SK ) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable[...]

8XC196 L X SUPPLEMENT 4-4 4.2.2 Interrupt Pending Registers Figures 4-3 and 4 -4 illustrate the interrupt pe nding registers for the 8XC1 96L x micro controllers. INT_MASK1 Address: Reset State : 0013H 00H The interrupt mask 1 (INT_MASK 1) register enables or disables (mask s) individual interrupt requests. (The EI and DI instructi ons enable and d[...]

4-5 STANDARD AND PTS INTERRUPTS INT_PEND Address: Reset State: 0009H 00H When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pendin[...]

8XC196 L X SUPPLEMENT 4-6 4.2.3 Peripher al T ransaction Se rver Register s Figures 4-5 and 4 -6 illustrate the P TS interrupt sel ect and service reg isters for the 8XC 196L x mi- crocont rollers. INT_PEND1 Address: Reset State : 0012H 00H When hardware detects an interrupt request, it sets the corresponding bit in the int errupt pending (INT_PEND[...]

4-7 STANDARD AND PTS INTERRUPTS PTSSEL Address: Reset State: 0004H 0000H The PTS select (PTSSEL) register selects either a P TS microcode routine or a standard interrupt service routine for each interrupt request. Setting a bit selects a PTS micro code routine; clearing a bit selects a standard interrupt service routine. In PTS modes that use the P[...]

8XC196 L X SUPPLEMENT 4-8 PTSSRV Address: Reset State: 0006H 0000H The PTS service (PTSSR V) register is used by the hardware to indicate that the final P T S interrupt has been serviced by the P TS routine. When PTSCOUNT reaches z ero, hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit, which requests the end- of-PT S interrupt. [...]

5 I/O Ports[...]

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5-1 CHAPTER 5 I/O PORTS The I/O por ts of the 8XC196 L x are functionall y identical to those of the 8XC196J x . However , o n the 87C19 6 LA and LB, the r eset state l evel of all 41 gen eral-purpose I/O pins has changed from a weak logic “1” (wk1) to a weak logic “0” (wk0) . This chapter o utlines the dif f erences between the 87C19 6LA, [...]

8XC196 L X SUPPLEMENT 5-2 input sign als s et SFD IR. Even if a pi n is to be u sed in sp ecial-func tion mo de, you must s till in i- tialize the pin as an inpu t or output by writing to th e port direction reg ister. Resistor R1 provides ESD pro tection for the pin. Input signals are buffered. Th e standard ports use Schmitt-trigg ered buf fers f[...]

5-3 I/O PORTS Figure 5-1. Ports 1, 2, 5, and 6 In ternal Structure (87 C196LA, LB Only) 5.2.1 Configuring Ports 1, 2, 5, and 6 (Bidirect ional Ports) Using the port mo de register , you can indivi dually configure each pin for port 1 , 2, 5, and 6 to operate either as a general-p urpose I/O signal (I/O mod e) or as a special-function signal (specia[...]

8XC196 L X SUPPLEMENT 5-4 impedance input, or open -drain outpu t. The port direction and data output reg isters select th e con- figuration for each pin. Complementary output means that the m icrocontroller driv es the signal high or lo w . High-impedance input means that the microcontr oller floats the signal. Open-drain output means that the mic[...]

5-5 I/O PORTS in using this pi n. Be certain that your system meets the V IH specificati ons during reset t o prevent inadvertent en try into ONCE mode or a test mode. 3. Following reset, P2.7/CLKOUT carries the strongly drive n CLKOUT signal. It is not held low . When P2.7/CLKOUT is configured as CLKOUT , it is always a complementary output . 5.3 [...]

8XC196 L X SUPPLEMENT 5-6 Figure 5-2. Ports 3 and 4 Inte rnal Structure (87C196LA, LB Only ) Q2 Q1 P x _REG P34_DRV Sample Latch PH1 Clock Internal Bus Address/Data P x _PIN D Q Weak Pullup RESET# Q3 Q4 Buffer Read Port LE 300ns Delay I/O Pin Bus Control Select 0 = Address/Data 1 = I/O RESET# A5264-01 150 Ω to 200 Ω R1 1 0 V SS Medium Pullup V [...]

6 Synchr onous Serial I/O Port[...]

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6-1 CHAPTER 6 SYNCHRONOUS SERIAL I/O PORT The synchronou s serial I/O (SSIO) port on the 8XC1 96L x has been enhance d, implementing two new special function reg isters (SSIO0_CLK and SSIO1_CLK) that allow you to select the oper- ating mode and configure the phase and polarity of the serial clock s ignals. 6.1 SSIO 0 CLOCK REGIS TER The SSIO 0 cloc[...]

8XC196 L X SUPPLEMENT 6-2 For transmissio ns, SSIO0_CLK det ermines whether the SSIO s hifts out data bi ts on rising or fall- ing clo ck edges. For rec eptions, SSIO0_CLK determin es whether the SSIO samples data bits on rising or fallin g clock edges. 6.2 SSIO 1 CLOCK REGIS TER SSIO1_CLK se lects the SSIO mo de of operat ion (standard, duplex, or[...]

6-3 SYNCHRONOUS SERIAL I/O PORT For transmissio ns, SSIO1_CLK det ermines whether the SSIO s hifts out data bi ts on rising or fall- ing clo ck edges. For rec eptions, SSIO1_CLK determin es whether the SSIO samples data bits on the risin g or falling clock ed ges. 2 CONPND Master Contention Interrupt Pending For channel-select master operations, th[...]

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7 Event Pr ocessor Array[...]

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7-1 CHAPTER 7 EVENT PROCESSOR ARRAY The EP A on the 8XC196L x is functionally identical to th at of the 8XC1 96J x ; however, the 8XC1 96L x has only t wo captur e/compare chan nels without pin s instead of four . In additi on, the 83C196LD has no compare-only channels. 7.1 EP A FUNCTIONAL OV ERVIEW T able 7-1 lists the capture/compare (with and wi[...]

8XC196 L X SUPPLEMENT 7-2 Figure 7-1. EP A Block Diagram (87C196LA, LB Only) Indirect Interrupt Processor Logic EPA x Interrupt A5269-01 Timer-Counter Unit EPA9 / COMP1 EPA8 / COMP0 EPA 3:0 EPA 3:0 Interrupts TIMER1 TIMER2 Compare-only Channel 1 Capture/Compare Channel 9 Compare-only Channel 0 Capture/Compare Channel 8 Capture/Compare Channel 6–7[...]

7-3 EVENT PROCESSOR ARRAY Figure 7-2. EP A Block Diagram (83C196LD Only) Indirect Interrupt Processor Logic EPA x Interrupt A5281-01 TIMER1 TIMER2 Timer-Counter Unit Capture/Compare Channel 9 Capture/Compare Channel 8 Capture/Compare Channel 6–7 Capture/Compare Channel 0–3 EPA9 EPA8 EPA 3:0 EPA 3:0 Interrupts[...]

8XC196 L X SUPPLEMENT 7-4 7.1.1 EP A Mask R egisters Figures 7-3 and 7 -4 illustrate the EP A m ask registers, EP A_MASK and EP A_MASK1, for th e 8XC1 96L x microcontroller family . EP A_MASK Addres s: Reset State: 1F A0H 0000H The EP A interrupt mask (EP A_MASK) register enables or disables (masks ) interrupts associated with the shared EP A x int[...]

7-5 EVENT PROCESSOR ARRAY 7.1.2 EP A Pending Registers Figures 7-5 and 7 -6 illust rate the EP A pend ing registers, EP A_ PEND and EP A_PEND1, for the 8XC1 96L x microcontroller family . EP A_PEND Addres s: Reset State: 1FA2H 0000H When hardware de tects a pending EP A 6–9 or OVR0–3, 8–9 interrupt request, it sets the corresponding bit in th[...]

8XC196 L X SUPPLEMENT 7-6 7.1.3 EP A Interrupt Pri ority V ector Register Figure 7-7 illust rates the EP A interrupt priority vector (EP A IPV) register for the 8XC 196L x mi- crocont roller f amily . EP AIPV Address: Reset State: 1FA8H 00H When an EP A x interrupt occurs, the EP A interrupt priority vector (EP AIPV) register contains a number that[...]

8 J1850 Communications Contr oller[...]

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8-1 CHAPTER 8 J1850 COMMUNICATIONS C ONTROLLER The J1850 communi cations controller manages communications between multip le network nodes. Thi s integrat ed peripher al supports the 10.4 Kb/s VPW (varia ble pulse wid th) medium- speed class B in-vehi cle network protocol. It also s upports bo th the st andard and i n-frame re- sponse (IFR) message[...]

8XC196 L X SUPPLEMENT 8-2 The J185 0 controll er can handle net work pr otocol fun ctions includ ing message frame s equenc- ing, bit arbitr atio n, in- frame re sponse (I FR) mes saging, er ror detecti on, and dela y comp ensatio n. The J1850 commu nications controller (Figure 8-2) consists of a control state machine (CSM), symbol s ynchronizati o[...]

8-3 J1850 COMMUNICATIONS CONTROLLER 8.2 J1850 CONTROLLER SI GNALS AND REGI STERS T able 8-1 des cribes the J1 850 con troller ’ s pins , and T able 8-2 de scri bes the contr ol and st atus regi ster s. T able 8-1 . J1850 Controller Signals Signal T ype Description RXJ1850 I Receive Carries digital symbols from a remote transceiver to the J1850 co[...]

8XC196 L X SUPPLEMENT 8-4 8.3 J1850 CONTROLLER OPE RATION This section describes the control state machine (which contains the cyclic redundancy check generator) and the sy mbol s ynchronizatio n and timin g circuitry for J185 0 transmissio ns and re- ceptions. 8.3.1 Control Sta te Machine The control state machine (CSM) represents the engine of th[...]

8-5 J1850 COMMUNICATIONS CONTROLLER 8.3.1.2 Bus Contention Bus contention arises when multiple nodes attempt to access and transmit message frames across the J1850 bus simultaneously . This creates a conflict on the bus. The r ecognition of conflicting symbols or bi t s on t h e bus i s ref erred to as con tention detection . For examp le, if a nod[...]

8XC196 L X SUPPLEMENT 8-6 8.3. 2.1 Cloc k Pr escal er Because the 87C196LB microco ntroller can operate at a variety of input freq uencies (F XT AL 1 ), the clock prescaler circ uitry is used to provide a single, intern al clock frequency ( f/2) to ensure that the J1850 perip heral is clocked at the proper o perating frequency . This is accomplishe[...]

8-7 J1850 COMMUNICATIONS CONTROLLER Figure 8-3. H untz icker Symbol Definiti on for J1850 A symbol is defined as a timing -level formatted bit. The VP W symbol timing requirements stip- ulate that there is one symbol per transition an d one transition per symbol. This ensures that a message frame will always resu lt in a uniform square wavefo rm of[...]

8XC196 L X SUPPLEMENT 8-8 of arbitration, nodes A, C, and D are all transmitting an “active 0” symbol, thus the id le state of the “passive 1” symbol is over ruled in favor of th e driven state of the “active 0” symbo l. Node C i s the next n ode to discont inue transmitt ing when it attem pts to tak e control of th e bus by transmittin[...]

8-9 J1850 COMMUNICATIONS CONTROLLER Figure 8-6. J1850 Message Frames A standard message frame is in itiated by th e responder and contain s no more than 1 1 data bytes to be trans mitted. An IFR m e ssag e is a request initi atin g the recipient(s) to res pond by transmit- ting data within the same frame. The following subsections describe each of [...]

8XC196 L X SUPPLEMENT 8-10 (J_CFG.7) and considers whethe r the IFR message response has a CRC byte appended. Figure 8-7 dep icts the SAE preferred, active-level state bit format timing for the NB. Figure 8-7. Huntzick er Symbol Defin ition for the Normaliz ation Bit 8.4.1.4 Start and End Message Fra me Symbols Five symbols are used to mark the sta[...]

8-1 1 J1850 COMMUNICATIONS CONTROLLER Figure 8-8. De finition for Start an d End of Frame Symbols T able 8-4 details the symbol timing characteri stics support ed by the 87 C196LB. T able 8-4. Huntzicke r Symbol Timing Ch aracteristics Name Symbol Bus Level T TX min T TX nom T TX max T RX min T RX max Uni ts Logic Level 0 0 Passive 60 64 68 34 <[...]

8XC196 L X SUPPLEMENT 8-12 8.4.2 In-frame R esponse Messaging There are three types of in-frame respon se (IFR) message framings : type 1 (a single byte fr om a single responder), type 2 (a single byte from multiple respo nders), and type 3 (multiple bytes from a single respon der). Like the standar d message frame, the IFR frame is compo sed of he[...]

8-1 3 J1850 COMMUNICATIONS CONTROLLER Figure 8- 10. IFR T ype 2 Messa ge Frame 8.4.2.3 IFR Messa ging T ype 3: Multiple Bytes, Single Respo nder IFR messag ing ty pe 3 (Figu re 8-1 1) is ideal fo r request ing la rge amo unts of i nformation fro m a single source i n your sys tem. Y ou can compile up to 12 byt es of dat a from a r emote node on a s[...]

8XC196 L X SUPPLEMENT 8-14 T ransmitting the message requires that you first program the J1850 command (J_CMD) register to specify the number of byt es you want to tra nsfer across th e J1850 bus. The numb er of bytes specified must include the header byte(s). After the start of frame (SOF) symbol is put on the bus, the first header byte is transfe[...]

8-1 5 J1850 COMMUNICATIONS CONTROLLER NOTE An overrun conditio n can occur on transmissi on if the transmit buffer , JTX_BUF , is overwritten. 8.5.2 Rece iving Messages For a message r eception, after a SOF is detected o n the bus, the contro ller starts to shift data sym- bols into the J1850 r eceive buffer (JRX_BUF) un til an entire data byte has[...]

8XC196 L X SUPPLEMENT 8-16 If a third byte is received before J_RX is read, a J1850ST core interrupt is generated and the OVR_UNDR (J_ST A T .3) bit records a receiver over run error in the J_ST A T register . 8.5.3 IFR Messa ges In-frame response (IFR) messaging is identical in setup to standard messagin g for both transmis- sion and reception. It[...]

8-1 7 J1850 COMMUNICATIONS CONTROLLER J_CMD Address: Reset State: 1F51H 00H The J1850 command (J_CMD) register determines the messaging type, specifies the number of bytes to be transmitted in the next m essage frame, and updates the status of the message transmission in progress. This byte register can be directly addressed through windowing . Y o[...]

8XC196 L X SUPPLEMENT 8-18 8.6.2 Programming the J185 0 Configuration (J_CFG) Register The J1850 configur ation register (Figure 8-17) selects the prop er oscillator prescal er , in itiates a transm ission b reak for deb ugging, invokes cl ock quadrup ling operati on, and se lects the no rmal- ization bit format. J_CFG Address: Reset St ate: 1F54H [...]

8-1 9 J1850 COMMUNICATIONS CONTROLLER 8.6.3 Programming th e J1850 Delay C ompensation (J_DL Y) Re gister The J1850 d elay comp ensation r egister (Figur e 8-18) allows you to program the n ecessary delay time through the external transceiver to compensate for the inherent propagation delays and to accurately resolve bu s contention during arbitrat[...]

8XC196 L X SUPPLEMENT 8-20 J_DL Y Address: Reset State: 1F58H 00H The J1850 delay (J_DL Y ) register allows you compensate for the inherent propagation delays and to accurately resolve bus contention during arbitration. Thi s byte register can be directly addressed through windowing . 7 0 — — — DL Y4 DL Y3 DL Y2 DL Y1 DL Y0 Bit Number Bit Mne[...]

8-2 1 J1850 COMMUNICATIONS CONTROLLER 8.6.4 Programming th e J1850 Status (J_S T A T) Register The J1850 status register (Figure 8-19) prov ides the current status o f the message an d the fo ur interrupt sources associated with the J18 50 protocol. J_ST A T Address: Reset State: 1F53H 00H The J1850 status (J_ST A T) register provides the current s[...]

8XC196 L X SUPPLEMENT 8-22 2 MSG_TX Message T ransmit Interrupt This bit signals the successful transmission of a mess age upon detecting the EOD symbol. 0 = no action 1 = mess age transmitted 1 MSG_RX Mess age Receive Interrupt This bit signals the successful reception of a message upon detecting the EOD symbo l. 0 = no action 1 = mess age receive[...]

9 Minimum Hardwar e Considerations[...]

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9-1 CHAPTER 9 MINIMUM HARDWARE CONSIDERA TIONS This chapter discusses the major hardware con sideration differences between the 8XC196L x and the 8XC196 K x . The 8XC196L x has implemented a reset sou rce SFR that reveals the source of the most recent reset requ est. 9.1 IDENTIFYING THE RESE T SOURCE The reset source (RSTSRC) registe r indicates th[...]

8XC196 L X SUPPLEMENT 9-2 9.2 DESIGN CONSIDE RATIONS FOR 8XC196 LA, LB, AND LD W ith the excepti on of a few new multip lexe d functio ns, the 8XC1 96L x microcontrolle rs are pin compatible wi th the 8XC1 96J x microc ontr ollers . The 8X C196J x microcontr ollers are 52-lead versio ns of 8XC196K x m icrocontrollers. Follow these recommen dations [...]

10 Special Operating Modes[...]

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10- 1 CHAPTER 10 SPECIAL OPERATING MODES The 8XC196 Lx’ s idl e and powerd own modes are t he same as t hose of the 8XC196 Kx. However , the clock circu itry has changed, and the on -circuit emulation (ONCE) special-pu rpose mode o p- eration has chang ed slightly because of the new reset state pin levels that have been implemented. 10.1 INTERNAL[...]

8XC196 L X SUPPLEMENT 10-2 Figure 10-1. Clock Circuitry (8 7C196LA, LB Only) 10.2 ENTERING AND EX ITING ONCE MODE ONCE mode isolates the device from other compone nts in the system to allow printed- circuit- board test ing or deb ugging with a clip-o n emulator . During ONCE mode, all pins except XT AL1, XT AL2, V SS , and V CC are weakl y pulle d [...]

10- 3 SPECIAL OPERATING MODES an out put. If you choose t o conf igure this pin as an input, al way s hold i t low d u rin g r e set an d en- sure that your sy stem meets the V IH specification to prevent inadvertent entry into ONCE mode.[...]

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11 Pr ogramming the Nonvolatile Memory[...]

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11- 1 CHAPTER 1 1 PROGRAMMING THE NONVOLATILE MEMORY The 87C1 96LA and LB mi crocontr ollers con tain 24 Kbytes (2000–7 FFFH) of one-tim e-pro- grammable read-only memo ry (OTPROM). OTPROM is similar to EPROM, but it comes in a windowless package and cannot be erased. Y ou have the o ption of programming the OTPROM yoursel f or hav ing the factor[...]

8XC196 L X SUPPLEMENT 11-2 1 1.3 SLAV E PROGRAMMING CIR CUIT AND ADDRESS MAP Figure 1 1-1 shows the cir cuit diagr am and T able 1 1-3 details the address map for slave pr ogr am- ming of the 87C1 96LA a n d LB dev ices. T able 1 1 -2. 87C196LA, LB OTPROM Address Map Address Range (Hex) Description 7FFF 2080 Program memory 207F 205E Reserved (each [...]

11- 3 PROGRAMMING THE NONVOLATILE MEMORY Figure 1 1- 1. Slave Progra mming Circuit T able 1 1-3. Slave Programming M ode Address Map Description Address Comments OTPROM 2000–7FFFH OTPR OM Cells OFD 0778H OTPROM Cell DED † 0 758H UPROM Cell DEI † 0718H U PROM Cell PCCB 0218H T est EPROM Programming V CC 0072H Read Only Programming V PP 0073H R[...]

8XC196 L X SUPPLEMENT 11-4 1 1.4 SE RIAL PORT PROGRAM MING CIRCUIT AND ADDRES S MAP Figure 1 1-2 sh ows the circuit and T able 1 1-4 details the addres s map for serial port prog ramming. Figure 1 1 -2. Serial Port Programming Circuit 5 9 4 8 3 7 2 6 1 1.8k Ω 1.8k Ω 1.8k Ω 1.8k Ω 1.8k Ω 10µF A5278-01 RXD TXD RXD TXD V CC 87C196LA, LB 30 [...]

11- 5 PROGRAMMING THE NONVOLATILE MEMORY T able 1 1-4. Serial Port Programm ing Mode Add ress Map Description Address Range Normal Operation Serial Port Programming Mode Internal OTPROM 2000–7FFFH A000–FFFFH External memory — 4000–9FFFH Do not address — 2400–3FFFH T est ROM and RISM — 2000–23FFH[...]

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A Signal Descriptions[...]

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A-1 APPENDIX A SIGNAL DESCRIPTIONS This appendix pr ovides reference inform ation for the pin functions of th e 8XC196L x microcon- trollers. A.1 FUNCTIONAL GROUP INGS OF SIGNALS T ables A-1, A-2, and A-3 list the signal assignments for the 8XC196L x microcontroller s, grouped by function. A diag ram of each microco ntroller shows the pin location [...]

8XC196 L X SUPPLEMENT A-2 T able A-1. 87C196LA Signa ls Arranged by F unctional Cate gories Addr & Data Input/Output (Cont’d) Program Control Processor Control Name Pin Name Pin Name Pin Name Pin AD0 22 P2.1 / RXD 28 AINC# 30 EA # 24 AD1 21 P2.2 29 CPVER 31 EXTINT 29 AD2 20 P2.4 30 PA C T # 3 2 PLLE N 6 AD3 19 P2.6 31 P ALE# 28 RESET# 23 AD4 [...]

A-3 SIGNAL DESCRIPTIONS Figure A-1. 87C1 96LA 52-pin PL CC Package P6.1 / EPA9 / COMP1 P6.0 / EPA8 / COMP0 P1.0 / EPA0 / T2CLK P1.1 / EPA1 P1.2 / EPA2 / T2DIR P1.3 / EPA3 V REF ANGND P0.7 / ACH7 / PMODE.3 P0.6 / ACH6 / PMODE.2 P0.5 / ACH5 / PMODE.1 P0.4 / ACH4 / PMODE.0 P0.3 / ACH3 5 1 . S U B P / 7 . 4 P / 5 1 D A # L R W / # R W / N E L L P / 2 .[...]

8XC196 L X SUPPLEMENT A-4 T able A-2. 87C196LB Signa ls Arranged by F unctional Cate gories Addr & Data Input/Output (Cont’d) Program Control Processor Control Name Pin Name Pin Name Pin Name Pin AD0 22 P2.1 / RXD 28 AINC# 30 EA # 24 AD1 21 P2.2 29 CPVER 31 EXTINT 29 AD2 20 P2.4 / RXJ18 50 30 PA C T # 3 2 PLLEN 6 AD3 19 P2.6 / TXJ1850 31 P AL[...]

A-5 SIGNAL DESCRIPTIONS Figure A-2. 87C1 96LB 52-pin PL CC Package P6.1 / EPA9 / COMP1 P6.0 / EPA8 / COMP0 P1.0 / EPA0 / T2CLK P1.1 / EPA1 P1.2 / EPA2 / T2DIR P1.3 / EPA3 V REF ANGND P0.7 / ACH7 / PMODE.3 P0.6 / ACH6 / PMODE.2 P0.5 / ACH5 / PMODE.1 P0.4 / ACH4 / PMODE.0 P0.3 / ACH3 5 1 . S U B P / 7 . 4 P / 5 1 D A # L R W / # R W / N E L L P / 2 .[...]

8XC196 L X SUPPLEMENT A-6 T able A-3. 83C196LD Signals Arrange d by Functional Categories Addr & Data Input/Ou tput Input/ Output (Cont’d) Processor Control Name Pin Name Pin Name Pin Name Pin AD0 22 P1.0/EP A0/T2CLK 44 P4.7 7 CLKOUT 32 AD1 21 P1.1/ EP A1 43 P5.0 2 EA# 24 AD2 20 P1.2/EP A2/T2DIR 42 P5.2 6 E XTIN T 2 9 AD3 19 P1.3/ EP A3 41 P5[...]

A-7 SIGNAL DESCRIPTIONS Figure A-3. 83C1 96LD 52-pin PL CC Package A.2 DEFAULT CON DITIONS T a ble A-5 lists the values of the s ignals f or the 8 7C196LA an d 87C196LB during various o per- ati ng con ditions. T able A-6 lists the same informati on for the 83 C196LD. T able A-4 defines th e sym bols used to represent the pin stat us. Refer to t he[...]

8XC196 L X SUPPLEMENT A-8 T able A-5. 87C196LA, LB Defa ult Signal Conditions Port Signals Alternate Function s During RESET# Active Upon RESE T# Inactive (Note 6) Id le P ower- down P0.7:2 ACH7:2 HiZ HiZ HiZ H iZ P1.0 EP A0/T2C LK WK0 WK0 (Note 1) (Note 1) P1.1 EP A1 WK0 WK0 (Note 1) (Note 1) P1.2 EP A2/T2D IR WK0 WK0 (Note 1) (Note 1) P1.3 EP A3 [...]

A-9 SIGNAL DESCRIPTIONS T able A-6. 83C196LD Defa ult Signal Conditi ons Port Signals Alternate Function s During RESET# Active Upon RESE T# Inactive (Note 6) Id le P ower- down P0.7 :2 — HiZ HiZ HiZ HiZ P1.0 EP A0/T2C LK WK1 WK1 (Note 1) (Note 1) P1.1 EP A1 WK1 WK1 (Note 1) (Note 1) P1.2 EP A2/T2D IR WK1 WK1 (Note 1) (Note 1) P1.3 EP A3 WK1 WK1 [...]

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Glossary[...]

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Glossary-1 GLOSSARY This gl os sary def i nes acronyms, abbreviati on s, and terms that have s peci al meanin g i n th is man- ual. (C hapter 1 d iscusses n otational co nventions and general terminol ogy .) absolute error The maximum dif ference between corresponding actual and ideal co de trans itions . Absolute error accounts for all deviations [...]

8XC196 L X SUPPLEMENT Glossary-2 byte Any 8 -b it unit of da ta. BYTE An unsigned, 8 -bit variable with valu es from 0 throug h 2 8 –1. CCBs Chip con f iguration byte s. The ch ip configuration regis ters ( CCRs ) are loaded with the contents of the CCBs a ft er a reset. CCRs Chip configuration registers. Regi sters that define the environmen t i[...]

Glossary-3 GLOSSARY contention The detection of conflictin g symbols or b its on the bus. cr osstalk See off-isola tion. DC inp u t leakag e Leakage current fro m an analog input pin to ground or to the reference v oltage (V REF ). deassert The act of makin g a signal inactive (disabled). The polarity ( h igh or low) is defi ned by the si gnal name[...]

8XC196 L X SUPPLEMENT Glossary-4 external address A 21 -bit a ddress is pres ented on the microcon trol l er’ s pins. The address deco ded by an external device depen ds on ho w many of these a ddress pins the external system uses. See also intern al addr ess . f Lowercase “f” rep resents the frequency of the internal clock. far constants Con[...]

Glossary-5 GLOSSARY internal address The 24-bit address tha t the micro con troller generates. See also external addr ess . interrupt controller The module resp on sible for handling in terrupts that are to be ser viced by interrupt ser vice r outines th at you prov ide. Also called the pr o grammable in terrupt contr o ller (PIC) . interrupt laten[...]

8XC196 L X SUPPLEMENT Glossary-6 maskable interrupts All interrupts except stack o verflow , unimplemented opcode, and so ftware trap. Maskable interrupts can be disabled (masked) by t he individual mask bits in t he interrupt mask registers, and their servicing can be disabled by the DI (dis able interrupt service) instruction. Each ma s k ab le i[...]

Glossary-7 GLOSSARY nonlinearity The maximum d eviation o f code transit ions of the term inal-b ased chara cteris tic from the corre- sponding code transitions of the ideal characte ris tic . nonmaskab le interrupts Interrupts that cann ot be masked (disabled) an d cannot be assign ed to the P TS for processing. The nonmaska ble interrupts are sta[...]

8XC196 L X SUPPLEMENT Glossary-8 prioritized interrupt NMI, stack overflow , or any maskable i nterrupt . T w o of the no nmask able interr upts (unimplemented opcode and software trap ) are not prioritized; they vector directly to the interru pt s e rvice routine when executed. program memory A partition of mem ory where instructions can be stored[...]

Glossary-9 GLOSSARY P TS vector A location in special-purpo se memory t hat holds the starti ng address of a PTS co ntr ol block . QUAD-WORD An unsigned, 64 -bi t variable with values from 0 throug h 2 64 –1 . The QUAD-WORD variable is supported on ly as the operand for the EB MOVI instruction . quantizin g error An unavoidable A/D conversion err[...]

8XC196 L X SUPPLEMENT Glossary-10 sample time u ncertainty The va ri ation in the sample time . sample w indow The period of time that begins when the sample capacitor is attached to a selected channel of an A/D converter and ends when the sample capacitor is disconnected from the selected channel. sampled inpu ts All in put pins, with the exceptio[...]

Glossary-11 GLOSSARY special-purpose memory A partit ion of memory used for storing th e interrupt vectors , PTS vectors , ch i p configu ration bytes, and sever al reser ved locations. standard interrupt Any mas k ab le in terrupt t hat is assigned to th e interrupt con troller for pr ocessi ng by a n interrupt service routine . state time (or sta[...]

8XC196 L X SUPPLEMENT Glossary-12 V CC rejection The proper ty of an A/D converter that causes it to ignore (reject) changes in V CC so that the actual characteristic is unaf fected by those chan ges. The effectiven ess of V CC r ejection is measured by the ratio of the chang e in V CC to the change in the actual characteristic . VPW V ar iable pul[...]

Index[...]

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Index-1 INDEX A Address map, 3-1 Address par titions map, 3-1 OTPROM, 11-1 program memory , 11-1 spec ial-pu rpo se me mory , 11 -1 ALE, idle, powerdown, reset status, A-8, A-9 B Bloc k dia g r am 8XC196 L x , 2-2 C CLKOUT and i nternal timin g, 2-2– 2-4 idle, powerdown, reset status, A-8, A-9 outp ut frequen cy, 2-5 reset status, 5-2 Clock circu[...]

Index-2 P Period (t), 2 -4 Port 0 idle, powerdown, reset status, A-8, A-9 overview, 5-1 Port 1 config uring, 5-3 idle, powerdown, reset status, A-8, A-9 overview, 5-1 Port 2 config uring, 5-3 idle, powerdown, reset status, A-8, A-9 overview, 5-1 P2.7 reset statu s, 5-2 Port 3 idle, powerdown, reset status, A-8, A-9 internal structure, 5-5 overview,[...]