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Intel 82551 manual

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Table of contents for the manual

  • Page 1

    Intel 8255x 10/100 Mbp s Ethernet Controller Family Open Source Software Developer Manual January 2006 Revision 1.3[...]

  • Page 2

    ii Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Information in thi s document is pro vided in connection with Int el ® products. This specificat ion, the Intel 825 5x 10/100 Mbps E thernet Controller Family Open Source Software Developer Manual, is provided “as is” wit h no warranties whatsoever ,[...]

  • Page 3

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual iii Contents Contents 1 Introduction . ................ ................ ............. ................ ................. ............ ................. ................ ........ 1 1.1 Scope . ................ ............. ................ ................ ..[...]

  • Page 4

    iv Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Contents 5 EEPROM Interface ................... ............. ................ ................ ............. ................ ................ .......... 25 6 Host Software Interface ....... ................ ............. ................ ...............[...]

  • Page 5

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual v Contents 7.3.6 100BASE-TX Receive Error Frame Counter: Register 21 ........ ................ ........... 127 7.3.7 Receive Symbol Error Counter: Register 22 ....... ................ ................... .............. 1 27 7.3.8 100BASE-TX Receive EOF Error C[...]

  • Page 6

    vi Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Contents 20 Transmit Buffer Descript or ...... ............. ................ ................ ................ ................ ................ ....... 85 21 Load Microcode Command Format ........... .................... ................ ...............[...]

  • Page 7

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual vii Contents 40 82559 Configuration Byte Map .. ................ ................. ................ ................... ................ ........... .. 65 41 82557 Dual-Port FIFO Settings - Transmit ....... ................... ................ ................[...]

  • Page 8

    viii Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Contents Revision History Date Revision Description January 2006 1.3 • Added Section 2.2.3.2., “82551ER Features.” • Modified the title of Appendix B. September 2005 1.2 • Corrected minor typing errors. September 2004 1.1 • Added Section 16,[...]

  • Page 9

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 1 Introduction 1 This document is intended for use as a soft ware technical reference manual for the Intel ® 10/100 Mbps Fast Ethernet controller family , which includes the 82557, 82558 , 82559, 82550, and 82551, as well as the 82562 Platform LAN Connect dev[...]

  • Page 10

    2 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Introduction 1.2 Document Co nventions 1.2.1 Device References This document encompasses inform ation for all members of the Inte l Fast Ethernet controllers: 82551, 82550, 82559, 82558, 82 557 and the 825 62. Note: The 82562xx/ICHx combination are program[...]

  • Page 11

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 3 Introduction • Dword alignment: Dword align ment implies that th e phys ical addresses may only be aligned on 4-byte boundaries. In other words, the last nibble of the address may only end in 0h, 4h , 8h, or Ch. Example: 0FECBD9A8h • Paragraph alignment:[...]

  • Page 12

    4 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Introduction[...]

  • Page 13

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 5 Adapter and Controller Overview 2 Adapters based on an Intel ® 8255x device support the ANSI/IEEE 802.3u standard for 100BASE- TX (100 Mbps operat ion) a nd 10BASE-T (10 Mbps operatio n). 2.1 Adapter Block Diagram The main components of Intel Fast Ethernet [...]

  • Page 14

    6 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Adapter and Controller Overvie w 2.2 Intel Fast Ethernet MAC Features 2.2.1 82557 Features • Glueless 32-bit, zero wait state PCI bus master interface compliant with PCI Specification, Revision 2.1. • 10 and 100 Mb ps support in compli ance with IEEE 8[...]

  • Page 15

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 7 Adapter and Controller Overview • Optional Flash support up to 64 Kbytes. (Th e 82557 is capable of larger Flash size support.) 2.2.3 82559, 82550, 8255 1, and 82562 Features The 82559, 82 550, and 82551 dev ices are supersets of th e 82557 and 8255 8. How[...]

  • Page 16

    8 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Adapter and Controller Overvie w[...]

  • Page 17

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 9 Power Management Interface 3 The 82557 has no power management supp ort. The 82558 added support for the Advanced Configuration and Power Interface (ACPI) Speci fication and limited su pport for W ake on LAN (WOL). The 82558 B-step upgraded and expanded t he[...]

  • Page 18

    10 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Power Management Inter face 3.4 Link Operation In the D0 state, the device maintains an active link. The 82558 B-step (refer to T able 2, “Device and Revision ID” on pa ge 13 ) and later devices also maintain an active link in the D3 state if PME is e[...]

  • Page 19

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 11 PCI Interface 4 4.1 PCI Configuration S p ace One of the most important functions for enabling superior configurability and ease of use is the ability to relocate PCI devices in the address spaces. By defaul t PCI devices support “Plug and Play .” When [...]

  • Page 20

    12 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual PCI Interface 4.1.1 V endor ID (Offset 0) This field identifies the device manufacturer . For the 82557 B-step this field equa ls 8086h. For the 82557 C-Step, 82558, and 8255 9, this field is automatical ly loaded from the EEPROM at power on or upon the a[...]

  • Page 21

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 13 PCI Interface 4.1.5 Revision (Offset 8) This register specifies a device specific revision identi fier . For the 82557 C-Step, 82558, and 82559, this field may be automatical ly loaded from the EEPROM at power on or upon the asserti on of a PCI reset. The d[...]

  • Page 22

    14 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual PCI Interface 4.1.6 Class Code (Offset 9) The class code, 020000h, identifies the device as an Ethernet adapter . 4.1.7 Cache Line Size (Offset C) This register specifies the system cache line size in units of 32-bit words and can be read or written to. T[...]

  • Page 23

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 15 PCI Interface 4.1.10 Built in Self T est (Offset F) This optional register is used for contro l and status of Built in Self T est (BIST). This register is hard-wired to 0 indicating th at the devices do not support BIST . Three base address register s are s[...]

  • Page 24

    16 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual PCI Interface The 8255x requires one BAR for I/O mapping and one BAR for memory mappin g of these registers anywhere within the 32-bit memory ad dress space. The driver determines which BAR (I/ O or Memory) is used to access the Control/S tatus Registers.[...]

  • Page 25

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 17 PCI Interface the Flash. The 82557 implements th is register regardless of the presence or absence of a Flash component on the adapter . For the 82558 and later Fast Ethernet controllers, this register is only implemented if a bit is set in the EEPROM. The [...]

  • Page 26

    18 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual PCI Interface 4.1.17 Max_Lat / Min_Gnt (Offset 3E) These registers specify the device settings for Lat ency T imer values. For both regi sters, the value specifies a period of time in units of ¼ micros econd. Min_Gnt is used to sp ecify the burst le ngth[...]

  • Page 27

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 19 PCI Interface 4.1.18.4 Power Management Control/S t atus (Offset E0) The Power Management Control/Status Register (PMCSR) is used to determine and change the current power state of the device. It also allows for the con trol of the power managem ent interru[...]

  • Page 28

    20 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual PCI Interface While wake-up events are not allowed in the D0 power state, hardware does not automatically preclude this functionality . T o ensure that wake-up events are not generated when in D0, software must clear the PME Enable bit when putting the de[...]

  • Page 29

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 21 PCI Interface 4.1.18.5 Ethernet Power Consum ption Register s (Offset E2h) The Data Register is an 8-bit read-only register prov iding a m echanism for the device to report state dependent maximum power con sumption and heat dissipation. The value reported [...]

  • Page 30

    22 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual PCI Interface T able 7. Generated PCI Comma nds The controllers do not generate I/O commands, Interru pt Acknowledge cycles, or Configuration cycles. The controllers also do not support Dual Address Cycle (DAC). T argets (typically the system bridge) must[...]

  • Page 31

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 23 PCI Interface device may start the next cycle using either MW or MWI according to the conditions listed above. If the PCI latency timer o r the 82558 (or later generation device) arbitration co unter expires during a MWI cycle, the device continues the cycl[...]

  • Page 32

    24 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual PCI Interface[...]

  • Page 33

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 25 EEPROM Interface 5 The 8255x has a local memory interface that provides access to a serial EEPROM and optional Flash device. All controllers im plement these interfaces using mu ltip lexed pins. Since the interface uses multiplexed pins, it is not simultane[...]

  • Page 34

    26 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual EEPROM Interface[...]

  • Page 35

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 27 Host Software Interface 6 The 8255x LAN con trollers establis h a shared memory communication system with the host CPU. Software controls the device by writing and readi ng data to and from this s hared memory space. All of the LAN controller functi ons (co[...]

  • Page 36

    28 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface The CBL consists of a linked list of individual action commands in st ructures called Command Blocks (CBs). The CBs contain command parameters and status of the action comman ds. Action commands are categorized as follows: • Non-[...]

  • Page 37

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 29 Host Software Interface 6.2 Initializing the LAN Controller A hardware or software reset prepares the 8255 x for normal operation. Si nce the PCI Specification already provides automatic conf iguration of many critical parameters such as I/O, memo ry mappin[...]

  • Page 38

    30 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface T o support linear addressing, the devi ce should be programmed as follows: • Load a value of 00000000h into the CU base usin g the Load CU Base Address SCB command. • Load a value of 00000000h into the RU base usin g the Load [...]

  • Page 39

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 31 Host Software Interface As the table above i ndicates, the 82 55x have the sam e alignment restrictio ns with one exception: The 82558, and 82559 hav e a limited capability to suppo rt odd byte aligned buffers. 6.3 Controlling the Device Software issues con[...]

  • Page 40

    32 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface • SCB Command W ord. This register is where software writes commands for the CU and RU. • SCB Status W ord. The device place s the CU and RU status for th e CPU to read in this word. • SCB General Pointer . The SCB General Po[...]

  • Page 41

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 33 Host Software Interface preferred method of accessing the CSR. Some bridges may not properly transfer data in memory mapped mode and it may be necessary to have an I/O backup method if the memo ry method does not work. Note: All fields in the CSR are byte, [...]

  • Page 42

    34 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface — A flow control pause frame was received (FCP Interrupt). This do es not apply to the 82557. Note: TNO interrupts should be avoided. Protocol stacks automati cally retry failed transmits. Th is feature should only be enabled if [...]

  • Page 43

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 35 Host Software Interface malfunctions. It is simply ignored by the dev ice. Also, any 0 bits in the interrupt acknow ledge command have n o effect, whether the interrup t is pending or n ot. T able 13. SCB Statu s Word Bit s Descriptions Bit Symbol Descripti[...]

  • Page 44

    36 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface Note: The SCB Status word is not updated imm ediately in response to SCB commands. For example, the CU status will remain in the idle state for a period of time after the C U start command is issued. Software should not rely exclus[...]

  • Page 45

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 37 Host Software Interface When software wants to issue an action command, it should write to the Command b yte. The CUC and RUC fields of the Command by te specify the actions to be performed by the 82 55x. The command is ready for acceptance by the device as[...]

  • Page 46

    38 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface Bits 23:20 CUC This field contains the CU Command. V alid values for this field a re: 0000 NOP . The no operation command does not affect the current state of the unit. 0001 CU S tart. CU S tart begins execution of the fir st comma[...]

  • Page 47

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 39 Host Software Interface 6.3.2.3 SCB General Pointer The SCB General Pointer i s a 32-bit entity , w hich po ints to variou s data structu res depending on the command in the CUC or RUC fi eld. The two tables below in di cate what the SCB pointer means for t[...]

  • Page 48

    40 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface 6.3.2.4 S t atistical Counters The 8255x provides i nformation for network manageme nt by providing on-ch ip statistical counters that track a variety of events associated with both transmit and receive. The counters are upd ated b[...]

  • Page 49

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 41 Host Software Interface 28 T ran smit multiple collisions. This counter contains the number of transmitted frames that encountered more than one collision. 32 T ran smit total collisions. This counter contains the total number of collisions that were encoun[...]

  • Page 50

    42 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface As the above table indicates, the 8255x track of 16 dif ferent statistics. However, the 82558 also maintains three addit ional statistics (lightly shaded in the abov e table) for a total of 19 co unters. In addition to the 19 stati[...]

  • Page 51

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 43 Host Software Interface 3. W rite zeros to the last Dword in this area. This can be done before or after step 2. 4. W rite the Dump Statistical Counters or D ump and Reset Statistical Counters co mmand into the CUC field in the SCB. 5. W a it for the device[...]

  • Page 52

    44 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface 6.3.3.1 PORT Sof tware Reset The Port Software Reset is synonymous with the so ftware reset and is used to issue a complete reset to the device. Software must wait fo r ten sy stem clocks and five transmit clocks before accessing t[...]

  • Page 53

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 45 Host Software Interface Note: The self-test does not generate an interrupt or similar ind icator to the host CPU upon completion. 6.3.3.3 Port Selective Reset The Port Selective Reset is usef ul when only the device needs to be reset and all configuration p[...]

  • Page 54

    46 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface The serial EEPROM or equivalent integrated ci rcuit (IC) stores configuration data for the controller and the adapter . The EEPROM is a seri al in and serial out device. Serial EEPROMs range in size from 16 to 256 re gisters of 16 [...]

  • Page 55

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 47 Host Software Interface 6.3.4.2 Sof tware Determin ation of EEPROM Size T o determine the size of the EEPROM, software may use the following steps. Note: This algorithm will only work if the EEPROM drives a dummy zero to EEDO after receiving the complete ad[...]

  • Page 56

    48 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface 6.3.4.3 Sof tware Read Access from the EEPROM T o read from the EEPROM, software is required to perform the following steps. The example is a read from address 02h (0000 0010b). Note: Since the address field is written mo st signif[...]

  • Page 57

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 49 Host Software Interface 6.3.4.4 Sof tware Writ e Access to the EEPROM W rite access to the EEPROM is similar to the read access outlined above, with the differences of a write opcode an d step 4: 1. Activate the EEPROM by writing a 1 to the EECS bit. 2. W r[...]

  • Page 58

    50 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface The MII Management Interface allows software to have direct control over a MII compatible PHY through a control register in the device. This allows the driver software to place the PHY in specific modes such as full duplex, loopbac[...]

  • Page 59

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 51 Host Software Interface b. Interrupt Enable (bit 29) = 1 or 0 c. Opcode (bits 27:26) = 01b (writ e) d. PHY Add = the PHY addr ess from the MDI register e. RegAdd = the register addr ess of the specific register to be accessed (0 through 31) f. Data = data t[...]

  • Page 60

    52 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface to increase performance by decreasing NOS receive latencies. However , most software early interrupt schemes would increase CPU uti lization and software complexity . Thus, use of this register is not recomm ended. Bits 13:1 1 of t[...]

  • Page 61

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 53 Host Software Interface words before the end of the frame. If the T ype/Le ngth field contai ns a T ype value, the device does not generate an early interrupt, except in the case where the T ype value is 8137h (IPX) or 0800h (IP) and the device is configure[...]

  • Page 62

    54 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface • Bits 23:21 - Reserved. These bits are reserved. • Bit 20 - FC Paused Low . This read only bit is an indicati on of the device flow control state. It is set by the device when it receives a paus e low command with a value grea[...]

  • Page 63

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 55 Host Software Interface The PMDR has evolved over t ime in the various In tel Fast Ethernet control lers. The PMDR bits for the 82558 and 82559 are described below . Note: Not all bits are meaningful in the different generations of devices. For the 82559, P[...]

  • Page 64

    56 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface 6.3.10 General Control Regis ter The General Control register provides contro l over some general purpose features in the 82559. It is an 8-bit field at offset 1Ch of the CSR. Th is register is only present in the 82559 and later g[...]

  • Page 65

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 57 Host Software Interface 6.4 Shared Memory S tructures The 8255x shared memory structures consist of the Command Block List (CBL) and the Receive Frame Area (RF A) and are controlled by the SCB por tion of the CSR. The SCB is internal to the device while the[...]

  • Page 66

    58 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface 6.4.1.1 General Ac tion Command Format The format common to all actio n commands and the algorithms for begin ning and completing th e execution (also common to all acti on commands) is described below . The general format of the C[...]

  • Page 67

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 59 Host Software Interface The following sequence is performed by the CU at the completion of execution of an action command : 1. The devices writes command specific status to th e status word of the cu rrent CB (usually the C and OK bits are written to). If t[...]

  • Page 68

    60 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface After reading the command and determining it is a NOP , the device CU performs the following sequence: 1. Begins execution of the NOP action command. 2. Prepares the status word with C equal to 1 and OK equal to 1. 3. Completes the[...]

  • Page 69

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 61 Host Software Interface The individual address is transferred by the tr ansmi t DMA through the transmit FIFO to the execution machine in the CSMA/CD mo dule. Therefore, it may take some time to execute. The execution unit maintain s a 48-bit individual add[...]

  • Page 70

    62 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface The individual bit fields of the con figure co mmand is another area where there are numerous differences between the controllers (82557, 82 558, 825 59, etc.). Therefore, a complete configuration map for each device wi ll be prese[...]

  • Page 71

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 63 Host Software Interface 1 8 11110 Receive CRC T ransfer Padding S tripping 19 FDX Pin Enable Force FDX 000000 20 0 Multiple IA 111111 2 1 0000 Multicast All 101 T able 38. 82557 Configuration Byte Map Byte D7 D6 D5 D4 D3 D2 D1 D0[...]

  • Page 72

    64 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface Note: The shaded bits in the table above have dif ferent meaning for the 82558 B-step. T a ble 39. 82558 Configuration Byt e Map Byte D7 D6 D5 D4 D3 D 2 D1 D0 0 0 0 Byte Count 1 0 Transmit FIFO Limit Receive FIFO Limit 2 Adaptive I[...]

  • Page 73

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 65 Host Software Interface 6.4.2.3.1 Configuration Parameters The interpretation of the fields fr om t he configuration byt e maps are: • BYTE 0. T able 40. 82559 Configuration Byte Map Byte D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 Byte Count 1 0 Transmit FIFO Limit Re[...]

  • Page 74

    66 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface Bits 5:0 - Byte Count. The byte count indicates the number of Command Block bytes to be configured (and is always included in the count). It allows changing some of the parameters by specifying a byte count le ss than the maximum n[...]

  • Page 75

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 67 Host Software Interface T able 42. 82557 Dual-Port FIFO Settings - Receive Configuration V alue (Nibble Wide) Receive FIFO Limit Binary (Receive Bits 3:0) Dwords Bytes 0 0 0 0 16 64 0 0 0 1 15 60 0 0 1 0 14 56 0 0 1 1 13 52 0 1 0 0 12 48 0 1 0 1 1 1 44 0 1 [...]

  • Page 76

    68 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface • BYTE 2: Adaptive IFS. Th is byte indicates the minimum number of PCI clocks counted between sending two transmit frames on the wire. The resolution of this counter is 8 PCI clocks making the range from 0 to 2040 PCI clocks. Def[...]

  • Page 77

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 69 Host Software Interface systems that are extremely cache line oriented . More information of the read alignment capability is detailed in Section 4.2.2, “Read Align” . 0 = Read Alignment disabled. 1 = Read Alignment enabled. Default - 0 (Read Alignment [...]

  • Page 78

    70 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface no other intern al DMA channels are requesti ng a transfer , the tran smit DMA may perform an extended PCI burst. In order for this counter to be enabled, the DMA maximum byte count enable bit (byte 5, bit 7) must be set. If the en[...]

  • Page 79

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 71 Host Software Interface — Bit 4 - Extended T ransmit CB (TxCB). This bit is reserved on the 82557 and should be set to 1. However , for the 82558 or 82559, it determines the ty pe of TxCB that is to be used by the device. If this bit is 1, the device r ea[...]

  • Page 80

    72 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface Default - 0. Recommended - 0. — Bit 0 - Late SCB = Late SCB Update. This bit is reserved on the 82558 and 82559 and should be set to 0 on those devices. This bit only has meaning on the 82 557 and determines when the device updat[...]

  • Page 81

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 73 Host Software Interface 0 (00) = No re-transmission . If a transmitted frame encounters an underrun it will not be re-transmitted and the status indicating that the transmission failed will be returned and counted in the transmit underrun counter . 1 (01) =[...]

  • Page 82

    74 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface device transfers data to and from the link. So ftware should alway s set this bit to 0 when it is issuing a configure command with more than 8 bytes. 0 = Enable. 1 = Disable. Default - 0. Recommended - 0. • BYTE 9. — Bit 7 - Mu[...]

  • Page 83

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 75 Host Software Interface Default - 0 (off). Recommended - 0. VLAN TCO: On the 82559, this bit activates VL AN capability filter ing of received TCO packets at nominal D0 state. When this bit is clear, the 82559 implements receive TCO in D0 for non-tagged TCO[...]

  • Page 84

    76 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface Default - 1. Recommended - Depends on the NOS and driver environ ment. • BYTE 1 1. — Bits 2:0 - Linear Priority . These bits are reserved on the 82558 and 82559 an d should be set to 000b on those devices. For the 82557, these [...]

  • Page 85

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 77 Host Software Interface Similarly , the value at offset 14 of the configuration block is co mpared to the byte at offset 40 in ARP frames without a VLAN header and to byte 44 in ARP frames with a VLAN header . The 16-bit value of the IP address in the confi[...]

  • Page 86

    78 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface Default - 0 (disabled). Recommended - 0. — Bit 1 - Broadcast Disable. When this bit is set, it disables the de vice from receiving any frames with a broadcast address (address of all 1s). Promiscuous mode setting overrides broadc[...]

  • Page 87

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 79 Host Software Interface byte (7Eh) will be transmit ted to pad (in other words, fill) the minimum frame length . The CRC will include the padded bytes. If padding is disabled, no padding bytes will be added even if the frame is a short frame. Default - 1 (e[...]

  • Page 88

    80 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface — Bit 6 - Force Full Duplex. This bit forces the device to operate in full duplex mode. T ransmit and receive execution can be act ive simultaneously . CRS is only a receive activity indicator . Minimum reception sp acing betw ee[...]

  • Page 89

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 81 Host Software Interface Recommended - 0. — Bit 0 - Address W ake-up (82558 A-step); IA Ma tch W ake Enable (82558 B-step). This bit is reserved on the 82557 and 82559 and should be set to 0 on those devices. When this bit is set on the 82558 A-step, it en[...]

  • Page 90

    82 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface In the case of a port selective reset, the execution machine maintain s configuration registers for the device. In the case of a port software reset or a hardware reset, the devi ce reverts to the default values. 6.4.2.4 Multicast [...]

  • Page 91

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 83 Host Software Interface The transmit DMA transfers the list of multicast addresses from memory to the execution machine through the transm it FIFO. The CU p erforms the fol lowing sequence: 1. Begins execution of the multicast setup action comm and. 2. Read[...]

  • Page 92

    84 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface Link Address This is the 32-bit address of the next co mmand block. It is added to the CU base to obtain the actual address. EL (Bit 31) If this bit is set to one, it indicates t hat this command block is the last one on the CBL. T[...]

  • Page 93

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 85 Host Software Interface The 82558 and 82559 also offer a more advan ce transmit command block. When they are configured to use extended TCBs, the device r eads an 8-Dword TCB from host memory into its internal registers instead of the standard 4-Dword TCB. [...]

  • Page 94

    86 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface 6.4.2.5. 1 Dynam ic TBD Mode Note: Dynamic TBD mode only exists in the 82558 and 82559 devices. It is not a valid m ode for the 82557. The 82557 requires all TBDs to be setup by the driv er before the device is issued the CU start [...]

  • Page 95

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 87 Host Software Interface 5. Fetch data if the transmit buffer pointer is zer o (invalid) in the second TBD or poll the TBD. 6. Finish the t ransmission if th e EL bit is set . 6.4.2.5.2 T ransmit Command Operation The execution of a tran smit command causes [...]

  • Page 96

    88 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface While the CU pre-fetches the address and byte count of on e buffer , the transmit DMA is transferring the previous buffer to the transmit byte machine. Completion of a buffer transfer by the transmit DMA triggers the CU to initiate[...]

  • Page 97

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 89 Host Software Interface 2. The SFD field is transferred. 3. Start CRC calculation. 4. Read and transfer the 6 destinati on address bytes from the transmit FIFO. 5. If the no source address insertion configuration parameter is zero, the individual address sh[...]

  • Page 98

    90 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface • The device received a frame and generated a receive interrupt. If neither of these events occurred, the controll er generates a CNA interrupt when the CID time interval has elapsed. The actual delay experienced may be longer th[...]

  • Page 99

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 91 Host Software Interface The load microcode command instruct s the device to download microcode data from host memory into its internal microcode RAM. The microcode data is organized as a 64-Dword memory block that is appended to a standard command block hea[...]

  • Page 100

    92 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface Configuration parameters and content s of other registers are transferre d from the CSMA/CD unit through the status FIFO by the Command Unit to memory . The CU performs the follo wing sequence: 1. Starts the dump action command. 2.[...]

  • Page 101

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 93 Host Software Interface 5 FEXT RCV_R D Current Address Register (high) 6 FEXT RCV_R D Base Address Register (low) 7 FEXT RCV_R D Base Address Register (high) 8 FEXT EXEC_WR Current Address Counter (low) 9 FEXT EXEC_WR Current Address Counter (high) 10 FEXT [...]

  • Page 102

    94 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface 43 Individual Address Register 5 44 Individual Address Register 6 45 Transmit S tatus (low byte) 46 Transmit S tatus (high byte) 47 Transmit CRC 0 48 Transmit CRC 1 49 Transmit CRC 2 50 Transmit CRC 3 51 Receive CRC 0 52 Receive CR[...]

  • Page 103

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 95 Host Software Interface T able 51. Dump Data Dwords (20-1 48) Dword Byte 3 Byte 2 Byte 1 20 – 29 Reserved 30 Micromachine (MM) Register File 39 31 Micromachine (MM) Register File 38 32 Micromachine (MM) Register File 37 33 Micromachine (MM) Register File [...]

  • Page 104

    96 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface 88 Micromachine Register File 29 89 Micromachine Register File 28 90 Micromachine Register File 27 91 Micromachine Register File 26 92 Micromachine Register File 25 93 Micromachine Register File 24 94 Micromachine Register File 23 [...]

  • Page 105

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 97 Host Software Interface 6.4.2.8 Diagnose (1 1 1b) The diagnose command triggers an internal self-test procedure that checks the internal device hardware. Its format i s illustrated below . 126 Micr omachine Input Port 3 127 Micr omachine Input Port 2 128 Mi[...]

  • Page 106

    98 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface The diagnose command checks the foll owing internal device circuitry: • Exponential backoff random number generator (linear feedback shift register). • Exponential backoff time-out counter . • Slot time period co unter . • [...]

  • Page 107

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 99 Host Software Interface During Phase 1, the linear feedback shift register (LFSR), exponential backoff time-out, slot time, and collision counters are checked. The te st is performed in the following manner: 1. All counters and shift regist ers are reset si[...]

  • Page 108

    100 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface 6.4.3.1. 2 Recei ve Frame Des criptor F ormat Figure 24. Simplified Memory Structure Figure 25. Receive Frame De scriptor Format Offset Command Word Bits 31:16 St atus Word Bits 15:0 00h EL S 000000000 H S F 000 C 0 OK S tatus Bit[...]

  • Page 109

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 101 Host Software Interface Link Address The link address is a 32-bit offset to the next RFD. It is added to the RU base. The link address of the last frame can be used to form a cyclical lin k to the first RFD. Size This field is used in the simplified mode a[...]

  • Page 110

    102 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface 6.4.3.2 Initial Recei ve Frame Area S tructure T o enable the device to receive frames, so ftware must setup th e following structure: 1. The SCB general pointer in the SCB should poi nt to the first RFD on the list. 2. The link o[...]

  • Page 111

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 103 Host Software Interface For every frame, the RU configures a RFD in memory . The load ing of each buf fer is done by the receive DMA in parallel with pr e-fetching the next buffer by the RU. After co mpleting frame reception, the RU closes the last RFD and[...]

  • Page 112

    104 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface 4. If the RU start request and S bits are set, a new RFD is created and the state is changed to suspended. 5. If the RU state is not ready , frames should be discarded. 6. If the RU is in the ready state or has just exited the rea[...]

  • Page 113

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 105 Host Software Interface Example 2. Numerical Calcula tion Assume the following incoming packet: SA DA T yp e F1 F5 54 79 E7 9E F5 CRC S 0 = F5F1+7954 = 6F45, C 0 = 1 S 1 = 6F45 + 9EE7 + 1 = 0E2D, C 1 = 1 S 2 = 0E2C + 00F5 + 1 = 0F23, C 2 = 0 Check Sum = S [...]

  • Page 114

    106 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface 6.5.3 Command Unit Control The CU is the 8255x logical unit that executes action commands from the command block list (CBL). This section describes how software controls the execution of action commands. Specifically , start, stop[...]

  • Page 115

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 107 Host Software Interface 6.5.3.2 CU Resume Command The CU Resume (CU_RESUME) comm and resumes CU operation. The 8255x completes th e following sequence: 1. If the CU is in the suspended state it goes to the active state an d requests the beginn ing of the n[...]

  • Page 116

    108 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface 6.5.4 Receive Unit Control The receive unit (RU) is the logi cal unit that receives frames and st ores them in memory . It uses free buffers and descriptors prepar ed by the CPU. This section describes how the CPU controls frame r[...]

  • Page 117

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 109 Host Software Interface Frames arrive at the device indepe ndent of the state of the RU. When a frame is arri ving, the 8255x is referred to as actively receivi ng, even when the RU is not in the ready state and the frame is being discar ded. Software can [...]

  • Page 118

    110 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface 6.5.4.2 RU Resume Command The RU Resume (RU_RESUME) command resume s frame reception. Th e RU performs the following tasks: 1. The RU goes to the ready state and configures a new RFD if the RU is in the suspended state and not act[...]

  • Page 119

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 111 Host Software Interface 6.6.1 PHY Based Flow Control The 82558 supports t he PHY based flow co ntrol scheme known as the “Bay Flow Control” scheme. This scheme is supported only when the 82558 is op erating using its internal PHY TX unit. It is not sup[...]

  • Page 120

    112 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface A flow control frame is identified by a special type field (bytes transmitted left to right): 88 to 80. The reception of a FC frame can be done either th rough the regular indivi dual address filtering mechanism or by a special mu[...]

  • Page 121

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 113 Host Software Interface Flow control is set by three configuration bits: on e for transmit and two fo r receive flow control. The default setting i s off ( Section 6.4.2.3, “Configure (010b)” ). Software can interrogate the N- W ay registers to determi[...]

  • Page 122

    114 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface immediately . If the pause time (from the device) has expired, the controller starts monitorin g the FIFO again to determine if a new pause command should be sent . The two modes, ReStop and ReS tart, can be used together . The co[...]

  • Page 123

    Intel 8255x 10/100 Mbps Ethernet Cont roller Family Open Source Software Developer Manual 115 Host Software Interface 6.6.3 Priority Aw are Frame Based Flow Control The 82558 and l ater generation contro llers have the abili ty to respond to priority aware frame based flow control frames. Their operation relates to mul tiple queues. 6.6.3.1 Priorit[...]

  • Page 124

    116 Intel 8255x 10/100 Mbps Eth ernet Controller Fami ly Open Source Software Developer Man ual Host Software Interface The priority field is the field that differentiates between pause and pause lo w frames. Only the three least significant bits in this byte are considered. These three bits are compared to the FC priority threshold configuration f[...]

  • Page 125

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 117 Physical Layer Interface 7 Intel Fast Ethernet adapters all have a physical layer (PHY) com ponent that interfaces the network adapter to the wire. The MAC component of the a dapter interfaces to the PHY component via the IEEE Media Independent Interface (MII). Some[...]

  • Page 126

    118 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Physical Layer Interface This structure allows a controller , or other manageme nt hardware, to query t he PHY for the st atus of the link or configure the PHY to one of many modes. The next sectio n discusses the MDI registers. 7.2 MDI Register Set The generic MDI r[...]

  • Page 127

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 119 Physical Layer Interface The individual registers are defined in th e following subsections using the followi ng conventions: R: Read W : W r ite RO: Read only SC: Self clearing Note: The default values listed for the 82555 regist ers al so apply to the register s i[...]

  • Page 128

    120 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Physical Layer Interface 7.2.2 St atus Register: Register 1 For maximum accuracy of link status, the Auto-Negat iation Complete bit (bit 5), shou ld be polled at a continuous i nterval of at least 300 mi lliseconds. After the Auto-N egotiation process has completed, [...]

  • Page 129

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 121 Physical Layer Interface 7.2.3 Identification Registers: Registers 2 and 3 The 32-bit ID register provides a mechan ism for software to dete rmine which PHY is present. The contents of these registers differ depending on the PHY . There are three values encoded in r[...]

  • Page 130

    122 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Physical Layer Interface 7.2.4 Auto-Negotiation Advertise ment Register: Register 4 This register contains the advertis ement ability of the PHY . It is used by software to determine the highest common denominator technology after t he auto-negotiation process h as f[...]

  • Page 131

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 123 Physical Layer Interface NOTE: The Auto-Negotiation Link Partner Ability Registe r is read only . 7.2.6 Auto-Negotiation Exp ansion Register: Registe r 6 Register 6 contains supplemental informa tion used b y the auto-negoti ation process. 12:1 1 T echnology Ability[...]

  • Page 132

    124 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Physical Layer Interface 7.3 Intel 82555 Sp ecific Registers Note: The Intel MAC/PHY silicon devices (82558, 82559, 82550, and 8255 1) use the 82555 as the base for their integrated PHY units. Therefore, the inform ation contained in this section and the following su[...]

  • Page 133

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 125 Physical Layer Interface 7.3.2 Special Control Register: Register 17 Bit Name R / W Description Default 15 Scrambler Bypass RW 1 = By pass Scrambler 0 = Normal operation 0 14 4/5 Bypass RW 1 = Bypass 4-bit to 5-bit 0 = Normal operation 0 13 Force Transmit H Pattern [...]

  • Page 134

    126 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Physical Layer Interface 7.3.3 Clock Synthesis T est and Control Register: Register 18 7.3.4 100BASE-TX Receive False Carrier Counter: Register 19 7.3.5 100Base-TX Receive Disc onnect Counter: Register 20 Bit Name R / W Description Default 15 Clock Timing RW SC Clock[...]

  • Page 135

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 127 Physical Layer Interface 7.3.6 100BASE-TX Receive Error Frame Counter: Register 21 7.3.7 Receive Symbol Error Counter: Register 22 7.3.8 100BASE-TX Receive EOF Error Counter: Register 23 7.3.9 10BASE-T Receive EOF Error Counter: Register 24 7.3.10 10BASE-T T ransmit[...]

  • Page 136

    128 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Physical Layer Interface 7.3.1 1 Equalizer Control and St atus Register: Register 26 This register is used to control and monito r the operation of the 825 5x PHY module equalizer (excluding the 82557 since it does not have an integrated PHY unit). Bits 15:13 specify[...]

  • Page 137

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 129 Physical Layer Interface 7.3.12 Special Control Register: Register 27 01 1 Write to ASD configuration register 2 [9] Breakdown ASD counters. [8] Selects signal detections or transitions. [7:6] Slow mode adaptation time configure: 00 = 67 ms (default) 01 = 0.5 ms 10 [...]

  • Page 138

    130 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Physical Layer Interface 7.4 Auto-Negotiation Functionality The PHY units of the 8255x devices (excluding the 8255 7) all support auto-negotiation (N-W ay). Auto-negotiation is an automatic confi guration scheme designed to manage int eroperability in heterogeneous L[...]

  • Page 139

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 131 Physical Layer Interface T o detect the correct technology , the two register fields are AND ed together to obtain the highest common denom inator . This value is used t o map into a priority reso lution table used b y the MAC driver to select the ap propriate techn[...]

  • Page 140

    132 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Physical Layer Interface 7.5 V endor-Specific PHY Programming The Intel ® PRO/100B adapters are designed to support Intel and third-party PHY s using TX and T4 PHYs. The PHYs will be capab le of auto-nego tiation, but cer tain vendor specific pro gramming hooks may [...]

  • Page 141

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 133 Physical Layer Interface 7.5.2.1 PHY St and Alone (PHYSA) Mode Only the 82558 su pports a special mode where it s PHY unit can be used w ith an external contro ller through an MII-like interface. This mode is not fully MII compliant and should be used with care. The[...]

  • Page 142

    134 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Physical Layer Interface[...]

  • Page 143

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 135 Programming Recommendations 8 8.1 Adapter Initialization The initialization code can be broadly split in the following code m odules: • 8255x initialization • PHY detection and initializati on • NOS specific initialization The sample source code provides speci[...]

  • Page 144

    136 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Programming Recommendations 8.1.3 NOS Specific Initialization Software should be written so that NOS specific in terface routines call lower level driver routines. This will enable code re-use. 8.2 T ransmit Processing Frame transmission is th e most critical part of[...]

  • Page 145

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 137 Programming Recommendations 8.4 Interrupt Processing The 8255x supports l atched level triggered interrupts. Interrupts can be shared in the system if the software and NOS support this mechan ism. The SCB Command and Status words provide the necessary interface for [...]

  • Page 146

    138 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Programming Recommendations[...]

  • Page 147

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 139 W a ke-up Functionality A Note: This appendix applies only to the 82558 and subsequ ent devices. W ak e-up functionality was first intro duced with the 82558 A-step. This component is capable of being brought out of a power mana ged s tated by programming it to wake[...]

  • Page 148

    140 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Wake- up Functionality A.2 Low Power Modes The device wake-up capabilities require internal PHY and CSMA block s to be fully active. When the controller is set into the D2 o r D3 power st ate and wake up is disabled, the internal PHY and CSMA units are set into low p[...]

  • Page 149

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 141 Wake-u p Functionality A.3.1 Auxiliary Power Support The LIST A T signal should be 0 after a hardware reset. For WOL mode, the default value aft er power up reset (AL TRS T# is asserted) of the PME enable and status bits are: PME_Enable = 1 (wake up is enabled) PME_[...]

  • Page 150

    142 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Wake- up Functionality A.4.1 Magic Packet* The 82558 and later generation con trollers (except the 82559ER) are capable of generating a wake- up event upon reception of a Magic Packet. This feature is enabled by setting a bit in the Configuration comm and. A.4.2 Addr[...]

  • Page 151

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 143 Wake-u p Functionality The controller only filters the shaded fields in the frame format ab ove. Only the two low bytes of the IP address are compared. The controller does not check for VLAN type (any frame with type different than 0806 is trea ted as a VLAN frame i[...]

  • Page 152

    144 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Wake- up Functionality A.5 Link St atus Event The controller may be configured to wake up th e system on link disconn ect and conn ect events. The link status wake-up enable bit was added to the configuration com mand for the 82558 and later generation devices. If th[...]

  • Page 153

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 145 Wake-u p Functionality • Multiple IP address recognition A.6.1 Flexible Filtering T erminology Filter . A filter is a set of a signature and segments generated for a specific frame format. Each filter defines one frame that causes the controlle r to wake the syste[...]

  • Page 154

    146 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Wake- up Functionality A.6.3 W ake-up Packet S torage The device uses its internal registers for packet storage during power down mode. Only the first 124 bytes of a frame may be filtered and stored by the device. The residual section of the packet beyond the first 1[...]

  • Page 155

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 147 Wake-u p Functionality — Pre-Defined Filters. The 82559 contains pre-defin ed filters for both Ethern et T ype II and 802.2 snap. The 82559 distinguishes between these two types accord ing to the MAC T ype/Length field. The 82559 also handles VLAN taggin g per pac[...]

  • Page 156

    148 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Wake- up Functionality There are two groups of pre-defined filters: — The NBH, ARP and IA-T ype pre-defined filters each use the word match field. — The IA-Match and TCO pre- defined filters do not use the word match field. A single programming word may contain b[...]

  • Page 157

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 149 Wake-u p Functionality • Flexible Filter Filter type: Filter type CRC word Filter mask (up to 4 Dwords: DW0, DW1, DW2, DW3) 31 30 29 28 27 26 25 24 EL FIX=0 MLEN Reserved (0) EL The end of list bit indicates if this filter is the last active one. FIX Clearing this[...]

  • Page 158

    150 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Wake- up Functionality A.7.2 CRC Word calculation of a Flexible Filter A.7.3 Port Dump W ake Up Packet The 82559 Port commands are summarized in T able 6 7 , which also includes the new Dump W ake- up Packet command: Following the Dump W ake-up command, the 82559 wri[...]

  • Page 159

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 151 Wake-u p Functionality The sequence of events after a Dump W ake -up command that the 82559 performs are: 1. W rite the byte count fiel d at Dword 1. This fi eld contains the actual num ber of bytes posted in the host memory . A value of FFh indicates that the W ake[...]

  • Page 160

    152 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Wake- up Functionality CLK is inactive and 10 mA if it i s activ e. The deep power down state due to PME disable is enabled in the EEPROM. A.7.4.2 Power Down with W ake-up Cap abilities The 82559 provides wake-up capabilities at all power states. At the D0 state, the[...]

  • Page 161

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 153 Wake-u p Functionality 6. The device statistic counters ar e corrupted duri ng power down st ate. Therefore, the driver should clear the statistic counters by first issuin g load dump counters address and then a dump and reset statistic counters. 7. If the 82559 was[...]

  • Page 162

    154 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual Wake- up Functionality[...]

  • Page 163

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 155 82550 and 82551QM Specific Information B This appendix appl ies to the Intel ® 82 550 and 82551QM devices. B.1 IPCB The IP command block (IPCB) is new and used to activate the ne w offloading features of the 82550 and 82551. The value of the comm and field for IPCB[...]

  • Page 164

    156 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual 82550 and 82551QM Sp ecific Information The location and definition of the IPCB fiel ds are summarized in the following table. T a ble 72. IPCB Fields Field Name Byte Bit (s) Function D escription T otal TCP/UDP Payload 1Fh: 1Eh 15:0 Parameter , S tatus This field sp[...]

  • Page 165

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 157 82550 and 82 551QM Specific Informatio n Note: Using software parsing is only allowed with le gal TCP/IP or UDP/IP packets. W hen software parsing is used, IP and TCP offsets in the IPCB mu st poin t to the appropria te headers and the total TCP/UDP payload should b[...]

  • Page 166

    158 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual 82550 and 82551QM Sp ecific Information modes of operation. For instance, the driver must guarantee prop er values for the Maxi mum TCP Payload in Large Send mode and VLAN length inclusion. Note: IP fragmentation is not supported by the 82550. Therefore, the driver s[...]

  • Page 167

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 159 82550 and 82 551QM Specific Informatio n B.2.2 IPCB Field Assignment The mode bits in the IP Activation field contro l the checksum operation of the transmit command. • IPv4 Checksum (1bit). When this bit is set to 1, the device is forced to perform checksum opera[...]

  • Page 168

    160 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual 82550 and 82551QM Sp ecific Information first byte of the TCP or UDP header . The cont roller reads this parameter when Hardware Parsing is clear and TC P/UDP checksum is set. Note: If TCP/UDP headset offset is specified, then the IP header of fset must also be speci[...]

  • Page 169

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 161 82550 and 82 551QM Specific Informatio n Note: The partial checksum requi red by the 8255 0 is not the partial checksum passed by the Microsoft* IP stack per Microsoft o ffloading specification, v0.106. For TCP/UDP checksum computation, the 8 2550 requir es that the[...]

  • Page 170

    162 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual 82550 and 82551QM Sp ecific Information Note: T o use Large Send, the 82550 should be configured to use dynamic T ransmit Buffer Descriptors (TBDs). The driver should ensure transmit buffers associated with the Large Send IPCB contain enough bytes (headers size and t[...]

  • Page 171

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 163 82550 and 82 551QM Specific Informatio n Note: If the IPv4 checksum and TCP/UDP checksu m are clear (checksum of fload is not requested), frames will be transmit te d without computing and replacin g the checksum fields conten t. Therefore, the driver should set bot[...]

  • Page 172

    164 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual 82550 and 82551QM Sp ecific Information — Fragment of fset equals 0. This is expected but not checked by hardware. — IP options are not altered by ha rdware if they are present. — IP header checksum is calculated by the check sum hardware if the IP checksum bit[...]

  • Page 173

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 165 82550 and 82 551QM Specific Informatio n When the headers are finished, they are subject to checksum for processing. The rest of the transmission process is similar to transmissio n of a small send. This process repeats itsel f until the last frame is about to be tr[...]

  • Page 174

    166 10/100 Mbps Ethernet Con troller Family Open Source Software De veloper Manual 82550 and 82551QM Sp ecific Information way , it may read an extra TBD (o r 8 b ytes) after the last v alid TB D. The driver is responsible fo r allocating enough memory for the TBD array . Otherwis e, it needs to ensure that an extra 8 byte read access from the PCI [...]

  • Page 175

    10/100 Mbps Ether net Controller Family Open Source Softwar e Developer Manu al 167 82550 and 82 551QM Specific Informatio n B.4.1.1 Frame T yp es • Ethernet v2 . If the Ethernet v2 type field equals 0800h, the first byte of IP header is expected right after the optiona l VLAN field. • SNAP . The 82550 and 82551 ski p the DSAP and SSAP fields. [...]