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Intel 31154 manual

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Table of contents for the manual

  • Page 1

    Order Number : 278944- 001 Intel ® 31 154 13 3 MH z PCI Bridge Design Guide Desig n Guide April 2 004[...]

  • Page 2

    2 Inte l ® 3 1154 133 MHz PCI Bridge Desi gn Guide INFORMA TION IN THIS DOCUME NT IS PROV IDED IN CONNECTION WITH INT EL ® PRODUCTS. E XCEP T A S PROVIDED I N INTEL ’S TERMS AND CONDITIONS OF SALE FO R S UCH PRODUCTS, INTEL ASSUMES NO LIABIL ITY WHA TS OE VER, AND INTEL DISCLAIMS ANY E XPRESS OR IMPLIED WARRANTY RELA TING TO SALE AND/OR USE OF [...]

  • Page 3

    Inte l ® 31154 13 3 MHz PCI Br idge Desi gn Guide 3 Contents Content s 1 About T his Documen t ................. .. ..... .. ..... ..... ....... .. ..... ..... .. ..... ....... .. ..... ..... .. ....... ..... .. ..... ..... .. ..... .... 7 1.1 Te rmi n o lo g y and Def initi o n s ... ..... .. ..... .. ..... ..... .. ..... .. ..... ..... .. ..... [...]

  • Page 4

    4 Inte l ® 3 1154 133 MHz PCI Bridge Desi gn Guide Contents 7.2.4 .2 PIC MG 1.2 Syste m Overvi ew .... .... ..... ..... ....... ..... .... ..... ....... ..... ..... .... .... 52 8 Power Consi derat ions ....... ..... ..... .... ..... ..... ..... ....... .... ..... ..... ..... .... ..... ....... ..... ..... .... ..... ..... .... .. .. ... .. 57 8.1[...]

  • Page 5

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide 5 Contents 9 Secondary Bus F requency I nitialization ............... ............ ....... ................. ......... ............ .............. 33 10 PCI- X Init iali zatio n Pat tern ..... .... ..... ..... ..... .... ....... ..... ..... ..... .... ..... ..... ....... ..... .... ..... ..... ....[...]

  • Page 6

    6 Inte l ® 3 1154 133 MHz PCI Bridge Desi gn Guide Contents Revision History Date Revision Description Ap ril 2004 001 Ini tial rel ea se[...]

  • Page 7

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 7 Ab ou t Thi s Doc um e nt About This Document 1 This docu ment prov ide s layout infor m ati on and guideline s for design ing plat form or add-in board appli cati ons wi th th e Intel ® 31 154 133 MHz PCI Bridg e. This docu ment is int ended to be used as a guid eline only . Intel [...]

  • Page 8

    8 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide About This Do cumen t § § Ag gres sor An ag gre ssor net work is a net work th at tra nsmit s a coup led si gn al to an other net work . Vi ct im A n etw or k t hat rece iv es a co up led cr os s-t a lk signa l fro m a not her n etw ork is a c al led t he vi cti m netw ork. Network A[...]

  • Page 9

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 9 Int roduc tio n Introduction 2 2.1 Prod uct Overview The Inte l ® 31 154 133 MHz PCI Bridge (cal led hereaft er the “31 154”) is a PCI compone nt that functi ons as a high ly con current , low-lat en c y trans pa rent bridg e betwee n two PC I buse s . T he 31 154 can operate as[...]

  • Page 10

    10 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide In trod uct ion The 31 154 ha s a dditio nal hardwa re s upport for Com pactPCI* Hot Swap a nd Re dundant System Sl ot via queue flush, arbite r l oc k, and clock out put tristatin g. The 31 154 s upports any combina tion of 32-bit and 64-b it data trans fers o n its primary a nd se c[...]

  • Page 11

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 11 Int roduc tio n 2.3 Related External S peci fications • PCI L oca l Bus Spe ci fica tio n , Revis ion 2.3 • PCI-t o-PC I Bridge Arc hitec tu re Speci ficat ion , Rev ision 1.1 • PCI Bus Power Manag ement Inte r face Speci ficat ion , Rev is ion 1.1 • Compact PCI Hot Swap Spe[...]

  • Page 12

    12 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide In trod uct ion THIS PAG E I NTENTI ONAL LY LEFT BL ANK[...]

  • Page 13

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 13 Packa ge Informa tion Pack age Inform ation 3 The Inte l ® 31 154 133 MHz PCI Bridge is of fe r ed in a 421-lead PBGA packag e. The mechanic a l dimens ions for th is package are pr ovided in Figu re 2 on page 14 . Fig ure 3 on page 15 and Figure 4 on page 16 show the 421-lead P BG[...]

  • Page 14

    14 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Packag e Informatio n Figu re 2. Inte l ® 3 1 1 54 1 33 M Hz PCI Bridge Package B1290-01 BOTTOM VIEW SIDE VIEW TOP VIEW 1.27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B C D E F G H J K L M N P R AA Y W U T C Ø B A 0.30 S S S Ø 1.53 REF 1.27 1.27 1.53 REF PIN #1 CORNER 0.90 0.60 23 22 2[...]

  • Page 15

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 15 Packa ge Informa tion Fi gur e 3 . In tel ® 31 154 133 MH z PCI Bridge Ball Map—T op V iew, Left S ide B2240-01 A 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 B C D E F G H J K L M N P R T U V W Y AA AB AC A 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 B C D E F[...]

  • Page 16

    16 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Packag e Informatio n Figu re 4. Inte l ® 31 1 54 133 M Hz PCI Bri dge Ball Map—T op Vi ew, Right Sid e B2241-01 A 13 14 15 16 17 18 19 20 21 22 23 13 14 15 16 17 18 19 20 21 22 23 B C D E F G H J K L M N P R T U V W Y AA AB AC VSS VSS VCCP VSS P_ VCCA VCCP VSS TDI VSS VSS TCK VSS [...]

  • Page 17

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 17 Packa ge Informa tion 3.1 T ot al Sign al Count § § Ta b l e 4 . To t a l S i g n a l C o u n t Inter face Si gna ls PCI bus in terf ace 1 12 PC I 64-bi t ext ensio ns 78 Cl ock an d reset 20 JT A G 12 Serial ROM interface 4 CompactPCI* Hot Swap 6 Hardware stra p 5 Mi sce lla neou[...]

  • Page 18

    18 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Packag e Informatio n THIS PAG E I NTENTI ONAL LY LEFT BL ANK[...]

  • Page 19

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 19 T ermin atio ns T erminations 4 This cha pter d etails all the r ecommen ded Intel ® 31 154 133 MHz P CI Br idge terminati ons requi red for the dif fere nt operat ing m odes . The chapt er provide s th e recommende d pull -up a nd pull- down te r mination s for a 31 154 la yout. T[...]

  • Page 20

    20 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide T ermin atio ns P_GN T# Co nnect to GN T# of th e pri mar y PCI bu s. P_ ID SEL # Con nec t to o ne o f the AD l ines of th e pri mary PCI bus o r to th e ID SEL# si gnal o f th e PCI edge conn e cto r ( f or add-i n c ar d ap pli c ation s ). Re fer to Sect ion 5 .3 , “I D SEL Li n[...]

  • Page 21

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 21 T ermin atio ns S_AD[3 1:17] Thes e si gn al s can b e us ed a s IDS EL l in es and are con nec ted to IDS EL of the s econd ary PC I b us th ro ugh a n ex ter na l se rie s coup li ng res ist or (a re si st or of 2 K Ω is use d on the cus t ome r re fer en ce boar d) . PCI Cloc k[...]

  • Page 22

    22 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide T ermin atio ns S_GCLKOEN Wh en th e in tern al c lo ck o f t he 31 1 5 4 is us ed, pul l high to V CC 33 thr oug h an ext ern al 8. 2 K Ω r e sist or. Whe n an extern al c lo ck sour ce is us ed, t ie t o GND thr oug h a 330 Ω ex terna l res istor. All s eco ndary cloc k ou tput [...]

  • Page 23

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 23 T ermin atio ns HS _FRE Q[1: 0] For H ot S wap : • D ep endi ng on P r imar y P C I Bu s fr equ en cy 00 = PCI Mo de , 33 or 66 M H z (de fault ) 01 = PCI- X 66 MHz 10 = PCI -X 100 MHz 1 1 = P CI- X 133 MHz When not us in g Hot S w ap: • Tie l o w to GND. Onl y vali d w hen HS _[...]

  • Page 24

    24 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide T ermin atio ns OP AQUE _E N T o en able Op aqu e Memor y Base /Lim it R eg ister s to e st a bl ish a pri vat e memo ry sp ac e fo r sec on da ry bu s us ag e : • P ull h ig h to 3. 3 V thr oug h an exte rn al 8. 2 K Ω resisto r . T o di sabl e Opaq ue Mem ory Bas e/Limi t Re gis[...]

  • Page 25

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 25 T ermin atio ns JT A G TCK Pu ll lo w wh en n ot us ed. TDI When not u sed , pul l u p to 3. 3 V thr ough an ext ern al 8. 2 K Ω re sist or . TD O NC wh en no t u s ed TRST # Whe n n ot use d, pull lo w to G ND t hro ug h an ex te rnal 1 K Ω res i s t o r. TMS When no t used , p[...]

  • Page 26

    26 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide T ermin atio ns RS TV0 Tie to G ND thr oug h a 0 Ω extern al resistor . RSRV1/CRSTEN T ie to GND t hrough a 0 Ω ext ernal resi stor . S_ M6 6E N S_ M66E N is me an in gful onl y wh en S_ PCI XCA P is c on nected to GND (t hat is, when t h e se cond ar y PCI bu s is in lega c y PC [...]

  • Page 27

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 27 T ermin atio ns § § NT_MA SK# • Whe n forc ed reti rem ent o f t he 31 15 4 int ernal re qu es t queue s an d dat a buf fe r is not desir ed in t he ap pli cati on , t hi s pin mu st be pul led u p to 3. 3 V th r o ugh a n 8.2 K Ω resistor . • Whe n forc ed reti rem ent o f [...]

  • Page 28

    28 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide T ermin atio ns THIS PAG E I NTENTI ONAL LY LEFT BL ANK[...]

  • Page 29

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 29 PCI/PCI -X Interface PCI/PCI- X Interfa ce 5 This cha pter provi de s gui de lines for de signi ng wit h the Intel ® 31 154 133 MHz PCI Bridge PCI/PCI-X bus interface in your a pplication . 5.1 PCI/PCI-X V olt age Levels The Inte l ® 31 154 133 MHz PCI Bridge suppor ts the 5 V PCI[...]

  • Page 30

    30 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI /PC I -X Interfa c e 5.3 IDSEL L ines The IDSE L li nes act as chi p se lect s dur ing th e co n figur atio n cy cles . Co n figur atio n cy cles al l ow r ead and write access to on e of th e device c onfig uratio n space reg ister s. As in PCI, the IDSEL l ines can be ma pped t [...]

  • Page 31

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 31 PCI/PCI -X Interface 5.3. 3 Sec onda r y IDS EL Masking The 31 154 suppor ts pr iva te devi ce s th rough the use of IDSEL maski ng. When the IDSEL_MASK pin is sa mpl ed a s 1b on the traili ng edge of P_RST#, the d efa ult valu e for the Se con dary IDSEL Selec t Regis ter (SISR ) [...]

  • Page 32

    32 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI /PC I -X Interfa c e 5. 6 PCI-X Initi alizat i on Clocki ng M od e s Both of the PCI b us inte rfaces can oper ate at a variety of freque ncies, and in ei the r convent ion a l PCI mode, or in PCI-X mo de. Each interfa ce esta blis hes the bus mode and freq uency whe n coming out [...]

  • Page 33

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 33 PCI/PCI -X Interface T a ble 8. P CI-X Clocki ng Modes PCI -X Mod e PC I Mod e PC IXCAP (pin on P CI conn ec tor) P_ M6 6E N Not capable 33 M Hz GND GND Not ca pable 66 MHz GN D Not conn ected PC I-X/ 6 6 MH z 33 MHz Pull down GND PCI- X/66 MHz 6 6 MHz Pull down Not co nnec ted PCI [...]

  • Page 34

    34 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI /PC I -X Interfa c e Ta b l e 1 0 des cri bes the bus mode and freq uency ini ti alizati on pa t te rn that the 31 154 signa ls on its se condary bus whe n com ing out of S_RS T#, a fter h a ving evalu ated the above infor m ation. 5. 6.3 P ri mar y-to -Sec ondar y Freq uenc y Lim[...]

  • Page 35

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 35 Ro u t in g G u id e l in es Routing Guidel ines 6 This ch apt er provide s some bas ic rout ing guide lin es for la yout and design of a printe d circu it bo ard (PCB) usi ng the In tel ® 31 154 133 MHz PCI Bri dge . The high-s pee d cl ocking require d when des igning with t he 3[...]

  • Page 36

    36 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Routi ng Guidel ines 6.1 Cro sstal k Cros stal k is caus ed by c apac itive and induct ive c oupl ing between s ign als. Cr os stalk i s compose d of both bac kward a nd for ward cros stalk co mponents . Bac kward cro sstal k crea tes an indu ced s ignal on a victim net work that prop[...]

  • Page 37

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 37 Ro u t in g G u id e l in es 6.2 EMI Considerations It is hi ghly recommend ed tha t you follow good EMI desig n pr ac tice s when des ign ing with the 31 154: • T o mini mize EMI on your PCB, a us eful techni que is not to extend th e power planes to the edge of th e board. • A[...]

  • Page 38

    38 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Routi ng Guidel ines 6. 3 Power Dis t ri but ion an d Deco upling Ensure that t here is ample decoupli ng t o groun d for t he power pl anes , to minimiz e the e ffec ts of t he switc hing cur rents. Inadequa te hi gh-f requency decoupl ing results in in termittent and unre liabl e be[...]

  • Page 39

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 39 Ro u t in g G u id e l in es 6.4 T race Impedance The PCI-X Adden dum to the PCI Local Bus Spe cific at ion , Revi sion 1.0b, reco m mends that a l l sign al l ayers ha ve a c ontroll ed impe da nce of 57 Ω ±10% for add-in c ard appl ic ations . The chara ct eristi c imped anc e [...]

  • Page 40

    40 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Routi ng Guidel ines THIS PAG E I NTENTI ONAL LY LEFT BL ANK[...]

  • Page 41

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 41 PC I -X Lay out Gu ide l in es PCI-X Layout Gui delines 7 For acce pta ble signa l integr ity with bus speed s up to 133 MHz, it is impo rta nt for the PCB des ign layou t to ha v e con trolle d imp eda nce. The list bel ow provid e s gene ral guideli nes for rout ing your P CI bu s[...]

  • Page 42

    42 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines 7.1 PCI Clock Layo ut Guidelines The PCI-X Adde ndum to th e PCI Local Bus Speci ficat ion , Re visio n 1.0a , allows a maxi mum of 0.5 ns clock skew ti ming for each of the P C I-X fr equ encies : 66 MHz , 100 MHz, and 13 3 MHz. • T otal le ngt h of P_CLK [...]

  • Page 43

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 43 PC I -X Lay out Gu ide l in es Figure 8. P CI Clock Distribution and Matching Requiremen ts Device 8 Device 7 Device 6 Device 5 Device 4 Device 3 Device 2 Device 1 Intel 31154 133 MHz PCI Bridge Notes:[...]

  • Page 44

    44 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines 7. 2 PCI-X T opol ogy La y out Guide li nes The PCI-X Adde ndum to th e PCI Local Bus Speci ficat ion , Re visio n 1.0a , recommends the f ollowing guidelin e s f or the num ber o f loa ds for your PCI -X designs ( Ta b l e 1 3 ). Any devia tion f r om th es [...]

  • Page 45

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 45 PC I -X Lay out Gu ide l in es 7.2 .1 Sing le S l ot at 13 3 MHz Figure 9 shows o ne o f the c hip s et P CI AD li nes conn ecte d thr ough the W1 an d W12 line segme nts to a si ngl e -slo t connec tor through t he W13 li ne segment to the 31 154. This AD line is also used a s an I[...]

  • Page 46

    46 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines 7. 2.1.1 Inte l ® 31 154 13 3 MHz PC I Bridg e Embedded Appl ication at 133 MHz Fi gure 10 shows the 31 154 a pplic ation in a stand-a l one embedded appli cation. In t his appl ication the 31 154 is shown driving a sin gle PCI devic e. Ta b l e 1 5 shows th[...]

  • Page 47

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 47 PC I -X Lay out Gu ide l in es 7. 2.2 Du al- Slot at 1 00 MH z Figure 1 1 shows one of t he secon dary bridg e PCI AD line s branch ing i nto two se gments with e ach going thr ough slot connect ors to a buffe r on an add-i n ca rd. Ta b l e 1 6 shows the correspondin g wir ing leng[...]

  • Page 48

    48 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines 7. 2.2.1 Em bedded In tel ® 31 154 133 MHz PCI B ridge Appl ication at 100 MHz Fi gure 12 shows the PCI -X layo ut for a embe dded 13 3 MHz design . In this appli cation the 3 115 4 is drivi ng thre e loa ds. Ta b l e 1 7 shows the correspon ding wiring leng[...]

  • Page 49

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 49 PC I -X Lay out Gu ide l in es 7. 2.3 Quad -S lo ts at 66 MHz Figure 13 shows one of the bridge s eco ndar y AD lines bra nchi ng to four seg ments with each seg ment conne cting to a slot co nne ctor to a bu ffer on an add-in c ard. T he first segm ent re presenti ng an upper addre[...]

  • Page 50

    50 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines W15 0.6 0.6 – – inch es W1 6 1.12 5 1. 12 5 – – in che s W21 0.8 1 .2 0.8 1.2 in che s W22 0.1 0 .5 0.1 0.5 in che s W23 0.75 1.5 1. 75 2.75 i nches W32 0.1 0 .5 0.1 0.5 in che s W33 0.75 1.5 1. 75 2.75 i nches W42 0.1 0 .5 0.1 0.5 in che s W43 0.75 1[...]

  • Page 51

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 51 PC I -X Lay out Gu ide l in es 7.2. 3.1 Emb edded Int el ® 31 154 133 MHz PCI Br idge Ap plication a t 66 MHz Figure 14 shows an 311 54 in a s ta nd-alone embedd e d appli c ati on. In this appl icati on the 31 154 is shown dri ving four loa ds. Addition a l loads mi ght be possibl[...]

  • Page 52

    52 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines 7. 2.4 PCI - X at 33 MH z The 31 154 s upp orts running in an eight -slot PIC MG 1.2 style pass ive backpl ane environm ent at 33 MHz. T o verif y this , sim ulat ions were run b a se d on the tr a ce imped ance of 57 Ω ± 10%. 7. 2.4.1 Em bedded P CI-X Sp [...]

  • Page 53

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 53 PC I -X Lay out Gu ide l in es Figure 15 shows an examp le of this syst em with dua l 64-bit bus es wit h four expans ion sl ots on each bus. T he b a ckp lan e exa mp le s ho ws th e S HB in a n I SA ch as sis. T he S H B s lot is in th e cen te r of the boa rd. Fi gure 16 sho ws t[...]

  • Page 54

    54 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines Figure 16. PCI-X D ata Bus PICMG 1. 2 Style Back plane T ab le 20. Wi ring Lengths for PICMG 1.2 Backplan e Segm ent AD Bu s Units Min im um Le ngt h Ma ximum L ength W1 0.75 2.75 in ches W2 0.75 2.75 in ches W3 0.75 2.75 in ches W4 0.75 2.75 in ches W5 0.75 [...]

  • Page 55

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 55 PC I -X Lay out Gu ide l in es § § Figure 17. P CI-X Clock PICM G 1.2 S tyl e Backp lane T a ble 21. PCI-X Clock Wiring Lengths for PICMG Backpl ane Se gme nt Clock Point to Po int Unit s Minim um L eng th Maximu m Len gth S1 0 0.3 i nc he s S2 0. 75 2. 75 inc hes WN 0.75 2.75 inc[...]

  • Page 56

    56 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines THIS PAG E I NTENTI ONAL LY LEFT BL ANK[...]

  • Page 57

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 57 Pow er Consid eration s Power Considerations 8 8.1 Anal og Power Pin s The an alog v o lt age pins S_V CCA an d P _VCCA re quire a lo w - pas s filt er . Thi s is imp l ement ed by conne cting th e P _ VCCA and S _VCCA pin s to a 10 Ω series resi stor and 0.01 µ F and 4.7 µ F (l[...]

  • Page 58

    58 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Powe r Co nsi dera tions 8.2 Power S equencing When either P _VIO or S_VIO is connect ed to a po wer suppl y othe r than V CCP , you m ust perform on e of the followi ng steps (l isted in order fr om most favo rably recommende d to lea st favorab ly r ecommended) : 1. Ensure that the [...]

  • Page 59

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 59 Customer Referen ce Board Cust omer Re f ere nce Boa rd 9 This cha pte r provides inf orm ati on on the custome r refe rence board base d on the Int el ® 31 154 133 MHz PCI Bridge—th e Inte l ® IQ31 154 Cus tomer Referen ce Board (CRB). Figu re 21 shows the blo c k diagra m for [...]

  • Page 60

    60 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Customer Referen ce Boar d The I Q 3 1154 CR B is im pl em en t ed on ei gh t lay e r s. Th es e lay e r s are de ta il e d in Ta b l e 2 2 . T h is exa mple is provi ded as a re ference; each individ ual 3 115 4 applic ation m ay vary . FR- 4, 0. 062 in. ± 0. 008 , 1.0 oz . coppe r [...]

  • Page 61

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 61 Debu g Connecto rs and Logic Analyzer Connec tivity Debug Connectors an d Logic Analyzer Connectivity 10 10.1 Probi ng PCI -X Si gna l s T o ease the probi ng a n d deb ugging of the PCI-X signals , you are r ecommende d to pa ssive ly probe the PCI-X bus si gnals with a log ic anal[...]

  • Page 62

    62 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Debug Con nectors and Log ic Analy zer Connectivity T ab le 23. Logic An alyzer Po d 1 Mict or- 38 #1 Pin Num be r Odd Pod Logic Ana lyze r Channe l Num ber PC I- X Name 6 CLKC/16 CLK 8 15 C/ BE4 10 14 C/ BE5 12 13 C/ BE6 14 12 C/ BE7 16 1 1 ACK6 4 18 1 0 RE Q64 20 9 UNUSED 22 8 PM E [...]

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    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 63 Debu g Connecto rs and Logic Analyzer Connec tivity T a ble 24. Logic Analyzer Pod 2 Mict or - 38 #1 P in Nu mber O dd Pod Log ic A nal yz er Cha n n e l N umb er PCI- X Sign al N am e 5C L K / 1 6 F R A M E 7 1 5 DEVS EL 9 14 TRDY 1 1 13 C/BE2 13 12 C/BE3 15 1 1 IDSEL 17 10 R EQ 19[...]

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    64 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Debug Con nectors and Log ic Analy zer Connectivity T ab le 25. Logic An alyzer Po d 3 Mict or -38 #2 Pin Num be r Odd Pod Log ic Ana lyz e r Channe l N umber P CI-X Sign al Nam e 6 CLK/16 IRDY 81 5 A D 1 5 10 1 4 AD 14 12 1 3 AD 13 14 1 2 AD 12 16 1 1 AD 1 1 18 1 0 AD 10 20 9 AD 09 2[...]

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    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 65 Debu g Connecto rs and Logic Analyzer Connec tivity T a ble 26. Logic Analyzer Pod 4 Mict or - 38 #2 P in Nu mber O dd Pod Log ic A nal yz er Cha n n e l N umb er PCI- X Sign al N am e 5 CL K/16 UNUSED 71 5 A D 3 1 91 4 A D 3 0 11 1 3 A D 2 9 13 12 A D28 15 1 1 AD27 17 10 A D26 19 9[...]

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    66 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Debug Con nectors and Log ic Analy zer Connectivity T ab le 27. Logic An alyzer Po d 5 Mict or -38 #3 Pin Num be r Odd Pod Log ic Ana lyz e r Channe l N umber P CI-X Sign al Nam e 6C L K / 1 6 P A R 6 4 81 5 A D 4 7 10 1 4 AD 46 12 1 3 AD 45 14 1 2 AD 44 16 1 1 AD 43 18 1 0 AD 42 20 9[...]

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    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 67 Debu g Connecto rs and Logic Analyzer Connec tivity The recom mende d place ment of the Mictor con nector s is at either e nd of t he bus s egm en t. The Micto rs are pl a ced a t the end of a s tub tha t must be as s hort a s po ssible , and are then da isy- chained of f e i the r [...]

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    68 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Debug Con nectors and Log ic Analy zer Connectivity THIS PAG E I NTENTI ONAL LY LEFT BL ANK[...]

  • Page 69

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 69 The rmal Sol ution s Thermal Solutions 11 The Int el ® 31 154 133 MHz PCI Bri dge is p ackaged i n a 421 -lead PB GA pac kage. T he mechanic al dimens ions for th is package are pr ovided in Figu re 2, “Intel ® 31 154 133 MHz PCI Bridge Pa ck ag e ” on pa g e 14 . Ta b l e 2 9[...]

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    70 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide The rmal So lu tions THIS PAG E I NTENTI ONAL LY LEFT BL ANK[...]

  • Page 71

    Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 71 Referenc es Refe rences 12 12.1 Related Do cument s Ta b l e 3 0 list s sev era l books and spe ci ficat ion s th at a r e hel pful for design ing with the Inte l ® 31 154 133 MHz PCI Bri dge. Ta b l e 3 0 list s Intel ® document ation that i s helpfu l for de si gning with the In[...]

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    72 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide References THIS PAG E I NTENTI ONAL LY LEFT BL ANK[...]