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Intel 273246-002 manual

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Table of contents for the manual

  • Page 1

    Celeron™ Processor Development Kit Manual July 1999 Order N umber: 27 3246-00 2[...]

  • Page 2

    Celeron™ Proces sor Devel opment Ki t Man ual Informati on in this do cumen t is provided in connection with Intel products . No licens e, express or imp lied, by estoppel o r othe rwise, to any intellectua l property rights i s grante d by thi s docume nt. E xcept as pro vide d in Intel ’s T erms an d Condi tions of Sale fo r such p roducts , [...]

  • Page 3

    Celeron™ Proce ssor Developm ent Kit M anual iii Contents 1 About This Manual .................. ............. ............ ............. ............. ............. ................ 1-1 1.1 Content O verview .. ............. ............. ............ ............. ............. .................... ......... 1-1 1.2 Text Conv entions ..........[...]

  • Page 4

    iv Celeron™ Proces sor Devel opment Ki t Man ual 3.2.19 Post Code Debug ger ......... ............ ............. .................... ............. ...... 3-6 3.2.20 Clock Generation.. ...... ............. ...... ............. ....... ...... ............. ....... ...... 3-6 3.2.21 Interrupt Map . ............. ............. ................... ..[...]

  • Page 5

    Celeron™ Proce ssor Developm ent Kit M anual v 5.10.1 Console R edirect ion ....... ................... ............. ............. ............. ......... 5-9 5.10.2 CE-Ready W indows CE Loader ........ ............. ............. ............. ....... 5-10 5.10.3 Integrated B IOS Debug ger ......... ............. ............. ............. ...[...]

  • Page 6

    [...]

  • Page 7

    Celeron™ Proce ssor Developm ent Kit M anual 1-1 About This Manual 1 This manual tel ls yo u how t o set up and us e t he evaluat ion board and pr oces sor assembl y incl u ded in your Celeron ™ Processor Developmen t Kit. 1.1 Content Overview Chapter 1, “About This Manual” - This chapter contains a d escription of conventions used in this [...]

  • Page 8

    1-2 Celeron™ Proce ssor Deve lopment Ki t Manual About This Manua l 1.3 T echnical Support 1.3.1 Electronic Suppor t Systems Intel’ s site o n the World Wi de W eb (http ://www .intel.com /) prov id es up-to-date techn ical informat ion and p roduct support. This infor mation is availab le 24 hou rs per d ay , 7 days per week, providing technic[...]

  • Page 9

    Celeron™ Proce ssor Developm ent Kit M anual 1-3 About Thi s Manual 1.3.1.2 Intel Product Forums Intel provides technical expertise through electronic messaging. W ith publicly accessible forums, you have al l of the ben efits of email tech nical supp ort, with the add ed benefit of the o ption of viewing prev ious mes sages wr itten by other par[...]

  • Page 10

    1-4 Celeron™ Proce ssor Deve lopment Ki t Manual About This Manua l 1.5 R elated Docum ents T able 1 - 1. Related Documents Document Tit le Order Number Inte l ® Celeron™ Processor datasheet 243658 Inte l ® Celeron™ Processor Specification Update 243748 P6 Family of Processors Hardware Developer ’s Manual 244001 Intel Architecture Softwar[...]

  • Page 11

    Celeron™ Proce ssor Developm ent Kit M anual 2-1 Getting Started 2 This chapter identifies the Developm ent Kit’ s key components, features and specification s, and tells you ho w to set up th e bo ard for operation. 2.1 Overview The evaluation board co nsists of a baseboar d and a processor assembly . • The processor assembly contains an Int[...]

  • Page 12

    2-2 Celeron™ Proce ssor Deve lopment Ki t Manual Getting S tarted 2.1.2 Baseboard Features The baseboard has these features: • Flash system BIOS ROM — General Software system BIOS — In- circuit BIOS upg radab ility • T wo SDRAM DIMM connectors • 32-Mbyte SDRAM DIMM included — 4 Mbyte x64, 3.3 V , 66 MHz with a CAS latency o f 2 • Us[...]

  • Page 13

    Celeron™ Proce ssor Developm ent Kit M anual 2-3 Gett ing St arted 2.3 Software Key Featur es The software in t he kit was chosen to facilitate developmen t of real-time appl ications b ased on th e components used in th e evaluation bo ard. The softwar e tools included in you r kit are described in this section. Note: Software in the kit is prov[...]

  • Page 14

    2-4 Celeron™ Proce ssor Deve lopment Ki t Manual Getting S tarted 2.3.2 QNX Software Systems, Ltd. QNX Real Time Operating System for Intel Architecture. • Small memo ry fo otprint of the QNX operat ing system wit h microGUI • QNX microGUI is a full featured grap hical user interface (GUI) and windowing system • Photon Appli cat ion Bui l d[...]

  • Page 15

    Celeron™ Proce ssor Developm ent Kit M anual 2-5 Gett ing St arted 2.5 Setting up th e Evaluation Board Once you have gathered t he hardware desc ribed in the las t section, fo llow the steps below to set up your evaluation board. This manual assu mes you are familiar with basic con cepts involved with installing and configur ing hardware for a p[...]

  • Page 16

    2-6 Celeron™ Proce ssor Deve lopment Ki t Manual Getting S tarted 3. Make sure the board’ s jumpers are set to the following default location s. • J14 - Not ins talled • J15 - I nstalle d • J20 - Jump er pin s 2- 3 • J21 - Jump er pin s 2- 3 • J22 - Jump er pin s 2- 3 • J23 - Jump er pin s 2- 3 • J24 - Jump er pin s 1- 2 4. Mount [...]

  • Page 17

    Celeron™ Proce ssor Developm ent Kit M anual 2-7 Gett ing St arted — Y ou may have to make changes to the system BIOS to enable this hard disk. See Chapter 5, “BIOS Quick Reference” for mo re information . • Floppy drive: A floppy disk dri ve connected to the ev aluation board is the most d irect method for loadin g software. — Insert f[...]

  • Page 18

    [...]

  • Page 19

    Celeron™ Proce ssor Developm ent Kit M anual 3-1 Theory of Operation 3 3.1 Block Diagram Figure 3-1. Evaluation Board Block Dia gram Celeron™ Processor Sensor PIIX4E DRAM Bus ITP V oltage Regulator 72-Bit DIMM 72-Bit DIMM USB SMC FDC37B78X SuperI/O* PS/2 Mouse Floppy Drive ISA Bus Boot Flash Thermal PCI Connectors ISA Connectors Bus M aster I D[...]

  • Page 20

    3-2 Celeron™ Proce ssor Deve lopment Ki t Manual Theory of O peration 3.2 Sys tem Operatio n The Celeron™ pro cessor evaluation boar d is a full-f eatured system board and processor assembly . The processor assembly includes either a 366-MHz or a 433-MHz Celero n processor (based on the development kit pur chased) with 128 Kbytes of integrated [...]

  • Page 21

    Celeron™ Proce ssor Developm ent Kit M anual 3-3 Theory of O peration 3.2. 2.1 Syste m Bus I nter f ac e The 82443B X support s a maxim um of 4 Gbyt es of memor y address space fro m the proces sor perspectiv e. The lar gest address size is 32 bits. The 8244 3BX pro vides bus co ntro l signal s and address paths for transfers between the processo[...]

  • Page 22

    3-4 Celeron™ Proce ssor Deve lopment Ki t Manual Theory of O peration 3.2.4 82371EB PCI to ISA/ IDE Xcelerator ( PIIX4E) The 82443BX is design ed to sup port the PIIX4 E I/O br idge. The P IIX4E is a highly-int egrated multifunction a l co mponent that supp o rts the following: • PCI Revi sion 2. 1 compli ant PCI -to-ISA b ridge with su pport f[...]

  • Page 23

    Celeron™ Proce ssor Developm ent Kit M anual 3-5 Theory of O peration 3.2.10 IDE Support The evaluation boar d supports bo th a primary and secondary I DE interface via two 4 0-pin IDE connectors. The connector labeled I DE1 is the primary interface. IDE2 is the secondary interface. 3.2.1 1 Floppy Disk Support Floppy di sk sup port is prov ided b[...]

  • Page 24

    3-6 Celeron™ Proce ssor Deve lopment Ki t Manual Theory of O peration 3.2.19 Post Code Debugger The evaluat ion board has an on- board Post Code Debugger . Data from any program that does an I/O write to 0080H is l atched and d isplaye d on the two LEDs (U12 and U1 3). During BIOS start up, codes are posted to these LEDs to indicate what the BIOS[...]

  • Page 25

    Celeron™ Proce ssor Developm ent Kit M anual 3-7 Theory of O peration 3.2.22 Memory Map T abl e 3-2. Memory Map Address Range (Hex) Size Description 100000-8000000 127.25M Extended Memory E0000-FFFFF 128 K BIOS C8000-DFFFF Available expansion BIOS area (Flash disk mem ory window) A0000-C7FF F Off-board v ideo memory and BI OS 9FC00-9FFFF 1K Exten[...]

  • Page 26

    [...]

  • Page 27

    Celeron™ Proce ssor Developm ent Kit M anual 4-1 Hardware Reference 4 This section pro vides reference informatio n on the syst em desig n. Included in this s ection is connector pinout informati on, jump er settin gs, and other s ystem des ign in formatio n. 4.1 Processor Assembly The processo r ass emb ly cont ains t he Cele r on™ proces s or[...]

  • Page 28

    4-2 Celeron™ Proce ssor Deve lopment Ki t Manual Hardware Reference 4.3 ISA and PCI Expansion Slots The evaluation platform has three PCI expansion slots and two ISA slots. 4.4 PCI Device Map ping On the evaluation platform the PCI devices are mapp ed to PCI dev ice numbers b y connecting an address line to the IDSEL signal of each PCI device. T [...]

  • Page 29

    Celeron™ Proce ssor Developm ent Kit M anual 4-3 Hardware R eference 4.5 Con nect or P ino uts 4.5.1 A TX Power C onnector T able 4-2 shows the signals assigned to the ATX style power conn ector . T abl e 4-2. Primary Power Connector (J1 1 ) Pin Name Function 1 3.3 V 3.3 V 2 3.3 V 3.3 V 3 GND Ground 4 +5V +5 V VCC 5 GND Ground 6 +5V +5 V VCC 7 GN[...]

  • Page 30

    4-4 Celeron™ Proce ssor Deve lopment Ki t Manual Hardware Reference 4.5.2 ITP Debugger Connector 4.5.3 Stacked USB P0 is the bo ttom connecto r . P1 is on to p. T able 4 -3. ITP Connector Pin Assignment (J2 on the Processor Ass embly) Pin Signal Pin Signal 1 RESET# 16 PREQ0# 2 GND 17 GND 3 DBRE SET# 18 PRDY0# 4 GND 19 GND 5 TCK 20 PREQ1# 6 GND 21[...]

  • Page 31

    Celeron™ Proce ssor Developm ent Kit M anual 4-5 Hardware R eference 4.5.4 Mouse and Keyboard Connectors The keyboard port is on top . The mou se port is o n the bot tom. 4.5.5 Parallel Port T abl e 4-5. Keyboard and Mouse Connec tor Pinouts (J1 on the Baseboard) Pin Signal Name 1D a t a 2 No Connect 3 Ground 4 +5 V (fused) 5C l o c k 6 No Connec[...]

  • Page 32

    4-6 Celeron™ Proce ssor Deve lopment Ki t Manual Hardware Reference 4.5.6 Serial Ports COM1 is the top conn ector . COM2 is th e bo ttom connector . 4.5.7 IDE Co nnector T able 4 -7. Serial Port Connector Pinout (J4) Pin Signal Name 1 DCD 2 S erial In (SIN) 3 Serial Out (SOUT) 4D T R 5G N D 6D S R 7R T S 8C T S 9R I T able 4 -8. PCI IDE1 (JP3) an[...]

  • Page 33

    Celeron™ Proce ssor Developm ent Kit M anual 4-7 Hardware R eference 4.5.8 Floppy Drive Connector T able 4-9. Disket te Drive He ader Connector (JP 1) Pin Signal Name Pin Signal Name 1 Ground 2 FDHDIN 3 Ground 4 Reserved 5 Key 6 FDEDIN 7 Ground 8 Index 9 Ground 10 Motor Enable A# 1 1 Ground 12 Drive Select B# 13 Ground 14 Drive Select A# 15 Groun[...]

  • Page 34

    4-8 Celeron™ Proce ssor Deve lopment Ki t Manual Hardware Reference 4.5.9 PCI Slot Connector T able 4-10 . PC I Slo ts ( J7, J 8, J9) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name A1 VCC B1 - 12V A32 AD16 B32 AD17 A2 + 12V B2 GND A33 3.3V B33 CBE2# A3 VCC B3 G ND A34 FRAME# B34 GND A4 VCC B4 No Connect A35 GND B35 IRDY# A5 VCC B[...]

  • Page 35

    Celeron™ Proce ssor Developm ent Kit M anual 4-9 Hardware R eference 4.5.10 ISA Sl ot Connector T abl e 4-1 1. ISA Slots (J5, J6) Pin Signal Name Pin Signal Name P in Signal Name Pin Signal Nam e A1 IOCHK# B1 GND A26 SA5 B26 DACK2# A2 SD7 B2 RST SLOT A27 SA 4 B27 T C A3 SD6 B3 V CC A28 SA3 B28 BALE A4 SD5 B4 IRQB9 A29 SA2 B29 VCC A5 SD4 B5 – 5V[...]

  • Page 36

    4-10 Celeron™ Proce ssor Deve lopment Ki t Manual Hardware Reference 4.6 AGP C onnector T able 4- 12. AGP Slot (J13) P i n # BA P i n # BA 1 OVRCNT# 12V 34 Vddq3.3 Vddq3.3 2 5.0V TYPEDET# 35 AD21 AD22 3 5.0V Reserved 36 AD19 AD20 4 USB+ U SB- 37 GND GND 5 GND GND 38 AD17 AD18 6 INTB# INT A # 39 C/BE2# AD16 7 CLK RST# 40 Vddq3.3 Vddq3.3 8 RE Q# GN[...]

  • Page 37

    Celeron™ Proce ssor Developm ent Kit M anual 4-11 Hardware R eference 4.7 Jum per s T able 4-13 shows default Ju mper sett i ngs . 4.7.1 Enable Spread Spectrum Clocking (J 14) This jumper is used to enable o r disable spread spectrum clock ing on the clock syn thesizer . When this jumper is in, a 0.5% do wn spread will be introduced into the PCI [...]

  • Page 38

    4-12 Celeron™ Proce ssor Deve lopment Ki t Manual Hardware Reference 4.7.4 Flash BIOS VPP Se lect (J 21) This jumper controls the vo ltage presented to the flash BI OS VPP pin. The 2-3 position sup plies 5 V and is the defau lt for no rmal o peratio n. Thi s posi tion inhi bits progr amming or eras ing the flas h BIOS. The 1-2 position suppli es [...]

  • Page 39

    Celeron™ Proce ssor Developm ent Kit M anual 4-13 Hardware R eference 4.8 In-Circuit BIOS Update The BIOS can be up graded in-circuit. B IOS updates may pe riodically be posted to Intel’ s Developers’ site at http:// www .intel.com /des ign/. To r e p r o g r a m t h e B I O S : 1. Set Ju mper J2 1 and J umper J22 t o the 1 -2 positi on on th[...]

  • Page 40

    [...]

  • Page 41

    Celeron™ Proce ssor Developm ent Kit M anual 5-1 BIOS Quick Reference 5 The Celeron pr ocessor evaluation b oard is licensed with a single cop y of Embedd ed BIOS and Embedded DOS softwar e from General Software, Inc. 1 This s oftware is provid ed for demonstrat ion purpos es only and mus t be licens ed directl y from General Software, Inc. for i[...]

  • Page 42

    5-2 Celeron™ Proce ssor Deve lopment Ki t Manual BIOS Quic k Referen ce When the system is powered on for the first time, you’ll need to con figure the system through the Setup Screen System (described later) before peripherals, such as disk drives, are recog nized by the BIOS. The informatio n is written to battery-backed CMOS RAM on th e boar[...]

  • Page 43

    Celeron™ Proce ssor Developm ent Kit M anual 5-3 BIOS Qu ick Refe rence 5.3 Setup Screen System The system is configured from within the Setup Screen System, which is a series of menus that can be invok ed from PO ST by pr essing t he <DEL> k ey if th e main keybo ard is bein g used, or by pressing ^C if the cons ole is bei ng redi rected t[...]

  • Page 44

    5-4 Celeron™ Proce ssor Deve lopment Ki t Manual BIOS Quic k Referen ce 5.3.2 Config uring Drive Assignm ents Embedded BIOS allows the user to map a dif ferent file system to each drive letter . The BIOS allows file systems for each fl oppy (Floppy0 and Floppy 1), each IDE drive (Ide0, I de1, Ide2, and Ide3), and m emory disks when con figured (F[...]

  • Page 45

    Celeron™ Proce ssor Developm ent Kit M anual 5-5 BIOS Qu ick Refe rence 5.3.3 Configuring IDE Drive T ypes If true IDE disk file systems (and not their emu lators, such as ROM, RAM, or flash di sks) are mapped to drive letter s, then the IDE dr ives themselves must be configured in this section. The following table shows the drive assignments for[...]

  • Page 46

    5-6 Celeron™ Proce ssor Deve lopment Ki t Manual BIOS Quic k Referen ce 5.4 Con figuring Boo t Actions Embedded BIOS s upports up to si x dif ferent us er -defined steps in th e boot s equence. Wh en the entire system has b een initialized, POS T executes these steps in order until an operating sy stem successfully loads. In add ition, other pre-[...]

  • Page 47

    Celeron™ Proce ssor Developm ent Kit M anual 5-7 BIOS Qu ick Refe rence 5.6 Shadow Conf iguration Setu p Screen The system’ s Shadow Configuration Setup Screen ( Figure 5-5) allows the selective enabling and disabling of shad owing in 16 Kbyte secti ons, except f or the t op 64 Kbyt es of th e BIOS ROM, which is shadowed as a unit. Norm ally , [...]

  • Page 48

    5-8 Celeron™ Proce ssor Deve lopment Ki t Manual BIOS Quic k Referen ce 5.7 Standard Diag nostics R outines Setup Screen Embedded s ystems may require aut omated burn-in testing in the d evelopment cycle. This facility is provided directly in the system’ s system BIOS through the Standard Diagnostics Routines Setup Screen (Figure 5-6). T o use [...]

  • Page 49

    Celeron™ Proce ssor Developm ent Kit M anual 5-9 BIOS Qu ick Refe rence 5.9 Start RS232 Manufacturing L ink Setup Screen The Embedded B IOS Manufacturi ng Mode may be invok ed from th e Setup S creen main me nu, as well as a boot activity . Once invoked, Manufacturing Mo de takes over the system an d freezes the console of the sy stem (Figure 5-7[...]

  • Page 50

    5-10 Celeron™ Proce ssor Deve lopment Ki t Manual BIOS Quic k Referen ce The software on the tar get can be any terminal emulation prog ram that suppo rts ANSI terminal mode, using 9600 bau d, no parity , and one stop bit (Note: This can be modified by the OEM during BIOS adaptation.) The p rogram must be set to not use flow contro l, or the con [...]

  • Page 51

    Celeron™ Proce ssor Developm ent Kit M anual 5-11 BIOS Qu ick Refe rence T o activate the debugger at an y time from th e main console, press the left shift and the contro l keys together . A d isp lay similar to the one in th e HY PER TER MINAL session b elow (Figure 5-9) will appear , containing the title, “Embedded BIOS Debugger Breakpo in t[...]

  • Page 52

    5-12 Celeron™ Proce ssor Deve lopment Ki t Manual BIOS Quic k Referen ce A complete d iscu ssion of t he debu gger is beyond the scope o f this chapter; however , complet e documentation is available fro m General Software via th e web at http://www .gensw .com. 5.1 1 Em bedded BIOS POST Codes Embedded BIOS writ es pro gress cod es, also kno wn a[...]

  • Page 53

    Celeron™ Proce ssor Developm ent Kit M anual 5-13 BIOS Qu ick Refe rence POST_STATUS_VIDEOROM 2ch Passing control to video ROM. POST_STATUS_POSTVIDEO 2dh Control returned from video ROM. POST_STATUS_CHECKEGAVGA 2eh Check for EGA/VGA adapter. POST_STATUS_TESTVIDEOMEMORY 2fh No EGA/VGA found, test video memory. POST_STATUS_RETRACE 30h Scan for vide[...]

  • Page 54

    5-14 Celeron™ Proce ssor Deve lopment Ki t Manual BIOS Quic k Referen ce POST_STATUS_BEFORESETUP 86h Password accepted. POST_STATUS_CALLSETUP 87h Entering setup system. POST_STATUS_POSTSETUP 88h Setup system exited. POST_STATUS_DISPPWRON 89h Display power-on screen message. POST_STATUS_DISPWAIT 8ah Display "Wait..." message. POST_STATUS[...]

  • Page 55

    Celeron™ Proce ssor Developm ent Kit M anual 5-15 BIOS Qu ick Refe rence 5.12 Emb edded B IOS Beep Co des Embedded BIOS tests much of the system hardware early in POST before messages can be displayed on the screen. When system failures are encountered at these early stages, POST uses beep codes (a seq uence of tones on the speaker) to identify t[...]

  • Page 56

    [...]

  • Page 57

    Celeron™ Proce ssor Developm ent Kit M anual A-1 PLD Code Listing A The code listing below is for the 22V10 PLD. TITLE 22V10 PORT 80 ADDRESS DECODER / FLASH DECODE PATTERN 1 REVISION B AUTHOR CHRIS BANYAI COMPANY INTEL CORPORATION DATE 10/1/97 OPTIONS SECURITY = OFF ; ( part was 22V10FN before conversion ) CHIP P80B iPLD22V10N PIN 19 IOWR_BAR PIN[...]

  • Page 58

    A-2 Celeron™ Proce ssor Deve lopment Ki t Manual PLD Code Li sting SETF AEN /IOWR_BAR SETF /AEN SETF IOWR_BAR SETF SA0 /IOWR_BAR SETF /SA0 /IOWR_BAR SETF IOWR_BAR SETF /SA0 /SA1 /SA2 /SA3 /SA4 /SA5 /SA6 /SA7 /SA8 /SA9 SETF /SA19 /SA18 /SA17 /SA16 /SA15 /SA14 SETF /SEL SETF SA19 SA18 /SA17 /SA16 SA15 /SA14 SETF /SEL SETF /AEN SETF /SA19 SETF SA19 [...]

  • Page 59

    Celeron™ Proce ssor Developm ent Kit M anual B-1 Bill of Materials B T a b le B-1 is the bill of mate rials for th e baseboard. T able B-2 is the bill o f materials for the Proces sor A ssemb ly . T abl e B-1. Base board Bill of Mat erials (Shee t 1 of 4) Reference Description Manufacturer Manufacturer P/N Notes J14,J15 Conn,Jumper2,1X2 25-m il s[...]

  • Page 60

    B-2 Celeron™ Proce ssor Deve lopment Ki t Manual Bill of Materi als U1 1 BIOS FLA SH Memory ,TSOP12X20/40S INTEL 28F002BC U8 VLSI ,PII X4, PCI t o I DE &I SA Bridge,324 mBGA,BGA20x20- 324 Intel FW82371EB U14 IC,Interrupt Controller , 82093AA,QFP16x22-64 INTEL S82093AA DO NOT POPULA TE C99,C100,C132,C133,C2 09,C214 Chip Capacitor ,10pF , 50V ,[...]

  • Page 61

    Celeron™ Proce ssor Developm ent Kit M anual B-3 Bill of Material s R33,R35,R37,R48,R52,R9 8-R100, R106,R108- R1 16,R1 18-R122 Chip Resistor ,0 Ohm Shunt,5%,CR0805 Panasonic ERJ6GE Y0R00V DO NOT POPULA TE R33, R35, R37 R6,R25,R42,R45,R49- R51,R63,R101,R102 Chip Resistor ,1K,5%,CR0805 Panasonic E RJ6GEYJ10 2V DO NOT POPULA TE R6, R51 R2,R4,R5,R1 1[...]

  • Page 62

    B-4 Celeron™ Proce ssor Deve lopment Ki t Manual Bill of Materi als XBT1 Battery Holder Socket Renata HU-2032-1 BT1 Battery Reneta CR2032 D1,D2,D5 Diode,LED,SO T23-A Siemens LGS260-D O U1 VLSI,Super I/O,QFP128 S MSC FDC37B78X C122-C125,C229 Chip Capacitor ,47pF ,CC0603 TDK C1608C0G1H470JT$ DO NOT POPULA TE C229 C9-C21,C24-C26 Chip Capac itor ,220[...]

  • Page 63

    Celeron™ Proce ssor Developm ent Kit M anual B-5 Bill of Material s T abl e B-2. Celer on™ Processor Assembly Bil l of Materials (Sheet 1 of 2) Reference Descriptions Manufacturer Manufacturer P/N C1 CAP 20 pF 25V CC0603 Panasonic ECU-V1H200JCM C1 17 CAP 4700pF 50V CC0603 Panasonic ECJ-1VB 1H472K C84-C85, C94-C98 CAP 0.01uF 10V CC0603 Panas oni[...]

  • Page 64

    B-6 Celeron™ Proce ssor Deve lopment Ki t Manual Bill of Materi als R75,R73 Resistor 47K CR0805 P anasonic ERJ-6GEY J472V R55,R56 Resistor 75 1% CR0805 P anasonic ERJ-6ENF07 50V R60 Resistor 100 1% CR0805 Panasonic ER J-6ENF1000V R6,R5 Resistor 1 10 1% CR0805 Panasonic ER J-6ENF1 100V R57-R59 Resistor 150 1% CR0805 Panasonic ER J-6ENF1500V R61 Re[...]

  • Page 65

    Celeron™ Proce ssor Developm ent Kit M anual C-1 Schematics C The most current schematics, includ ing “flat” sch ematics (without the 400-pin connector), are located on Intel’ s Devel oper W eb sit e at: http://www .intel.co m /design/i ntarch/schems/. Schematics are provi ded fo r the fol lowing i tems: Baseb oa rd: • Block D iagram • [...]

  • Page 66

    5 5 4 4 3 3 2 2 1 1 D D C C B B A A 1. Swapped AD23 and AD19 on 400 pin co n nector. 2. Separated CSEL on IDE0 and IDE1 3. Swapped pins 1 and 3 (V5 with TP) on CPU-Fan c onnector. 4. Tied VBAT (pin 65) to 5.0V on Su p er I/O. 5. Changed RP48 to 4.7K. (Pullups for mouse and k eyboard.) 6. Inverted POWERON# signal (SUSC#) from PIIX4 to control soft -[...]

  • Page 67

    A A B B C C D D E E 4 4 3 3 2 2 1 1 DRAM (DIMM) Page 5,6,7 PIIX4 Page 13,14 PCI Connectors Page 10,11 Super I/O Page 16 Flash Bios Port 80 Page 20 ISA Connectors Page 18 PCI BUS ISA BUS CPU Module Connector Page 4 Power Page 21 Pullups Page 9 IDE Page 15 USB Page 17 PS2 KBD/MS Page 16 Serial Page 19 Parallel Page 19 Floppy Page 19 AGP Port Page 12 [...]

  • Page 68

    A A B B C C D D E E 4 4 3 3 2 2 1 1 THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. {Doc} D Mini PCI Connector C 3 22 Thursday, February 25, 1999 Title Size Document Number Rev Date: Sheet of AD29 AD30 AD0 AD1 AD2 AD3 AD4 AD5 AD6 A[...]

  • Page 69

    A A B B C C D D E E 4 4 3 3 2 2 1 1 Note:GFBCLK must be 3.0" longer than GCKOUT THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. {Doc} D CPU Connector C 4 22 Thursday, February 25, 1999 Title Size Document Number Rev Date: Shee[...]

  • Page 70

    A A B B C C D D E E 4 4 3 3 2 2 1 1 Slave address 10100000b Socket 0 THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. {Doc} D DIMM0 C 5 22 Thursday, February 25, 1999 Title Size Document Number Rev Date: Sheet of MD3 MD4 MD26 MD61 M[...]

  • Page 71

    A A B B C C D D E E 4 4 3 3 2 2 1 1 Slave address 10100001b Socket 1 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END U SER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. {Doc} D DIMM1 C 6 22 Thursday, February 25, 1999 Title Size Document Number Rev Date: Sheet of MD3 MD4 MD26 MD61 M[...]

  • Page 72

    A A B B C C D D E E 4 4 3 3 2 2 1 1 Slave address 10100010b Socket 2 Note: J16 is not popula ted THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. {Doc} D DIMM2 C 7 22 Thursday, February 25, 1999 Title Size Document Number Rev Date: [...]

  • Page 73

    A A B B C C D D E E 4 4 3 3 2 2 1 1 Stuff only to enable stopping of clocks This circuit is only used for TX/Pentium Designs. Note only two DIMMS are supported. This circuit is only used for BX/PentiumII Designs. Note three DIMMS are supported. These caps can be tuned to change delay through buffer. Keep crystal close to cl ock and caps close to cr[...]

  • Page 74

    A A B B C C D D E E 4 4 3 3 2 2 1 1 ISA Pullup s PCI Pullu ps Note IRQ8 Pull-up is on PIIX4 page THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END U SER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. {Doc} D ISA/PCI Pul lups C 9 22 Thursday, February 25, 1999 Title Size Document Number[...]

  • Page 75

    A A B B C C D D E E 4 4 3 3 2 2 1 1 PCI SLOT 0 PCI SLOT 1 J7/J8 V5_ 0: A5, A8, A10, A16, A59, A61, A62 | A1, A3, A4 B5, B6, B19, B22, B59, B61, B62 J7/J8 V3_ 3: A21, A27, A33, A39 A45, A53 B25, B31, B36, B41, B43, B54 J7/J8 N C: A9, A11, A1 4, A19 B10, B14 J7/J8 GN D: A12, A13, A18, A24, A30, A35, A37, A42, A48, A56 B3, B12, B13, B15, B17, B28, B34[...]

  • Page 76

    A A B B C C D D E E 4 4 3 3 2 2 1 1 PCI SLOT 2 THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. {Doc} D PCI Slot 2 C 11 22 Thursday, February 25, 1999 Title Size Document Number Rev Date: Sheet of AD4 AD9 AD17 AD5 AD13 AD14 AD3 AD20[...]

  • Page 77

    A A B B C C D D E E 4 4 3 3 2 2 1 1 Stub length from connector to resistor must be less than 0.1" Pin A3 is tied to ground per AGP Specification Rev 1.0 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END U SER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. D AGP Connector C 12 22 T[...]

  • Page 78

    A A B B C C D D E E 4 4 3 3 2 2 1 1 PIIX4 is PCI device #8 This circuit is to prevent IOAPIC from being powered by IRQ#8 when in suspend and power is not applied to device. Note: U14, C203,C215, C210 , R50 and R51 are not popula ted THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT[...]

  • Page 79

    A A B B C C D D E E 4 4 3 3 2 2 1 1 CPU Module must drive CONFIG1l to indicate processor type. 3.3V = PentiumII 0V = Pentium 1-2 Normal Operation 2-3 Clear CMOS Keep crystal close to PIIX4 and caps close to crystal Trace lengths should be equal THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. [...]

  • Page 80

    A A B B C C D D E E 4 4 3 3 2 2 1 1 Primary IDE Connect or Secondary IDE Connect or HD Active LED THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. {Doc} D IDE Connectors C 15 22 Thursday, February 25, 1999 Title Size Document Number[...]

  • Page 81

    A A B B C C D D E E 4 4 3 3 2 2 1 1 PULL romCs# high so as not to interfere with boot rom! Install for 370 Config address Install for 3F0 Config address Do not stuff Install only one resistor! This disables the ROM buffers. BIOS needs to enable and configure IRQs THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN[...]

  • Page 82

    A A B B C C D D E E 4 4 3 3 2 2 1 1 NOTE 1: USB differential traces route together (Z0- & Z0+) and (Z1- & Z1+). Must be 45 Ohm Matched Stripline width 0.015 (for 1 oz)->44.88/45.45 Ohm. 8Ohm/100MHz/500mA 8Ohm/100MHz/500mA PCB Trace 45 Ohm Matched, Routed Together Stripline width 0.015 (1 oz) 44.88/45.45 Ohm Poly-F use Poly-F use NOTE 2: [...]

  • Page 83

    A A B B C C D D E E 4 4 3 3 2 2 1 1 ISA Slots J5/J6 V5_ 0: B03, B29, B3 1, D16 J5/J6 GN D: B01, B10, D18 J5/J6: +12V B09 -12V B07 -5V B05 Note Cap Direc tion Note Cap Direc tion THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END U SER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. {Doc}[...]

  • Page 84

    A A B B C C D D E E 4 4 3 3 2 2 1 1 COM0/COM1 FLOPPY PARALLEL COM1 COM0 THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. {Doc} D COMx, DB25, Floppy C 19 22 Thursday, February 25, 1999 Title Size Document Number Rev Date: Sheet of SP[...]

  • Page 85

    A A B B C C D D E E 4 4 3 3 2 2 1 1 Expect All 0's except SA7=1 for P80 Decode Standard Stuff Option Port 80 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END U SER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. {Doc} D BIOS/ Port 80 C 20 22 Thursday, February 25, 1999 Title Size [...]

  • Page 86

    A A B B C C D D E E 4 4 3 3 2 2 1 1 Note Cap Dire ction Power Indicator s SPEAKER HEADER Open Collec tor PS_OK = OR of PW_OK,-DBRESET,RESET SWITCH Note: Add screen marking for V5_0 LED, V3_3 LED Place at ATX Connector Place at ATX Connector Place at ATX Connector Place at ATX Connector Place at ATX Connector Note Cap Direction THIS DRAWING CONTAINS[...]

  • Page 87

    A A B B C C D D E E 4 4 3 3 2 2 1 1 Make these connections Cutable Make these connections Cutable Make these connections Cutable Make these connections Cutable Make these connections Cutable Make these connections Cutable THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBL[...]

  • Page 88

    5 5 4 4 3 3 2 2 1 1 D D C C B B A A No license, express or implied, by estoppel or otherwise, to an y intellectual property rights is granted herein. Revision A1 THIS DRAWING CONTAINS INFOR MATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACT URING AS AN END USER PRODUCT. INTEL IS NOT R ESPONSIBLE FOR THE MISUSE OF THIS I NFORMATION. Intel disclaims all[...]

  • Page 89

    5 5 4 4 3 3 2 2 1 1 D D C C B B A A Socket 370 Page 3&4 440BX Page 7&8 CPU Connector Page 9 GTL+ Termination Page 5 & 6 GTL+ ITP Bus Ratio Logic Thermal Sensor Page 10 Voltage Regulator Page 11 THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULA[...]

  • Page 90

    A A B B C C D D E E 4 4 3 3 2 2 1 1 THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE. Do Not Populate CPU Fan Conn ector Voltage Tran slators Needed for CuMine FERR# Vol[...]

  • Page 91

    A A B B C C D D E E 4 4 3 3 2 2 1 1 **REFERENCE VOLTAGE FOR P ROCESSOR. THERE ARE 8 VREF PINS. PLACE ONE CAPACITOR NEAR EVERY 2 VREF PINS. Make MREF as short and fat a s possible. Use at least 24 m ill line. THIS DRAWING CONTAINS INFORM ATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTU RING AS AN END USER PRODUCT. INTEL IS NOT RE SPONSIBLE FOR THE MI[...]

  • Page 92

    5 5 4 4 3 3 2 2 1 1 D D C C B B A A GTL+ TERMINATION RESISTORS-BX THIS DRAWING CONTAINS INFOR MATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACT URING AS AN END USER PRODUCT. INTEL IS NOT R ESPONSIBLE FOR THE MISUSE OF THIS I NFORMATION. Resistor Packs placed for Dual End Termination. Not used on Celeron Processor in PPGA package with Single End Termi[...]

  • Page 93

    5 5 4 4 3 3 2 2 1 1 D D C C B B A A Place one Cap near every two R-packs THIS DRAWING CONTAINS INFORM ATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTU RING AS AN END USER PRODUCT. INTEL IS NOT RE SPONSIBLE FOR THE MISUSE OF THIS I NFORMATION. NOTE : VTT = TERMIN ATI ON VOLTAGE GTL+ TERMINATION RESISTORS-CPU Celeron Processor Adaptor A GTL Terminatio[...]

  • Page 94

    5 5 4 4 3 3 2 2 1 1 D D C C B B A A Place as cl ose as possible to B X Are these suppose to be 0.001uF? Note: PCI 5V THIS DRAWING CONTAINS INFORM ATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTU RING AS AN END USER PRODUCT. INTEL IS NOT RE SPONSIBLE FOR THE MISUSE OF THIS I NFORMATION. Do Not S tuff Do Not S tuff Do Not Stuff Celeron Processor Adapt[...]

  • Page 95

    5 5 4 4 3 3 2 2 1 1 D D C C B B A A Resistor Function Board De fault Setting R21 R22 R23 R24 R25 In-Order Queue Depth Enable. Quick Start Select AGP Dis able Memory Mo dule Configura tion Host Bus Buffer Mode Select Do Not S tuff Do Not S tuff Do Not S tuff Signal MAB10# MAB9# MAB7# MAB6# MAB11# Do Not S tuff Do Not S tuff BX Strapping Options THIS[...]

  • Page 96

    5 5 4 4 3 3 2 2 1 1 D D C C B B A A AGP clock signals Layout: G_CLKIN,GCLKO_A+G_CLKOUT, GCLKO_B+G_CLKOUT should all be the same length Mounting Holes THIS DRAWING CONTAINS INFORM ATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTU RING AS AN END USER PRODUCT. INTEL IS NOT RE SPONSIBLE FOR THE MISUSE OF THIS I NFORMATION. Routing Guidelin es: Route HCLK[...]

  • Page 97

    5 5 4 4 3 3 2 2 1 1 D D C C B B A A UNUSED GATES BUS RATIO SE L EC T FOR PR OCESSOR Address Select Straps Current Address: 1001 110 THE RM AL SENSOR THIS DRAWING CONTAINS INFOR MATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACT URING AS AN END USER PRODUCT. INTEL IS NOT R ESPONSIBLE FOR THE MISUSE OF THIS I NFORMATION. Pullups on Sh akopee? CRESET# fr[...]

  • Page 98

    5 5 4 4 3 3 2 2 1 1 D D C C B B A A GTL Reference Voltage Generator Place c lose to C S- /CS+ Place near pin 3 Place ar ound uProcessor Note: AGND must tie directly to nearest output CAP. DO NOT TIE DIRECTLY TO GROUND PLANE. Place near pin 4 Cout Run Para llel GND to AGND co nnection THIS DRAWING CONTAINS INFOR MATION WHICH HAS NOT BEEN VERIFIED FO[...]

  • Page 99

    Celeron™ Proce ssor Developm ent Kit M anual Index-1 Index #, d efine d 1-1 440BX AGP set 3-2 82371EB PCI ISA IDE Xce lerator (PIIX4E) 2-1 , 3-4 82443BX Host Bridge/Controller 2-1 A Address siz e 3-3 AGP connector 3-5 , 4-10 AGP support 2-1 , 3-2 , 3-3 ATX power conne ctor 4-3 B Baseboard 2-1 Beep codes 5-1 , 5-15 BIOS 2-7 Basic Setup Screen 5-3 [...]

  • Page 100

    Index-2 Celeron™ Proce ssor Deve lopment Ki t Manual J15, cl oc k frequen cy select ion 4-11 J20, on/ of f 4- 11 J21, flash BIOS VPP select 4-1 2 J22 , f l ash BIOS bo ot block cont rol 4-1 2 J23, SMI# source control 4-12 J24, CMOS RAM clear 4-12 K Keyb oard 2-4 , 3-5 , 4-5 Kit co nt ents 2-2 M Measurem ents, defi n ed 1-2 Memory ad dres s space [...]