IBM 25CPC710 manual

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Table of contents for the manual

  • Page 1

    Page 1 of 8 Ver sion 1.0 11/08/01 Abstract This Application Note describes the differences between the CPC710 - 100+ (DD2) and the CPC710 (DD3.x) versions of the PowerPC Dual PCI/Memory Controller companion chip. The purpose of this not e is to provide designers with an overview of the changes and point out performance enhancements and potential pr[...]

  • Page 2

    Page 2 of 8 Ver sion 1.0 11/08/01 Processor Interface: v Voltage Level and Bus Speed Differences Ø The CPC710 DD3.x revision supports 60x bus operation at speeds of up to 133MHz, at an I/O voltage of 2.5V. This interface voltage level is supported on the PPC750L, 750CX, and 750CXe processors. This is a change from the previous revision. v I/O Sign[...]

  • Page 3

    Page 3 of 8 Ver sion 1.0 11/08/01 Memory Interface: v Extended SDRAM Addressing Ø The signal MADDR13 has been added to support the following additional SDRAM organizations: § 13 - 12 - 2, 14 - 9 - 2, 14 - 10 - 2, 14 - 11 - 2, 14 - 12 - 2 § Register SDRAM0_MCER [26:29] is used to select the SDRAM organization; refer to the CPC710 - 133 User’s M[...]

  • Page 4

    Page 4 of 8 Ver sion 1.0 11/08/01 v Extended Addressing of PCI Memory Ø System memory addressing range in creased from 2GB to 4GB. The standard addressing capability is 2GB; with the size defined by bits 24 - 31 of PCI local registers PCILx_PSSIZE. The address extension is implemented by setting bit 27 of chip control register CPC0_PGCHP. In this [...]

  • Page 5

    Page 5 of 8 Ver sion 1.0 11/08/01 plane. In most circumstances, however, it is prudent to place a filter circuit on AVDD; refer to the CPC710 DD3.x User’s Manual for mor e information. Ø The PLL is now set up and controlled by external signals PLL_RANGE [1:0] and 6 external signals PLL_TUNE [5:0] instead of PLL133 and PLL_TUNE [1:0]. This is a c[...]

  • Page 6

    Page 6 of 8 Ver sion 1.0 11/08/01 v I/O Pi n Additions: The following I/Os are new on the DD3 revision: INTERFACE SIGNAL NAME IMPACT 60x bus Interface SYS_BG2_, SYS_BG3_, SYS_MCP2, SYS_MCP3, SYS_HRESET2, SYS_HRESET3, SYS_SRESET2, SYS_SRESET3 New for 4 - way CPU support 60x bus Interface SYS_TA_HIT Memory Interface MADDR13 Used for newer memory size[...]

  • Page 7

    Page 7 of 8 Ver sion 1.0 11/08/01 Performance Enhanc ements and Improvements: v The CPC710 DD3.x revision has improvements to support PCI Long Burst Write operations and improvements in the deadlock prevention circuits. These enhancements can be selected by programming select bits in PCI local registers PCILx _PSWCR and PCILx_DLKCTRL. Ø Crossing a[...]

  • Page 8

    Page 8 of 8 Ver sion 1.0 11/08/01 (c) Copyright International Business Machines Corporation 2001 All Rights Reserved Printed in the United States of America November 2001 The follo wing are trademarks of International Business Machines Corporation in the United States, or other countries, or both: IBM PowerPC IBM Logo Other company, product and ser[...]