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Cypress STK14C88-5 manual

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Table of contents for the manual

  • Page 1

    STK14C88-5 256 Kbit (32K x 8) AutoS tore nvSRAM Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-51038 Rev . ** Revised March 02, 2009 Features ■ 35 ns and 45 ns access times ■ Hands off automatic STORE on power down with externa l 68 µF capacitor ■ STORE to QuantumT[...]

  • Page 2

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 2 of 17 Pin Configurations Pin Definitions Pin Name Alt IO T ype Description A 0 –A 14 Input Address Inp uts . Used to select one of the 32,768 bytes of the nvSRAM. DQ 0 -DQ 7 Input or Output Bidirectio na l Data IO Lines . Used as input or output lines depending on opera ti on. WE W Input Write[...]

  • Page 3

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 3 of 17 Device Operation The STK14C88-5 nvSRAM is made up of two functional compo- nents paired in the same physical cell. These ar e an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolat[...]

  • Page 4

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 4 of 17 Hardware STORE (HSB ) Operation The STK14C88-5 provides the HSB pin for cont rolling an d acknowledging the STORE operations. The HSB pin is used to request a hardware ST OR E cycle. When the HSB pin is driven LOW , the STK14C88-5 co nditionally initiate s a STORE operation after t DELA Y [...]

  • Page 5

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 5 of 17 Dat a Protection The STK14C88-5 protects data from corruption during low voltage conditions by inhibiting all externally in itiated STORE and WRITE operations. The l ow voltage condition is detected when V CC is less than V SWITCH . If the STK14C88-5 is in a WRITE mode (both CE and WE are [...]

  • Page 6

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 6 of 17 Best Practices nvSRAM products have been used effectively for over 15 years. While ease of use is one of t he product’s main system values, experience gained worki ng with hundreds of appli cations has resulted in the following suggestions as be st practices: ■ The nonvolatile cell s i[...]

  • Page 7

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 7 of 17 Maximum Ratin gs Exceeding maximum ratings may shorten the useful life of the device. These user guid elines are not tested. S torage T emperature ........................... ... .. . –65 ° C to +150 ° C T emperature under Bias ................. ............ –55 ° C to +125 ° C V o[...]

  • Page 8

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 8 of 17 Cap acit ance In the following table, the capacitance parameters are listed. [8] Parameter Description T est Condition s Max Unit C IN Input Capacit ance T A = 25 ° C, f = 1 MHz, V CC = 0 to 3.0V 5p F C OUT Output Capacit a nce 7p F Thermal Resist ance In the following table, the thermal [...]

  • Page 9

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 9 of 17 AC Switching Characteristics SRAM Read Cycle Parameter Description 35 ns 45 ns Unit Min Max Min Max Cypress Parameter Alt t ACE t ELQV Chip Enable Access Time 35 45 ns t RC [9] t AVAV, t ELEH Read Cycle T ime 35 45 ns t AA [10] t AV Q V Address Access T ime 35 45 ns t DOE t GLQV Output Ena[...]

  • Page 10

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 10 of 17 SRAM Write Cycle Parameter Description 35 ns 45 ns Unit Min Max Min Max Cypress Parameter Alt t WC t AVAV W rite Cycle T ime 35 45 ns t PWE t WL WH, t WLEH Write Pulse Width 25 30 ns t SCE t EL WH, t ELEH Chip Enable T o End of W ri te 25 30 ns t SD t DVWH, t DVEH Data Setup to End of Wri[...]

  • Page 11

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 1 1 of 17 AutoS tore or Power Up RECALL Parameter Alt Description STK14C88-5 Unit Min Max t HRECALL [15] t REST ORE Power up RECALL Duration 550 μ s t STORE [16] t HLHZ STORE Cycle Duration 10 ms t DELA Y [16] t HLQZ , t BLQZ Time Allowed to Complete SRAM Cycle 1 μ s V SWITCH Low V oltage T rigg[...]

  • Page 12

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 12 of 17 Sof tware Controlled STORE/RECALL Cycle The software controlled ST ORE/RECALL cycle follows. [19] Parameter Alt Description 35 ns 45 ns Unit Min Max Min Max t RC [16] t AVAV ST ORE/RECALL Initiation Cycle Time 35 45 ns t SA [18, 19] t A VEL Address Setup Time 0 0 ns t CW [18, 19] t ELEH C[...]

  • Page 13

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 13 of 17 Hardware STORE Cycle Parameter Alt Description STK14C88-5 Unit Min Max t DHSB [16, 20] t RECOVER, t HHQX Hardware STORE High to Inhibit Off 700 ns t PHSB t HLHX Hardware STORE Pulse Width 15 ns t HLBL Hardware ST ORE Low to ST ORE Busy 300 ns Switching W aveforms Figure 14. Hardware STORE[...]

  • Page 14

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 14 of 17 Ordering Information Spe e d (ns) Ordering Code Package Diagram Package T ype Operating Range 35 STK14C88-5C35M 001-51694 32-pi n CDIP (300 mil ) Military STK14C88-5K35M 001-51694 32-pi n CDIP (300 mil) STK14C88-5L35M 51-80068 32-pin LCC (450 mil) 45 STK14C88-5C45M 001-51694 32-pi n CDIP [...]

  • Page 15

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 15 of 17 Package Diagram Figure 15. 32-Pin (300-Mil) Side Braze DIL (001-51694) 001-51694 ** [+] Feedback[...]

  • Page 16

    STK14C88-5 Document Number: 001-51038 Rev . ** Page 16 of 17 Figure 16. 32-Pad (450-Mil) LCC (51-80068) Package Diagram (continued) 51-80068- ** [+] Feedback[...]

  • Page 17

    Document Number: 001-51038 Rev . ** Revised March 02, 2009 Page 17 of 17 AutoS tore and Qua ntumTr ap are registered tr ademarks of Cypress Se miconductor Corpor ation. All produ cts and comp any names mentio ned in this document may be the trademarks of thei r respective holders. STK14C88-5 © Cypress Semiconducto r Corporatio n, 2009. The informa[...]