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Cypress CY7C1526V18 manual

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Table of contents for the manual

  • Page 1

    72-Mbit QDR™-II SRAM 4-W ord Burst Architecture CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-05363 Rev . *F Revised August 06, 2008 Features ■ Separate independent read and write data ports ❐ Supports concurrent tr[...]

  • Page 2

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 2 of 32 Logic Block Diagra m (CY7C151 1V18) Logic Block Diagram (CY7C1526V18) 2M x 8 Array CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 16 21 32 8 NWS [1:0] [...]

  • Page 3

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 3 of 32 Logic Block Diagram (CY7C1513V18) Logic Block Diagram (CY7C1515V18) CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 36 20 72 18 BWS [1:0] V REF Write A[...]

  • Page 4

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 4 of 32 Pin Configuration The pin configuration for CY7C151 1V18 , CY7C 1526V18, CY7C1513V18 , and CY7C1515V18 follow . [1] 165-Ball FBGA (15 x 17 x 1 .4 mm) Pinout CY7C151 1V18 (8M x 8) 123456789 10 11 A CQ AA W P S NWS 1 K NC/144M RPS AA C Q B NC NC NC A NC[...]

  • Page 5

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 5 of 32 CY7C1513V18 (4M x 1 8) 123456789 10 11 A CQ V SS /144M AW P S BWS 1 K NC/28 8M RPS AA C Q B NC Q9 D9 A NC K BWS 0 AN C N C Q 8 C NC NC D10 V SS AN CA V SS NC Q7 D8 D NC D1 1 Q1 0 V SS V SS V SS V SS V SS NC NC D7 E NC NC Q1 1 V DDQ V SS V SS V SS V DD[...]

  • Page 6

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 6 of 32 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks when valid write operations are active. CY7C151 1V18 − D [7:0] CY7C1526V18 − D [8:0] CY7C1513V18 − D [17:0] [...]

  • Page 7

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 7 of 32 CQ Echo Clock CQ Referenced with Respect to C . This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II. In the single clock mode , CQ is generated wi th respect to K. The timing s for the echo clocks are [...]

  • Page 8

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 8 of 32 Functional Overview The CY7C151 1V18, C Y7C1526V18, CY7C1513V18, CY7C1515V18 are synchronous pipeline d Burst SRAMs with a read port and a write port. The read port is dedicated to rea d operations and the write port is dedicated to write operations. [...]

  • Page 9

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 9 of 32 Concurrent T ransactions The read and write ports on the CY7C151 3V18 operates completely independe ntly of one another . As each port latches the address in puts on different clock edges, the user ca n read or write to any location, regardless of the[...]

  • Page 10

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 10 of 32 Application Example Figure 1 shows four QDR-II used in an application. Figure 1. Application Example T ruth T a ble The truth table for CY7C151 1V18, CY7C1526V 18, C Y7C1513V18, and C Y7C1515V18 follows. [2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ D[...]

  • Page 11

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 1 1 of 32 Write Cycle Descriptions The write cycle description table for CY7C151 1V18 and CY 7C1513V18 follows. [2, 10] BWS 0 / NWS 0 BWS 1 / NWS 1 K K Comments L L L–H – During the data portion of a write sequence : CY7C151 1V18 − both nibbles (D [7:0][...]

  • Page 12

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 12 of 32 Write Cycle Descriptions The write cycle description t able for CY7C1 515V18 follows. [2, 10] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments LLLL L – H – D u r i n g t h e D a t a p o r t i o n o f a w r i t e s equence, all four bytes (D [35:0] ) are writ[...]

  • Page 13

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 13 of 32 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 14 9.1-1900. The T AP operates using JEDEC standard 1.8V IO l[...]

  • Page 14

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 14 of 32 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister . It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the T AP controller enters th e Shi[...]

  • Page 15

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 15 of 32 T AP Controller St ate Diagram The state diagram for the T AP controller follows. [1 1] TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0[...]

  • Page 16

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 16 of 32 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [12, 13, 14] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V olt age I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V olt age I OH = − 100 μ [...]

  • Page 17

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 17 of 32 T AP AC Switching Characteristics Over the Operating Range [15, 16] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t TMSS TMS Setup t[...]

  • Page 18

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 18 of 32 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C151 1V18 C Y7C1526V18 CY7C1513V18 C Y7C1515V18 Revision Numb er (31:29) 000 000 000 000 V ersion number . Cypress Device ID (28:12) 1 101 001 101 10 00100 1 1 01001 101 [...]

  • Page 19

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 19 of 32 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum p ID 0 6R 28 10G 56 6A 84 1J 1 6 P2 9 9 G 5 7 5 B8 5 2 J 2 6N 30 1 1F 58 5A 86 3K 3 7P 31 1 1G 59 4A 87 3J 4 7 N3 2 9 F 6 0 5 C8 8 2 K 5 7R 33 10F 61 4B 89 1K 6 8R 34 1 1E 62 3A [...]

  • Page 20

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 20 of 32 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operations. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (All other inputs can be HIGH or LOW). ❐ [...]

  • Page 21

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 21 of 32 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature ....... ................. ......... –65°C to +150°C Ambient T empe r at ur e with Power Appl i ed. [...]

  • Page 22

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 22 of 32 I DD [21] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200MHz (x8) 655 mA (x9) 660 (x18) 715 (x36) 850 167MHz (x8) 570 mA (x9) 575 (x18) 615 (x36) 725 I SB1 Automatic Power down Current Max V DD , Both Ports Deselected, V IN ?[...]

  • Page 23

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 23 of 32 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V , V DDQ = 1.5V 5.5 pF C CLK Clock In[...]

  • Page 24

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 24 of 32 Switching Characteristics Over the Operating Range [22, 23] Cypress Parameter Consor tium Parameter Description 300 MHz 278 MHz 250 MHz 20 0 MHz 167 MHz Unit Min Max Min Max Min Max Min Max Min Max t POWER V DD (T ypical) to the First Access [24] 111[...]

  • Page 25

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 25 of 32 Output T imes t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data V alid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold af ter Output C/C Clock Rise (Active to Active) –0.45 – – 0.45 – –0.45 – ?[...]

  • Page 26

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 26 of 32 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 8, 29, 30 ] K 1 2 34 5 6 7 RPS WPS A Q D C C READ READ WRITE WRITE NOP NOP DON’ T CARE UNDEFINED CQ CQ K A0 A1 t KH t KHKH t KL t CY C t t HC t SA t HA A2 SC tt HC SC A3 t KHCH t KHCH t[...]

  • Page 27

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 27 of 32 Ordering Information Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www .cypress.com for actual products offered. Spee d (MHz) Ordering Code Package Diagram Package T ype O[...]

  • Page 28

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 28 of 32 250 CY7C151 1V18-250BZC 51-85195 1 65-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1526V18-250BZC CY7C1513V18-250BZC CY7C1515V18-250BZC CY7C151 1V18-25 0BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free[...]

  • Page 29

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 29 of 32 167 CY7C151 1V18-167BZC 51-85195 1 65-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1526V18-167BZC CY7C1513V18-167BZC CY7C1515V18-167BZC CY7C151 1V18-16 7BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free[...]

  • Page 30

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 30 of 32 Package Diagram Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-8 5195 !  0).#/2.%2 ¼ ¼   [...]

  • Page 31

    CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 31 of 32 Document History Page Document Title: CY7C151 1V18/CY7 C152 6V18/CY7C1513V18/CY7C1515V18, 72-Mb it QDR™-II SRAM 4-Word Burst Archi- tecture Document Number: 38-05363 REV . ECN NO. SUBMISSION DA TE ORIG . OF CHANGE DESCRIPTION OF CHANGE ** 226981 Se[...]

  • Page 32

    Document Number: 38-05363 Rev . *F Revised August 06, 2008 Page 32 of 32 QDR RAMs and Qua d Data Ra te RA Ms comprise a ne w fam i ly of pr od uct s developed by Cypress, Hit a chi, IDT , NEC, an d S am sun g. A ll pr odu ct a nd comp any names mentioned in this document are the tradem arks of their r es pective hold ers. CY7C151 1V18, CY7C1526V18 [...]