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Cypress CY7C1515JV18 manual

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Table of contents for the manual

  • Page 1

    72-Mbit QDR™-II SRAM 4-W ord Burst Architecture CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-12560 Rev . *C Revised March 10, 2008 Features ■ Separate independent read and write data ports ❐ Supports concurren[...]

  • Page 2

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 2 of 27 Logic Block Diagra m (CY7C151 1JV18) Logic Block Diagram (CY7C1526JV18) 2M x 8 Array CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 16 21 32 8 NWS[...]

  • Page 3

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 3 of 27 Logic Block Diagram (CY7C1513JV18) Logic Block Diagram (CY7C1515JV18) CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 36 20 72 18 BWS [1:0] V REF [...]

  • Page 4

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 4 of 27 Pin Configuration The pin configuration for CY7C151 1JV18, CY7C1513JV18, and CY7C1515JV18 follow . [1] 165-Ball FBGA (15 x 17 x 1 .4 mm) Pinout CY7C151 1JV18 (8M x 8) 123456789 1 0 1 1 A CQ AA W P S NWS 1 K NC/144M RPS AA C Q B NC NC NC A NC/288M[...]

  • Page 5

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 5 of 27 CY7C1513JV18 (4 M x 18) 123456789 1 0 1 1 A CQ NC/144M A WPS BWS 1 K NC/288M RPS AA C Q B NC Q9 D9 A NC K BWS 0 AN C N C Q 8 C NC NC D10 V SS AN CA V SS NC Q7 D8 D NC D1 1 Q1 0 V SS V SS V SS V SS V SS NC NC D7 E NC NC Q1 1 V DDQ V SS V SS V SS V[...]

  • Page 6

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 6 of 27 Pin Definitions Pin Name IO Pin Descripti on D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks when valid write operations are active. CY7C151 1JV18 − D [7:0] CY7C1526JV18 − D [8:0] CY7C1513JV18 − [...]

  • Page 7

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 7 of 27 CQ Echo Clock CQ is Referenced with Respect to C . This is a free running clock and is synchronized to the input cl ock for output data (C) of the QDR-II. In the single clock mode , CQ is generated wi th respect to K. The timing s for the echo cl[...]

  • Page 8

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 8 of 27 Functional Overview The CY7C151 1JV18, CY7C1526JV18 , CY7C1513JV18, CY7C1515JV18 are synchronous pipel ined Burst SRAMs with a read port and a write port. The read port is dedicated to rea d operations and the write port is dedicated to write ope[...]

  • Page 9

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 9 of 27 Concurrent T ransactions The read and write ports on the CY7C1513JV1 8 operates completely independe ntly of one another . As each port latches the address in puts on different clock edges, the user ca n read or write to any location, regardless [...]

  • Page 10

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 10 of 27 Application Example Figure 1 shows four QDR-II used in an application. Figure 1. Application Example T ruth T able The truth table for CY7C151 1JV18, CY7C1526 JV1 8, CY7C1513JV18, and CY7C1515JV18 follow s. [2, 3, 4, 5, 6, 7] Operation K RPS WPS[...]

  • Page 11

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 1 1 of 27 Write Cycle Descriptions The write cycle description table for CY7C151 1JV18 and CY7C1513 JV18 fo llows. [2, 10] BWS 0 / NWS 0 BWS 1 / NWS 1 K K Comments L L L–H – During the data portion of a write sequence : CY7C151 1JV18 − both nibbles[...]

  • Page 12

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 12 of 27 Write Cycle Descriptions The write cycle description tabl e for CY7C1515JV18 follows. [2, 1 0] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments LLLL L – H – D u r i n g t h e D a t a p o r t i o n o f a w r i t e s equence, all four bytes (D [35:0] ) ar[...]

  • Page 13

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 13 of 27 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 14 9.1-2001. The T AP operates using JEDEC standard 1.8V[...]

  • Page 14

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 14 of 27 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister . It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the T AP controller enters the[...]

  • Page 15

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 15 of 27 T AP Controller St ate Diagram The state diagram for the T AP controller follows. [1 1] TEST -LOGIC RESET TEST -LOG IC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0[...]

  • Page 16

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 16 of 27 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [12, 13, 14] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V oltage I OH = − 100 [...]

  • Page 17

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 17 of 27 T AP AC Switching Characteristics Over the Operating Range [15, 16] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t TMSS TMS Se[...]

  • Page 18

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 18 of 27 Identification R egi ster Definitions Instruction Field Va l u e Descriptio n CY7C151 1JV18 CY7C1526JV18 CY7C1513JV18 CY7C1515JV18 Revision Numb er (31:29) 001 001 001 001 V ersio n number . Cypress Device ID (28:12) 1 101 001 101 1000100 1 1010[...]

  • Page 19

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 19 of 27 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6 P2 9 9 G 5 7 5 B8 5 2 J 2 6N 30 1 1F 58 5A 86 3K 3 7P 31 1 1G 59 4A 87 3J 4 7 N3 2 9 F 6 0 5 C8 8 2 K 5 7R 33 10F 61 4B 89 1K 6 8R 34 1 1E 62[...]

  • Page 20

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 20 of 27 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operations. During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of st able clock. Power [...]

  • Page 21

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 21 of 27 Maximum Ratings Exceeding maximum ratin gs may impair the useful life of the device. These user guidelines are not teste d. S torage T emperature ............. ................. ... –65°C to +150°C Ambient T empe r at ur e with Power Appl i [...]

  • Page 22

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 22 of 27 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V , V DDQ = 1.5V 5.5 pF C CLK Clo[...]

  • Page 23

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 23 of 27 Switching Characteristics Over the Operating Range [21] Cypress Parameter Consor tium Parameter Description 300 MHz Unit Min Max t POWER V DD (T ypical) to the First Access [22] 1m s t CYC t KHKH K Clock and C Clock Cycle T ime 3.3 8.4 ns t KH t[...]

  • Page 24

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 24 of 27 Switching W aveforms Figure 3. Read/Write/Deselect Sequence [2 6, 27, 28 ] K 1 2 34 5 6 7 RPS WPS A Q D C C READ READ WRITE WRITE NOP NOP DON’ T CARE UNDEFINED CQ CQ K A0 A1 t KH t KHKH t KL t CY C t t HC t SA t HA A2 SC tt HC SC A3 t KHCH t K[...]

  • Page 25

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 25 of 27 Ordering Information Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www .cypress.com for actual products offered. Spee d (MHz) Ordering Code Pack age Diagram Package T[...]

  • Page 26

    CY7C151 1JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev . *C Page 26 of 27 Package Diagram Figure 4. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 !  0).#/2.%2 ¼ ¼   ?[...]

  • Page 27

    Document Number: 001-12560 Rev . *C Revised March 10, 2008 Page 27 of 27 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s develope d by Cypress, IDT , NEC, Renesas, and Samsung. All pr oduct and co mpany nam es mentione d in this docum ent are the tr ad emarks of their resp e ctive hold ers. CY7C151 1JV18, CY7C1526JV18 CY7C1513[...]