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Cypress CY7C1473BV25 manual

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Table of contents for the manual

  • Page 1

    72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-15013 Rev . *E Revised February 29, 2008 Features ■ No Bus Latency™ (NoBL™) architecture eliminates dead c[...]

  • Page 2

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 2 of 30 Logic Block Diagram – CY7C1471BV25 (2M x 36) Logic Block Diagram – CY7C1473BV25 (4M x 18) C MODE BW A BW B WE CE1 CE2 CE3 OE READ LOGIC DQs DQP A DQP B DQP C DQP D MEMORY ARRAY E INPUT REGISTER BW C BW D ADDRESS REGISTER WRITE REGISTRY AND DATA COHERENCY CONTROL[...]

  • Page 3

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 3 of 30 Logic Block Diagram – CY7C1475BV25 (1M x 72) A0, A1, A C MODE CE1 CE2 CE3 OE READ LOGIC DQ s DQ Pa DQ Pb DQ Pc DQ Pd DQ Pe DQ Pf DQ Pg DQ Ph D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGIST[...]

  • Page 4

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 4 of 30 Pin Configurations A A A A A1 A0 NC/288M NC/144M V SS V DD A A A A A A DQP B DQ B DQ B V DDQ V SS DQ B DQ B DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SS DQ A DQ A DQ A DQ A V SS V DDQ DQ A DQ A DQP A DQP C DQ C DQ C V DDQ V SS DQ C DQ C DQ C DQ C[...]

  • Page 5

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 5 of 30 Pin Configurations (continued) A A A A A1 A0 NC/288 M NC/144M V SS V DD A A A A A A A NC NC V DDQ V SS NC DQP A DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD DQ A DQ A V DDQ V SS DQ A DQ A NC NC V SS V DDQ NC NC NC NC NC NC V DDQ V SS NC NC DQ B DQ B V SS V DDQ DQ B D[...]

  • Page 6

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 6 of 30 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm ) Pinout CY7C1471BV25 (2M x 36) 234 56 7 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C CEN A CE2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ D DQ D A V DDQ B[...]

  • Page 7

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 7 of 30 Pin Configurations (continued) A B C D E F G H J K L M N P R T U V W 12 3 45 6 7 8 9 1 1 10 DQg DQg DQg DQg DQg DQg DQg DQg DQc DQc DQc DQc NC DQPg DQh DQh DQh DQh DQd DQd DQd DQd DQPd DQPc DQc DQc DQc DQc NC DQh DQh DQh DQh DQPh DQd DQd DQd DQd DQb DQb DQb DQb DQb [...]

  • Page 8

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 8 of 30 T able 1. Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address Inpu t s Used to Select One of the Address Locations . Samp led at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter . BW A , BW B , BW C , BW D , BW E , BW[...]

  • Page 9

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 9 of 30 Functional Overview The CY7C1471BV25, CY7C1473BV25 , and CY7C1475BV25 are synchronous flow through burst SRAMs designed specifi- cally to eliminate wait states during write read transitions. All synchronous inputs pass through input registers controlled by the risin[...]

  • Page 10

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 10 of 30 included to greatly simplify re ad/modify/write seque nces, which can be reduced to simple byte write operations. Because the CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 are common IO devices, data must not be driven into the device while the outputs are active. T[...]

  • Page 11

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 1 1 of 30 T a ble 4. T ruth T able The truth table for CY7C1471BV25, CY7C1473BV25, and CY7C1475 BV25 follows. [1, 2, 3, 4, 5, 6, 7] Operation Ad dress Used CE 1 CE 2 CE 3 ZZ ADV/LD WE BW X OE CEN CLK DQ Deselect Cycl e None H X X L L X X X L L->H T ri-S tate Deselect Cyc[...]

  • Page 12

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 12 of 30 T able 5. T ru th T able for Re ad/Write The read-write truth table for CY7C1471BV25 follows. [1, 2, 8] Function WE BW A BW B BW C BW D R e a d HXXXX Write No bytes written L H H H H Write Byte A – (DQ A and DQP A ) L L HHH Write Byte B – (DQ B and DQP B )L H L[...]

  • Page 13

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 13 of 30 IEEE 1 149.1 Serial Boun dary Scan (JT AG) The CY7C1471BV25, CY7C1473BV25 , and CY7C1475BV25 incorporate a serial bounda ry sca n T est Access Port (T AP) . This port operates in accordance with IEEE S tandard 1 149.1-1990 but does not have the set of functions req[...]

  • Page 14

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 14 of 30 T AP Registers Registers are connected between the TDI and TDO balls and enable the scanning of data into and out of the SRAM test circuitry . Only on e register is selectable at a time through the instruction register . Data is serially loaded into the TDI bal l o[...]

  • Page 15

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 15 of 30 no guarantee as to the value that is captured. Repeatable results may not be possible . T o gua rantee that the boundary scan register captures th e correct signal value, make certain that the SRAM signal is stabi- lized long enough to meet the T AP controller ’s[...]

  • Page 16

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 16 of 30 2.5V T AP AC T est Conditions Input pulse levels .................... .............. ........... .... V SS to 2.5V Input rise and fall time ............... ...................... ................ 1 ns Input timing reference levels........... .............. ........[...]

  • Page 17

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 17 of 30 T able 8. Iden tification Reg ister Definitions Instruction Field CY7C1471BV25 (2MX36) CY7C1473BV25 (4MX18) CY7C1475BV25 (1MX72) Description Revision Number (31:29) 000 000 000 Describes the version number Device Depth (28:2 4) 0101 1 0101 1 0101 1 Reserved for int[...]

  • Page 18

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 18 of 30 T able 1 1. Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ba ll ID Bit # 165-B all ID 1 C 12 1 R 34 1 J 1 1 6 1 B 7 2D 1 2 2 P 2 4 2 K 1 0 6 2 B 6 3E 1 2 3 R 4 4 3 J 1 0 6 3 A 6 4D 2 2 4 P 6 4 4 H 1 1 6 4 B 5 5E 2 2 5 R 6 4 5 G 1 [...]

  • Page 19

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 19 of 30 T a ble 13. Boun dary Scan Exit Orde r (1M x 72 ) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ba ll ID Bit # 209-B all ID 1 A1 29 T1 57 U10 85 B1 1 2A 2 3 0 T 2 5 8 T 1 1 8 6 B 1 0 3B 1 3 1 U 1 5 9 T 1 0 8 7 A 1 1 4B 2 3 2 U 2 6 0 R 1 1 8 8 A 1 0 5 C1 33 V1 61 R1[...]

  • Page 20

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 20 of 30 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature ..................... ............ –65 ° C to +150 ° C Ambient T emperat ure with Power Applied .......... .......[...]

  • Page 21

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 21 of 30 Cap acit ance T ested ini tially and after any design or process change that may affect these parameters. Parameter Description T est Condit ions 100 TQFP Max 165 FBGA Max 209 FBGA Max Unit C ADDRESS Address Input Capacit ance T A = 25 ° C, f = 1 MHz, V DD = 2.5V [...]

  • Page 22

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 22 of 30 Switching Characteristics Over the Operating R ange. Timing reference level is 1.25V when V DDQ = 2.5 V . T est conditions shown in (a) of “AC T est Loads and W aveforms” on page 21 unless otherwise noted. Parameter Descrip tion 133 MHz 100 MHz Unit Min Max Min[...]

  • Page 23

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 23 of 30 Switching W aveforms Figure 8 shows read-write timing waveform. [19, 20, 21] Figure 8. Read/W rite Timing WR I T E D(A 1) 123456789 CLK t CY C t CL t CH 10 CE t CE H t CE S WE CE N t C ENH t CE N S BW X AD V/ L D t AH t AS AD D R E S S A1 A2 A3 A4 A5 A6 A7 t DH t D[...]

  • Page 24

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 24 of 30 Figure 9 shows NOP , ST ALL and D ESELECT Cycles waveform. [19, 20, 22] Figure 9. NOP , ST ALL and DESELECT Cycles Switching W aveforms (continued) READ Q(A3) 456 789 1 0 A3 A4 A5 D(A4) 123 CLK CE WE CEN BW [A:D] ADV/LD ADDRESS DQ C OMMAND WRITE D(A4) STALL WRITE D[...]

  • Page 25

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 25 of 30 Figure 10 shows ZZ Mode timing waveform. [23, 24] Figure 10. ZZ Mode Timing Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZR E C A LL IN PU TS ( e x ce p t ZZ) DO N’T CA R E I DDZ Z t ZZI t RZ Z I Ou t p ut s (Q) Hig h- Z DES ELEC T or REA D O nly Note[...]

  • Page 26

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 26 of 30 Ordering Information Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www .cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram Part and Package T ype Operatin[...]

  • Page 27

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 27 of 30 Package Diagrams Figure 1 1. 100-Pin Thin Plastic Quad F latpack (14 x 20 x 1.4 mm), 51-85050 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3[...]

  • Page 28

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 28 of 30 Figure 12. 165-Ball F BGA (15 x 17 x 1 .4 mm), 51-85165 Package Diagrams (continued) A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.45±0.05(165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35 1.40 MAX. SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP [...]

  • Page 29

    CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 29 of 30 Figure 13. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167 Package Diagrams (continued) 51-85167-* * [+] Feedback[...]

  • Page 30

    Document #: 001-15013 Rev . *E Re vised February 29, 2008 Page 30 of 30 NoBL and No Bu s Latency are trademar ks of Cypress Semicondu ctor Co rporation. ZBT is a trademark of Integrat ed Device T echn ology , Inc. All products and company names me ntioned in this document may be the tr ademarks of their respe ctive hold er s. CY7C1471BV25 CY7C1473B[...]