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Cypress CY7C1462AV33 manual

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Table of contents for the manual

  • Page 1

    36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05353 Rev . *D Revised June 22, 2006 Features • Pin-comp atible and functionally equiv a le nt to ZBT™ ?[...]

  • Page 2

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 2 of 27 A0, A1, A C MODE BW a BW b WE CE1 CE2 CE3 OE READ LOGIC DQs DQP a DQP b D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTRO[...]

  • Page 3

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 3 of 27 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQa DQa V DDQ V SS DQa DQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQd DQd DQd V SS V DDQ A A CE 1 CE 2 BW a CE 3 V DD [...]

  • Page 4

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 4 of 27 Pin Configurations (continued) 23 4 567 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d NC/72M V DDQ BW d BW a CLK WE V SS V SS V SS V SS V DDQ V SS V DD V SS[...]

  • Page 5

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 5 of 27 Pin Definitions Pin Name I/O T ype Pin Descripti o n A0 A1 A Input- Synchronous Address Inp uts used to select one of the address locations . Sample d at the rising edge of the CLK. BW a BW b BW c BW d BW e BW f BW g BW h Input- Synchronous Byte Write Select Inputs[...]

  • Page 6

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 6 of 27 CLK Input- Clock Clock Inpu t . Used to capture all synchronous inpu ts to the devi ce. CLK is qualified with CEN . CLK is only recognized if CEN is active LOW. CE 1 Input- Synchronous Chip Enable 1 Input, active LOW . Sampled on the rising edge of CLK. Used in con[...]

  • Page 7

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 7 of 27 Functional Overview The CY7C1460A V33/CY7C1462A V33/CY7C1464A V33 are synchronous-pipel ined Burst NoBL SRAMs designed specifi- cally to eliminate wait states during Write/Read transitions. All synchronous inp uts pass through input registers controlled by the risi[...]

  • Page 8

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 8 of 27 counter is incremented. The correct BW (BW a,b,c,d,e,f,g,h for CY7C1464A V33, BW a,b,c,d for CY7C1460A V33 and BW a,b for CY7C1462A V33) inputs must be driven in each cycle of the burst write in order to writ e the correc t bytes of data. Sleep Mode The ZZ input pi[...]

  • Page 9

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 9 of 27 Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D) Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D) NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-S tate WRITE ABORT (Continue Burst) Next X L H X H X L L-H T ri-S tate IGNORE C[...]

  • Page 10

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 10 of 27 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1460A V33/CY7C1462A V33/CY7C1464A V33 incor- porates a serial boundary scan test access port (T AP). This part is fully compliant with 1 149.1 . The T AP operates using JEDEC-standard 3.3V or 2.5V I/O logi c level.[...]

  • Page 11

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 1 1 of 27 When the T AP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board -level serial test data path. Byp ass Register T o save time when serially shifting data throug[...]

  • Page 12

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 12 of 27 When this scan cell, called the “extest outpu t bus tri-state,” is latched into the prel oad register during the “Update-DR” state in the T AP controller , it will directly control the state of the output (Q-bus) pins, when t he EXTEST is entered as the cu[...]

  • Page 13

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 13 of 27 3.3V T AP AC T est Conditions Input pulse levels .......................... ........... ........... V SS to 3.3V Input rise and fall times ......... ..... ... ... ........... ... ........... ... ... 1 ns Input timing referenc e levels ................. ...........[...]

  • Page 14

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 14 of 27 Scan Register Sizes Register Name Bit Size (×36) B it Size (×18) Bit Size (×72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order (165-ball F BGA package) 89 89 - Boundary Scan Order (209-ball F BGA package) - - 138 Identification Codes Instruction[...]

  • Page 15

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 15 of 27 165-ball FBGA Boundary Scan Order [13] CY7C1460A V33 (1M x 36), CY7C1462A V33 (2M x 18) Bit# ball ID Bit# ball ID Bit# ball ID Bit# ball ID 1N 6 2 6 E 1 1 5 1 A 3 7 6 N 1 2N 7 2 7 D 1 1 5 2 A 2 7 7 N 2 3 10N 28 G10 53 B2 78 P1 4P 1 1 2 9 F 1 0 5 4 C 2 7 9 R 1 5 P8[...]

  • Page 16

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 16 of 27 209-ball BGA Boundary Scan Orde r [13, 1 4] CY7C14604V33 (512K x 72) Bit# Ball ID Bit# ball ID Bit# ball ID Bit# ball ID 1 W6 36 6F 71 6H 106 3K 2 V6 37 8K 72 6C 107 4K 3 U6 38 9 K 73 6B 108 6K 4 W7 39 10K 74 6A 109 2K 5 V7 4 0 1 1J 75 5A 1 10 2L 6 U7 41 10J 76 5B[...]

  • Page 17

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 17 of 27 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied ........... ............................ ...... [...]

  • Page 18

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 18 of 27 Note: 17. T ested initially and af ter any design or proc ess chan ges that may affect these p arameters. Cap acit ance [17] Parameter Description T est Conditions 100 TQFP Max. 165 FBGA Max. 209 FBGA Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD[...]

  • Page 19

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 19 of 27 Switching Characteristics Over the Operating Range [22, 23] Parameter Descriptio n –250 –200 –167 Unit Min. Max. Min. Max. Min. Max. t Power [18] V CC (typical) to the first access read or write 1 1 1 ms Clock t CYC Clock Cycle T ime 4.0 5.0 6.0 ns F MAX Max[...]

  • Page 20

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 20 of 27 Switching W aveforms Read/Write/T iming [24, 2 5, 26] Notes: 24. For this waveform ZZ is tied low . 25. When CE is LOW, CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW . When CE is HIG H,CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 26. Order of the Burst sequence is de[...]

  • Page 21

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 21 of 27 Notes: 27. The IGNORE CLOCK EDGE or ST ALL cycle (Clock 3) illustrated CEN being used to create a pause. A wr ite is not perform ed during this cycle. 28. Device must be deselected when entering ZZ mode. See cycle descr ipt ion table for all possible signal condit[...]

  • Page 22

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 22 of 27 Ordering Information Not all of the speed, package and temperature ranges are available. Please con tact your local sale s rep resentative or visit www .cypress.com for actual pro duct s offered. Spee d (MHz) Ordering Code Package Diagram Part and Package T ype Op[...]

  • Page 23

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 23 of 27 250 CY7C1460A V33-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1462A V33-250AXC CY7C1460A V33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1462A V33-250BZC CY7C1460A V33-250BZXC 51- 85165 165[...]

  • Page 24

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 24 of 27 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE[...]

  • Page 25

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 25 of 27 Package Diagrams (continued) A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.45±0.05(165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35 1.40 MAX. SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10.00 14.00 B C D E[...]

  • Page 26

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 26 of 27 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodie[...]

  • Page 27

    CY7C1460A V33 CY7C1462A V33 CY7C1464A V33 Document #: 38-05353 Rev . *D Page 27 of 27 Document History Page Document Title: CY7C1460A V33/CY7C1462A V33/CY7C1464A V33 36-Mbit (1M x 36/2M x 18 /512K x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05353 REV . ECN No. Issue Date Orig. of Change Description of Chang e ** 25491 1 See E[...]