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Cypress CY7C1024DV33 manual

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Table of contents for the manual

  • Page 1

    Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-08353 Rev . *C Revised November 6, 2008 CY7C1024DV33 3-Mbit (128K X 24) S tat ic RAM Features ■ High speed ❐ t AA = 10 ns ■ Low active po w e r ❐ I CC = 175 mA at 10 ns ■ Low CMOS standby power ❐ I SB2 = 25 mA ■[...]

  • Page 2

    CY7C1024DV33 Document Number: 001-08353 Rev . *C Page 2 of 9 Selection Guide Description –10 Unit Maximum Access T ime 10 ns Maximum Operating Current 175 mA Maximum CMOS S tandby Current 25 mA Pin Configuration Figure 1. 1 19-Ball PBGA To p View [1] 1234567 A N C AAAAA N C B NC A A CE 1 AA N C C I/O 12 NC CE 2 NC CE 3 NC I/O 0 D I/O 13 V DD V SS[...]

  • Page 3

    CY7C1024DV33 Document Number: 001-08353 Rev . *C Page 3 of 9 Maximum Ratings Exceeding maximum ratin gs may impair the useful life of the device. These user guidelines are not teste d. S torage T emperature ............. .................... –65 ° C to +150 ° C Ambient T e mperature wit h Power Applied ............ ....................... .....[...]

  • Page 4

    CY7C1024DV33 Document Number: 001-08353 Rev . *C Page 4 of 9 Figure 2. AC T est Loads an d Waveform [4] AC Switching Characteristics Over the Operatin g Range [5] Parameter Description –10 Unit Min Max Read Cycle t power [6] V CC (T ypical) to the First Access 100 μ s t RC Read Cycle Time 10 ns t AA Address to Data V alid 10 ns t OHA Data Hold f[...]

  • Page 5

    CY7C1024DV33 Document Number: 001-08353 Rev . *C Page 5 of 9 Write Cycle [9, 10] t WC Write Cycle T ime 10 ns t SCE CE active LOW to W rite End [3] 7n s t AW Address Setup to W rite End 7 ns t HA Address Hold from Write End 0 ns t SA Address Setup to W rite S tart 0 ns t PWE WE Pulse Wi dth 7 ns t SD Data Setup to W rite End 5.5 ns t HD Data Hold f[...]

  • Page 6

    CY7C1024DV33 Document Number: 001-08353 Rev . *C Page 6 of 9 Switching W aveforms Figure 3. Read Cycle No. 1 (Address Trans ition Con trolled) [13, 14] Figure 4. Read Cycle No. 2 (OE Controlled) [3, 14, 15] Figure 5. Write Cycle No. 1 (CE Controll ed) [3, 16, 17] PREVIOUS DATA VALID DATA VALID RC t AA t OHA t RC ADDRESS DATA OUT 50% 50% DA T A V AL[...]

  • Page 7

    CY7C1024DV33 Document Number: 001-08353 Rev . *C Page 7 of 9 Figure 6. W rite Cycle No. 2 (WE Con trolled, OE HIGH Du ring Write) [3, 16, 17] Figure 7. Write Cycle No. 3 (WE Cont ro lled , OE LOW) [3, 17] T ruth T able CE 1 CE 2 CE 3 OE WE I/O 0 – I/O 23 Mode Power H XXXX H i g h Z P o w e r D o w n S t a n d b y ( I SB ) X L X X X High Z Power D[...]

  • Page 8

    CY7C1024DV33 Document Number: 001-08353 Rev . *C Page 8 of 9 Ordering Information Spee d (ns) Ordering Code Package Name Package T yp e Operating Range 10 CY7C1024DV33-1 0BGXI 51-851 15 1 19-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Free) Industrial Package Diagram Figure 8. 1 19-Ball PBGA (14 x 22 x 2.4 mm) 51-851 15-*B [+] Feedback [+] [...]

  • Page 9

    CY7C1024DV33 © Cypress Semico nductor Corporation, 2006-2008. The inform ation contained h erein is subject to change without notice. Cypress S emiconductor Corpora tion as sume s no re sponsi bility for t he use of any circuitry othe r than circuitry embodied in a Cy press product. Nor does it convey or imply any lic ense under patent or ot her r[...]