English dropdown-ico

Cypress CY14B104M manual

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

Go to page of

Similar user manuals

A good user manual

The rules should oblige the seller to give the purchaser an operating instrucion of Cypress CY14B104M, along with an item. The lack of an instruction or false information given to customer shall constitute grounds to apply for a complaint because of nonconformity of goods with the contract. In accordance with the law, a customer can receive an instruction in non-paper form; lately graphic and electronic forms of the manuals, as well as instructional videos have been majorly used. A necessary precondition for this is the unmistakable, legible character of an instruction.

What is an instruction?

The term originates from the Latin word „instructio”, which means organizing. Therefore, in an instruction of Cypress CY14B104M one could find a process description. An instruction's purpose is to teach, to ease the start-up and an item's use or performance of certain activities. An instruction is a compilation of information about an item/a service, it is a clue.

Unfortunately, only a few customers devote their time to read an instruction of Cypress CY14B104M. A good user manual introduces us to a number of additional functionalities of the purchased item, and also helps us to avoid the formation of most of the defects.

What should a perfect user manual contain?

First and foremost, an user manual of Cypress CY14B104M should contain:
- informations concerning technical data of Cypress CY14B104M
- name of the manufacturer and a year of construction of the Cypress CY14B104M item
- rules of operation, control and maintenance of the Cypress CY14B104M item
- safety signs and mark certificates which confirm compatibility with appropriate standards

Why don't we read the manuals?

Usually it results from the lack of time and certainty about functionalities of purchased items. Unfortunately, networking and start-up of Cypress CY14B104M alone are not enough. An instruction contains a number of clues concerning respective functionalities, safety rules, maintenance methods (what means should be used), eventual defects of Cypress CY14B104M, and methods of problem resolution. Eventually, when one still can't find the answer to his problems, he will be directed to the Cypress service. Lately animated manuals and instructional videos are quite popular among customers. These kinds of user manuals are effective; they assure that a customer will familiarize himself with the whole material, and won't skip complicated, technical information of Cypress CY14B104M.

Why one should read the manuals?

It is mostly in the manuals where we will find the details concerning construction and possibility of the Cypress CY14B104M item, and its use of respective accessory, as well as information concerning all the functions and facilities.

After a successful purchase of an item one should find a moment and get to know with every part of an instruction. Currently the manuals are carefully prearranged and translated, so they could be fully understood by its users. The manuals will serve as an informational aid.

Table of contents for the manual

  • Page 1

    PRELIMINARY CY14B104K, CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real T ime Clock Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-07103 Rev . *K Revised January 29, 2009 Features ■ 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14B104K) o[...]

  • Page 2

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 2 of 31 Pinout s Figure 1. Pi n Diagram - 44-P In and 54 -Pin TSOP II T able 1. Pin Definitions Pin Name I/O T ype Description A 0 – A 18 Input Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration . A 0 – A 17 Address Inputs Used to Select [...]

  • Page 3

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 3 of 31 Device Operation The CY14B104K/CY14B104M nvSRAM is made u p of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile Qua ntumT rap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is tr[...]

  • Page 4

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 4 of 31 power-on-recall, the MPU must be active or the WE held inactive until the MPU comes out of reset. T o reduce unnecessary nonvo latile STOREs, AutoS tore and Hardware STORE operations are ignored unless at least one write operation has taken place since th e most recent STO[...]

  • Page 5

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 5 of 31 Preventing AutoStore The AutoS tore function is disabled by initiati ng an AutoS tore disable sequence. A sequence of read ope rations is performed in a manner si milar to the Software STORE initiation. T o initiate the AutoS tore disable sequence, the followi ng sequence [...]

  • Page 6

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 6 of 31 Dat a Protection The CY14B104K/CY14B104M prot ects data from corruption during low voltage conditio ns by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected w hen V CC is less than V SWITCH . If the CY14B104K/ CY14B104M is[...]

  • Page 7

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 7 of 31 must be set to ‘1’. This turns off the oscillator circuit, extending the battery life. If the OSCEN bit goes from disabled to ena bled, it takes approximately one second (two seconds maximum) for the oscillator to start. While system power is off, If t he voltage on th[...]

  • Page 8

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 8 of 31 New time out values are written b y setting the watchd og write bit to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out value bits D5-D0 are enabled to modify the time out value . When WDW is ‘1’, write s to bits D5-D0 are ignored. The WDW function[...]

  • Page 9

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 9 of 31 Figure 4. RTC Rec ommended Component Co nfiguration Figure 5. Interrupt Block Diagram Recommended V alues Y 1 = 32.768 KHz (6 pF) C 1 = 21 pF C 2 = 21 pF X 1 X 2 Y1 C2 C1 Note: The recommende d values for C1 and C2 incl ude board trace capacit ance. W atchdog T imer Power [...]

  • Page 10

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 10 of 31 T able 4. RTC Register Map [8] Register BCD Format Data [9] Function/Range CY14B104K CY14B104M D7 D6 D5 D4 D3 D2 D1 D0 0x7FFFF 0x3F FFF 10s Y ears Y ears Y ears: 00–99 0x7FFFE 0x3FFFE 0 0 0 10s Months Months Months: 01–12 0x7FFFD 0x3FFFD 0 0 10s Da y of Month D ay Of [...]

  • Page 11

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 1 1 of 31 T able 5. Register Map Detail Register Description CY14B104K CY14B104M 0x7FFFF 0x3FFFF Time Keeping - Y ears D7 D6 D5 D4 D3 D2 D1 D0 10s Y ea rs Y ears Contains the lower two BCD digits of the year . Lowe r nibble (four bits) contains the value for years; upper nibble (f[...]

  • Page 12

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 12 of 31 Register Description CY14B104K CY14B104M 0x7FFF8 0x3FFF8 Calibration/Control D7 D6 D5 D4 D3 D2 D1 D0 OSCEN 0 Calibration Sign Calibration OSCEN Oscillato r Enable. When set to 1, the oscillator is stopped. Whe n set to 0, the oscillator runs. Disabling the oscillato r sav[...]

  • Page 13

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 13 of 31 Register Description CY14B104K CY14B104M 0x7FFF4 0x3FFF4 Alarm - Hours D7 D6 D5 D4 D3 D2 D1 D0 M 10s Alarm Hours Alarm Hours Contains the alarm value for the hours and the mask bi t to select or deselect the hours value. M Match. When this bit is set to 0, the hours value[...]

  • Page 14

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 14 of 31 Maximum Ratin gs Exceeding maximum ratings may impair the useful life of the device. These user guid elines are not tested. S torage T emperature ................ .............. ... –65 ° C to +150 ° C Maximum Accumulated Storage T ime At 150 ° C Ambient T emperature[...]

  • Page 15

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 15 of 31 AC T est Conditions Input Pulse Levels ..................... ........... .............. ...... 0V to 3V Input Rise and Fall T imes (10% - 90%) ..... ................. .. < 3 ns Input and Output T iming Reference Levels .................... 1.5V Dat a Retention and Endu[...]

  • Page 16

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 16 of 31 T able 6. RTC Characteristics Parameters Description T est Conditions Min Ty p Max Units I BAK [15] RTC Backup Current Room T emperature (25 o C) 300 nA Hot T emperature (85 o C) 450 nA V RTC ba t RTC Battery Pin V oltage 1.8 3.0 3.3 V V RTC ca p RTC Capacitor Pin V o lta[...]

  • Page 17

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 17 of 31 AC Switching Characteristics Parameters Description 20 ns 25 ns 45 ns Unit Cypress Parameters Alt Parameters Min Max Min Max Min Max SRAM Read Cycle t ACE t ACS Chip Enable Access T ime 20 25 45 ns t RC [16] t RC Read Cycle T ime 20 25 45 ns t AA [17] t AA Address Access [...]

  • Page 18

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 18 of 31 Switching W aveforms Figure 8. SRAM Read Cycle 2: CE Controlled [3 , 16, 20] Figure 9. SRAM W rite Cycle 1: WE Controlled [3, 19, 20, 21] Ad dr es s Val id Ad dr e ss Data Output Ou tput D ata Va lid Stand by Acti ve High Impedance CE OE BHE, BLE I CC t HZCE t RC t ACE t [...]

  • Page 19

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 19 of 31 Switching W aveforms Figure 10. SRAM Write Cycle 2: CE Con trolled [3, 19, 20, 21] Figure 1 1 . SRAM Write Cycle 3: BHE and BLE Controlled [6, 19, 20, 21, 22] D ata Ou tput Da ta Inpu t Inpu t D ata Va li d High Impedance Ad d res s Va lid Ad dr e ss t WC t SD t HD BHE , [...]

  • Page 20

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 20 of 31 AutoStore/Power Up RECALL Parameters Descrip tion 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t HRECALL [23] Power Up RECALL Dura tion 20 20 20 ms t STORE [24] ST ORE Cycle Duration 8 8 8 ms t DELA Y [25] T ime Allowed to Complete SRAM Cycle 20 25 25 ns V SWITCH Low V [...]

  • Page 21

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 21 of 31 Sof tware Controlled ST ORE and RECALL Cycle In the following table, the software controlled STORE and RECALL cycle p arameters are listed. [28, 29] Parameters Descrip tion 20 ns 25 ns 45 n s Unit Min Max Min Max Min Max t RC STORE/ RECALL I nitiation Cycle T ime 20 25 45[...]

  • Page 22

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 22 of 31 Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t DHSB HSB T o Output Active Time when write latch not set 20 25 25 ns t PHSB Hardware STORE Pulse Wid th 15 15 15 ns Switching W aveforms Figure 15. Hardware STORE Cycle [24] Figur[...]

  • Page 23

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 23 of 31 T ruth T able For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration CE WE OE Input s and Output s [2] Mode Power H X X High Z Deselect/Power down S tandby L H L Data Out (DQ 0 –DQ 7 ); Read Active L H H High Z Output Disabled Active L L X [...]

  • Page 24

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 24 of 31 Part Numbering Nomenclature Option: T - T ape & Reel Blank - S td. S peed: 20 - 20 ns 25 - 25 ns Data Bus: K - x8 + RT C M - x16 + RTC Density: 104 - 4 Mb V oltage: B - 3.0V Cypress CY14 B 104 K ZS P 20 X C T NVSRAM 14 - AutoStore + Software STORE + Hardware STORE T e[...]

  • Page 25

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 25 of 31 Ordering Information Spee d (ns) Ordering Code Pac kage Diagram Package T ype Operating Range 20 CY14B104K-ZS20XCT 51-85087 44-pin TSOPII Commercial CY14B104K-ZS20XC 51-85 087 44-pin TSOPII CY14B104K-ZS20XIT 51-85087 44-pin TSOPII Industrial CY14B104K-ZS20XI 51-85087 44-p[...]

  • Page 26

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 26 of 31 Package Diagrams Figure 17. 44-Pin TSOP II (51-85087) MAX MIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.016) 0.300 (0.012) EJECTOR PIN R G O K E A X S 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 1.194 ([...]

  • Page 27

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 27 of 31 Figure 18. 54-Pin TSOP II (51-85160) Package Diagrams (continued) 51-85160 ** [+] Feedback[...]

  • Page 28

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 28 of 31 Document History Page Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 Rev . ECN No. Submi ssion Date Orig. of Change Description of Change ** 43 1039 See ECN TUP New Data Sheet *A 489096 See ECN TUP Re[...]

  • Page 29

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 29 of 31 *F 1890926 See ECN vsutmp8/AE- SA Added Footnote 1, 2 and 3. Updated Logic Block d iagram Updated Pin definition T able Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8 ) package. Corrected typo in V IL min spec Changed the value of I CC3 from 25[...]

  • Page 30

    PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 30 of 31 *I 2519319 06/20/08 GVCH/PYRS Added 20 ns access speed in “Features” Added I CC1 for tRC=20 ns for b oth industrial and Commercial temperature Grad e Updated Thermal resistance values for 44-TSOP II and 54-TSOP II packages Added AC Switching Characteristi c s specs fo[...]

  • Page 31

    Document #: 001-07103 Rev . *K Revised January 29, 2009 Page 31 of 31 AutoS tore and Qu antumT rap are re gistered tradem arks of Cypress Semico nductor Corpora tion. All product s and compa ny names mentio ned in this document are th e trademarks of their resp ective holders. PRELIMINARY CY14B104K, CY14B104M © Cypress Semicondu ctor Corporati on,[...]