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Cypress CY14B101P manual

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  • Page 1

    PRELIMINARY CY14B101P 1 Mbit (128K x 8) Serial SPI nvSRAM with Real T ime Clock Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-44109 Rev . *B Revised February 2, 2009 Features ■ 1 Mbit NonV olatile SRAM ❐ Internally organize d as 128K x 8 ❐ STORE to QuantumTrap ® nonvol[...]

  • Page 2

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 2 of 32 Pinout s Figure 1. Pin Diagram - 16-Pin SOIC T able 1. Pin Definitions Pin Name I/O T ype Description CS Input Chip Select . Activates the device when pu lled LOW . Driving this pin HIGH puts the device in low power standby mode. SCK Input Serial Clock . Runs at speeds up to a maximu[...]

  • Page 3

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 3 of 32 Device Operation CY14B101P is a 1-Mbit nvSRAM memory with integrated RTC and SPI interface. All the read s an d writes to nvSRAM happen to the SRAM which gives nvSRAM the unique capability to handle infinite writes to th e memory . The data in SRAM is secured by a STORE sequence that[...]

  • Page 4

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 4 of 32 Figure 2. AutoStore Mode Sof tware S tore Operation Software S tor e allows the user to trigger a STORE operation through a special SPI instructi on. This operation i s initiated irrespective of whether a write has been p erformed since last nv operation. A STORE cycle t akes t STORE[...]

  • Page 5

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 5 of 32 master is the opcode. Following the opcode, an y addresses and data ar e then transf erred. The CS mu st go inac tive af ter an operation is complete and before a new opcode can be issued. The commonly used terms used in SPI protocol are given below: SPI Master The SPI Master device [...]

  • Page 6

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 6 of 32 SPI Modes CY14B101P device may be driven by a microcontroller with its SPI peripheral running in either of the followin g two modes: ■ SPI Mode 0 (CPOL=0, CPHA=0) ■ SPI Mode 3 (CPOL=1, CPHA=1) For both these modes, input data is latched in on the rising edge of Serial Clock (SCK)[...]

  • Page 7

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 7 of 32 SPI Operating Features Power Up Power up is defined as the co ndition when the power supply is turned on and V CC crosses Vswitch voltage. During this time, the Chip Select (CS ) must be enable d to follow the V CC voltage. Therefore, CS must be co nnected to V CC through a suitable [...]

  • Page 8

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 8 of 32 St atus Register The status register bits are listed in Ta b l e 3 . The status register consist s of Ready bi t (RDY ) and data protection bits BP1, BP0, WEN and WPEN. The RDY bit can be polled to check the Ready/Busy status while a nvSRAM STORE cycle is in progress. The status regi[...]

  • Page 9

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 9 of 32 Write Protection and Block Protection CY14B101P provides features for both software and hardware write protection using WRDI in struction and WP . Additionally , this device also provides block protection mechanism thro ugh BP0 and BP1 pins of the S tatus Register . The write enable [...]

  • Page 10

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 10 of 32 When WP pin is LOW and WPEN is set to “1”, any mod ifications to status re gister are disa bled. Therefore, the memory is protected by se tting the BP0 and BP1 bits and the WP pin inhibits any modification of the status register bits, providing ha rdware write prot ection . Note[...]

  • Page 11

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 1 1 of 32 READ RTC (RDRTC) Instruction Read RTC (RDRTC) instruction allows the user to read the contents of RT C registers. Reading the RTC registers through the serial output (SO) pin req uir es the following se quence: After the CS line is pulled LOW to sele ct a device, the RDRTC opcode i[...]

  • Page 12

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 12 of 32 WRITE RTC (W RTC) Instruction WRITE RTC (WRTC) instruction allows the user to modify the contents of R TC registers. T he WRTC instruct ion requires the WEN bit to be set to '1' before it can be issued. If W EN bit is '0', a WREN instruction needs to be issued be[...]

  • Page 13

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 13 of 32 bit is cleared on the positive ed ge of CS following the STORE instruction. Sof tware Reca ll (RECALL) When a RECALL instruction i s executed, CY14B101P p erforms a Software Recall operation. T o issue this instruction, the device must be write enabled (WEN = ‘1’). The instructi[...]

  • Page 14

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 14 of 32 Real Time Clock Operation nvTIME Operat ion The CY14B101P offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. The RTC registers occupy a separate address sp ace from nvSRAM and are accessible through Read RTC (RDRTC) and W rite RTC (WRTC)[...]

  • Page 15

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 15 of 32 The value of OSCF must be reset to ‘0’ when the time reg isters are writ ten for the first time. This in itializes t he st ate of th is bit which may have become set when the system was first powered on. T o reset OSCF , set the write bit “W” (in the Flags reg ister at 0x00)[...]

  • Page 16

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 16 of 32 . Power Monitor The CY14B101P provides a power manage ment scheme with power fail interrupt capability . It also controls the internal switch to backup power for the clock and protects the memory from low V CC access. The power monitor is base d on an internal b and gap reference ci[...]

  • Page 17

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 17 of 32 Accessing the Real T ime Clock through SPI CY14B101P uses 16 registers for Real Time Clock (RTC). These registers can be read out or written to by accessing all 16 registers in burst mode or accessing each registe r , one at a time. The RDRTC and WRTC instructions are used to access[...]

  • Page 18

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 18 of 32 T able 9. RTC Register Map [1, 2] Register BCD Format Data Function/Range D7 D6 D5 D4 D3 D2 D1 D0 0x0F 10s Y ears Y ears Y ears: 00–99 0x0E 0 0 0 10s Months Months Months: 01–12 0x0D 0 0 10s Day of Month Day Of Month Day of Month: 01–31 0x0C 0 0 0 0 0 Day of week Day of week: [...]

  • Page 19

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 19 of 32 T able 10. Register Ma p Detail 0x0F Time Keeping - Y ears D7 D6 D5 D4 D3 D2 D1 D0 10s Y ears Y ears Contains the lower two BCD digits of the year . Lower nibbl e (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble oper[...]

  • Page 20

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 20 of 32 0x07 W atchDog Timer D7 D6 D5 D4 D3 D2 D1 D0 WDS WDW WDT WDS W atchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer . Setting the bit to 0 has no effect. The bit is cleared automa ti cally after the watchdog time r is rese t. The WDS bit is write only . Read[...]

  • Page 21

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 21 of 32 0x02 Alarm - Seconds D7 D6 D5 D4 D3 D2 D1 D0 M 10s Alarm Seconds Alarm Seconds Contains the alarm value for the seconds and the mask bit to select or deselect the secon ds’ value . M Match. When this bit is set to 0, the seconds valu e is used in the alarm match. Setting this bit [...]

  • Page 22

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 22 of 32 Maximum Ratin gs Exceeding maximum ratings may shorten the useful life of the device. These user g uidelines are not tested. S t orage T emperature ............. ... .. ... ............ –65 ° C to +150 ° C Maximum Accumulated Storage T ime At 150 ° C Ambient T emperature.......[...]

  • Page 23

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 23 of 32 AC T est Conditions Input Pulse Levels .................. .............. .............. ...... 0V to 3V Input Rise and Fall T imes (10% - 90%) ...................... .. < 3 ns Input and Output T iming Reference Levels .................... 1.5V Dat a Retention and Endurance Parame[...]

  • Page 24

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 24 of 32 T able 12. RTC Characteristics Parameters Descrip tion T est Conditi o ns Min Ty p Max Units I BAK [7] RTC Backup Current Room T emperature (25 o C) 300 nA Hot T emperature (85 o C) 450 nA V RTC ba t RTC Battery Pin V oltage 1.8 3.0 3.3 V V RTC ca p RTC Capacitor Pin V oltage 1.5 3.[...]

  • Page 25

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 25 of 32 Figure 25. Sync hronous Data Timing (Mode 0) Figure 26. HOLD Timi ng HI-Z V ALID IN HI-Z CS SCK SI SO t CL t CH t CSS t SD t HD t CO t OH t CS t CSH t HZCS CS SCK HOLD SO t SH t HHZ t HLZ t HH t SH t HH ~ ~ ~ ~ [+] Feedback[...]

  • Page 26

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 26 of 32 AutoS tore or Power Up RECALL Parameters Descript ion CY14B101P Unit Min Max t FA [8] Power Up RECALL Duration 20 ms t STORE [9] STORE Cycle Duration 8 ms t DELA Y [10] T ime Allowed to Complete SRAM Cycle 25 ns V SWITCH Low V ol tage Trigger Level 2.65 V t VCCRISE VCC Rise T ime 15[...]

  • Page 27

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 27 of 32 Sof tware Controlled ST ORE/RECALL Cycles Parameter Description CY14B101P Unit Min Max t RECALL RECALL Duration 200 µs t SS [1 1, 13] Soft Sequence Processing T ime 100 µs Figure 28. Software ST ORE Cycle [13] Figure 29. Software RECALL Cycle [13] 0 0 1 1 1 1 0 0 CS SCK SI RWI Hi-[...]

  • Page 28

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 28 of 32 Hardware STORE Cycle Parameter Descr iption CY14B101P Unit Min Max t DHSB HSB T o Output Active Time when write latch not set 25 ns t PHSB Hardware STORE Pulse Wid th 15 ns Figure 30. Hardware STORE Cycle [9] ~ ~ ~ ~ HSB (IN) HSB (OUT) SO RWI HSB (IN) HSB (OUT) RWI t HHHD t STORE t [...]

  • Page 29

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 29 of 32 Ordering Information Ordering Code Package Diagram Package T ype Operating Range CY14B101P-SFXCT 51-85022 16 SOIC Commercial CY14B101P-SFXC 51-85022 16 SOIC CY14B101P-SFXIT 51-85022 16 SOIC Industrial CY14B101P-SFXI 51-85022 16 SOIC All the above part s are Pb - free. The above t ab[...]

  • Page 30

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 30 of 32 Package Diagrams Figure 31. 16-Pin (300 mil) SOIC Package (51-85022 ) 51-85022 *B [+] Feedback[...]

  • Page 31

    PRELIMINARY CY14B101P Document #: 001-44109 Rev . *B Page 31 of 32 Document History Page Document Title: CY14B101P 1 Mbit (128K x 8) Serial SPI nvSRAM with Real Time Clock Document Number: 00 1-441 09 REV . ECN NO. Submission Date Orig. of Change Description of Change ** 1939467 See ECN UNC/AESA New Data Sheet *A 2607447 1 1/21/2008 GSIN/ GVCH/AESA[...]

  • Page 32

    Document #: 001-44109 Rev . *B Revised February 2, 2009 Page 32 of 32 AutoS tore and Qu antumT rap are re gistered tradem arks of Cypress Semico nductor Corporati on. All product s and compa ny names mentio ned in this document are th e trad emark s of th eir resp ectiv e holders. PRELIMINARY CY14B101P © Cypress Semicondu ctor Corpor ation, 2008-2[...]