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Cypress Semiconductor CY25566 manual

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Table of contents for the manual

  • Page 1

    S pread S pectrum Clock Generator CY25566 Cypress Semiconductor Corpora tion • 3901 North First S treet • San Jose • CA 95134 • 408-943 -2600 Document #: 38-07429 Rev . *B Revised October 26, 20 05 Features • 25- to 200-MHz opera ting freq uen cy range • Wide range of spread selections (9) • Accepts clock or c rystal inputs • Provid[...]

  • Page 2

    CY25566 Document #: 38-07429 Rev . *B Page 2 of 9 General Description The Cypress CY25566 is a S pread S pectrum Clock Generator (SSCG) IC used for the purpose of reducin g electromagnetic interference (EMI) found in today’s high-speed digital electronic systems. The CY25566 uses a Cypress-proprietary phase-locked loop (PLL) and S pread Spectrum [...]

  • Page 3

    CY25566 Document #: 38-07429 Rev . *B Page 3 of 9 SSCLK1a/b SSCLK1a and SSCLK1b are spread spectrum clock outp uts used for the purpose of reducing EMI in digital systems. SSCLK1a and SSCLK1b ca n be connected in severa l different ways to provide flexibility in application desig ns. Each clock can drive separate nets with a capacitative load up to[...]

  • Page 4

    CY25566 Document #: 38-07429 Rev . *B Page 4 of 9 Modulation Rate S pread S pectrum clock generators utilize frequency modulation (FM) to distribute e nergy over a specific band of frequencies. The maximum freque ncy of the clock (Fmax) and minimum frequency of the clock (Fmin) determine this band of frequencies. The time required to transition fro[...]

  • Page 5

    CY25566 Document #: 38-07429 Rev . *B Page 5 of 9 T able 1. Frequency and Band width Selection Chart (Grou p 1)(Lo w Frequency (1x) Selection Ch art) 25–50 MHz (Low Range) XIN/CLK (MHz) S1 = M S0 = M S1 = M S0 = 0 S1 = 1 S0 = 0 S1 = 0 S0 = 0 S1 = 0 S0 = M 25–35 4.3 3.8 3.4 2.9 2.8 35–40 3.9 3.5 3.1 2.5 2.4 40–45 3.7 3.3 2.8 2.4 2.3 45–50 [...]

  • Page 6

    CY25566 Document #: 38-07429 Rev . *B Page 6 of 9 Application Schematic In this example, the CY255 66 is being driven by a 75-MHz reference clock. S0 = 0 and S1 = 0 are programmed to select a BW of 2.5%. (Refer to Ta b l e 1 and 2. ) S2 = 0 and S3 = 1 are programmed to select the Group 2 range. V DD = 3.30 VDC. SSCLK1a = 75 MHz @ 2.5% center spread[...]

  • Page 7

    CY25566 Document #: 38-07429 Rev . *B Page 7 of 9 Absolute Maximum Ratings [1, 2] Supply V oltage (V DD : ................. ........... .............. ............ .+6V Operating T emperature: ........ .............. .............. .. 0°C to 70°C S torage T emperature ... ... ... ... .............. .. ... ... –65°C to +150°C T able 4. DC Elec[...]

  • Page 8

    CY25566 Document #: 38-07429 Rev . *B Page 8 of 9 © Cypress Semico nductor Corpor ation, 2002. Th e information cont ained herein is subject to chan ge without not ice. Cypress Semico nductor Corporation assumes no respon sibility for the use of any circ uitry other than cir cuitry embodied i n a Cypress Semi conductor product. Nor does it convey [...]

  • Page 9

    CY25566 Document #: 38-07429 Rev . *B Page 9 of 9 Document Title:CY25566 Spread S pectrum Clock Generator Document Number: 38 -07429 Rev . ECN No. Issue Date Orig. of Change Description of Ch an ge ** 1 15771 07/01/02 OXC Ne w Data Sheet *A 122705 12/30/02 RBI Added power up require ments to maximum ratings information. *B 404070 See ECN RGL Minor [...]