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Analog Devices AD9843A manual

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Table of contents for the manual

  • Page 1

    REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analo[...]

  • Page 2

    –2– REV. 0 AD9843A–SPECIFICA TIONS GENERAL SPECIFICA TIONS Parameter Min Typ Max Unit TEMPERATURE RANGE Operating –20 +85 ° C Storage –65 +150 ° C POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver 2.7 3.6 V POWER CONSUMPTION Normal Operation (Specified Under Each Mode of Operation) Power-Down Modes Fast Recovery Mode 45 mW Standby 5 [...]

  • Page 3

    –3– REV. 0 AD9843A Parameter Min Typ Max Unit Notes P OWER CONSUMPTION 78 mW See TPC 1 for Power Curves MAXIMUM CLOCK RATE 20 MHz CDS Allowable CCD Reset Transient 1 500 mV See Input Waveform in Note 1 Max CCD Black Pixel Amplitude 1 200 mV Max Input Range Before Saturation 1 1.0 V p-p With 4 dB CDS Gain Max Input Range Before Saturation 1.5 V [...]

  • Page 4

    –4– REV. 0 AD9843A–SPECIFICA TIONS AUX1-MODE SPECIFICA TIONS Parameter Min Typ Max Unit POWER CONSUMPTION 60 mW MAXIMUM CLOCK RATE 20 MHz INPUT BUFFER Gain 0d B Max Input Range 1.0 V p-p VGA Max Output Range 2.0 V p-p Gain Control Resolution 1023 Steps Gain (Selected Using VGA Gain Register) Min Gain 0 dB Max Gain 36 dB Specifications subject[...]

  • Page 5

    AD9843A –5– REV. 0 TIMING SPECIFICA TIONS Parameter Symbol Min Typ Max Unit SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period t CONV 48 50 ns DATACLK High/Low Pulsewidth t ADC 20 25 ns SHP Pulsewidth t SHP 71 2 . 5 n s SHD Pulsewidth t SHD 71 2 . 5 n s CLPDM Pulsewidth t CDM 4 10 Pixels CLPOB Pulsewidth 1 t COB 2 20 Pixels SHP Rising Edge to SHD Fal[...]

  • Page 6

    AD9843A –6– REV. 0 PIN CONFIGURATION 36 35 34 33 32 31 30 29 28 27 26 25 13 14 1 5 16 17 1 8 19 20 21 22 2 3 24 1 2 3 4 5 6 7 8 9 10 11 12 4 8 47 4 6 45 44 39 3 8 37 4 3 42 41 40 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) AUX1IN AVSS AUX2IN AVDD2 BYP4 NC CCDIN (LSB) D0 D1 D2 D3 D4 NC = NO CONNECT D5 D6 D7 D8 BYP2 BYP1 AVDD1 AVSS AD9843A (MSB) D9 [...]

  • Page 7

    AD9843A –7– REV. 0 DEFINITIONS OF SPECIFICATIONS DIFFERENTIAL NONLINEARITY (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 10- b it resolution indicates that all 1024 codes, respectively, must be presen[...]

  • Page 8

    AD9843A –8– REV. 0 SAMPLE RATE – MHz 100 70 40 52 0 10 POWER DISSIPATION – mW 50 60 80 90 15 V DD = 3.3V V DD = 3.0V V DD = 2.7V TPC 1. Power vs. Sample Rate 0 1000 400 200 600 800 0 – 0.5 0.5 0.25 – 0.25 TPC 2. Typical DNL Performance – T ypical Performance Characteristics VGA GAIN CODE – LSB 4 2 0 0 1000 400 OUTPUT NOISE – LSB 2[...]

  • Page 9

    AD9843A –9– REV. 0 CCD-MODE AND AUX-MODE TIMING N – 10 N – 9N – 8N – 1N N N+1 N+2 N+9 N+10 t ID t ID t S1 t S2 t CP t INH t OD t H NOTES: 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES. SHP SHD DATACLK OUTPUT DATA CCD SIGNAL [...]

  • Page 10

    AD9843A –10– REV. 0 SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION Table I. Internal Register Map Register Address Data Bits Name A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Operation 0 0 0 Channel Select Power-Down Software OB Clamp 0 * 1 ** 0 * 0 * 0 * CCD/AUX Modes Reset On/Off VGA Gain 1 0 0 LSB MSB X Clamp Level 0 1 0 LSB MSB X X[...]

  • Page 11

    AD9843A –11– REV. 0 Table II. Operation Register Contents (Default Value x000) Optical Black Clamp Reset Power-Down Modes Channel Selection D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 * 0 * 0 * 1 ** 0 * 0 Enable Clamping 0 Normal 0 0 Normal Power 0 0 CCD-Mode 1 Disable Clamping 1 Reset All 0 1 Fast Recovery 0 1 AUX1-Mode Registers 1 0 Standby 1 0 AUX2-[...]

  • Page 12

    AD9843A –12– REV. 0 2dB TO 36dB CLPDM CCDIN 10 DIGITAL FILTERING CLPOB DC RESTORE INPUT OFFSET CLAMP OPTICAL BLACK CLAMP 0 TO 64 LSB 0.1  F DOUT 10-BIT ADC VGA 8-BIT DAC 8 VGA GAIN REGISTER 10 CDS – 2dB TO +10dB INTERNAL V REF 2V FULL SCALE CDS GAIN REGISTER 6 CLAMP LEVEL REGISTER Figure 11. CCD-Mode Block Diagram CIRCUIT DESCRIPTION AND O[...]

  • Page 13

    AD9843A –13– REV. 0 together with CLPOB or separately. The CLPDM pulse should be a minimum of four pixels wide. Variable Gain Amplifier The VGA stage provides a gain range of 2 dB to 36 dB, program- mable with 10-bit resolution through the serial digital interface. Combined with the typical 4 dB gain from the CDS stage, the total gain range for[...]

  • Page 14

    AD9843A –14– REV. 0 Table VIII. VGA Gain Register Used for AUX2-Mode MSB LSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (dB) X0 XXXXXXXXX0 . 0 10000000000 . 0 •• •• •• 11111111111 8 . 0 AUX1IN 0.1  F VGA GAIN REGISTER ADC VGA 10 5k  0.4V 0.4V INPUT SIGNAL ??V 0.8V 0.4V MIDSCALE 0dB TO 36dB Figure 14. AUX1 Circuit Configuration 0dB[...]

  • Page 15

    AD9843A –15– REV. 0 APPLICATIONS INFORMATION The AD9843A is a complete Analog Front End (AFE) product for digital still camera and camcorder applications. As shown in Figure 16, the CCD image (pixel) data is buffered and sent to the AD9843A analog input through a series input capacitor. The AD9843A performs the dc restoration, CDS, gain adjust-[...]

  • Page 16

    –16– C02194–0–10/00 (rev. 0) PRINTED IN U.S.A. AD9843A REV. 0 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) TOP VIEW (PINS DOWN) 1 12 13 25 24 36 37 48 0.019 (0.5) BSC 0.276 (7.00) BSC SQ 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) BSC SQ 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0  MIN[...]