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AMD CS5536 manual

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Table of contents for the manual

  • Page 1

    46959A - March 2009 1 AMD Geode™ LX Processor DDR2 BIOS Porting Guide 1.0 Scope The AMD Geode™ LX processo r has an integrated DDR memor y controller . Due to the concer ns over the av ailability and increasing cost of DDR, AMD ha s dev eloped a method f or operating DDR2 memor y with the processor’ s memor y controller . This application not[...]

  • Page 2

    2 AMD Geode™ LX Processor DDR2 BIOS P orting Gu ide 46959A - March 2009 Application Note 3.0 Solution The method for initializing DDR2 memor y on the p rocessor is to inser t a CPLD and q uick s witches in the address and BA signals. Figure 3-1 shows a b lock diagr am of this design. Dur ing initialization, the Enable signal opens (def ault) the [...]

  • Page 3

    AMD Geode™ LX Processor DDR2 BIOS P orting Gui de 3 46959A - March 2009 Application Note 3.2 CPLD Registers The CPLD contains two registers that indicate how it should asser t the BA[1 :0], A[12:0] signals and switch enable signals. • If accessing the registers via I2C , the register addresses are 80h and 81h. • If accessing with I/O, the add[...]

  • Page 4

    4 AMD Geode™ LX Processor DDR2 BIOS P orting Gu ide 46959A - March 2009 Application Note 3.3 Initialization Steps Some of the f ollowing steps may be optional, depending on the specific implementation. The reader is encouraged to hav e a copy of the JEDEC standard fo r DDR2 SDRAM, including the SPD byte definitions. The AMD Geode™ LX Processors[...]

  • Page 5

    AMD Geode™ LX Processor DDR2 BIOS P orting Gui de 5 46959A - March 2009 Application Note cally suppor table. As an e xample, consider the fo llow- ing DIMM characteristics: This is has a fundamental access time of 15ns, and therefore at CL=2, the minimum cycle time should be 7.5ns. This DIMM should be function normally at 133MHz, with a CL settin[...]

  • Page 6

    6 AMD Geode™ LX Processor DDR2 BIOS P orting Gu ide 46959A - March 2009 Application Note the CPLD are typically 0. Set SW_EN# hig h and BA[1:0] to 01b . Next, in MC_CF07_D A T A register , set MSR_ BA=01b and PROG_DRAM=1. Then clear PROG_DRAM. 6) Issue a LOAD MODE command to MR to reset the DLL. Regardless of whether the DLL is running, AMD does [...]

  • Page 7

    AMD Geode™ LX Processor DDR2 BIOS P orting Gui de 7 46959A - March 2009 Application Note 3.4 Other Info rmation and Restrictions The LX processor/DDR2 solu tion does not do DQS train- ing. The LX processor’ s memor y controller does not have the adjustability to make this wor thwhile, and the speeds are slow enough that this is not a problem. T[...]

  • Page 8

    © 2009 Advanced Micr o Devices, Inc. All r ights reser ved. The contents of this docu ment are pr ovid ed in connection with Adv anced Micro Devices , Inc. (“AMD”) products. AMD make s no representations or w arranties with respect to the accuracy or completeness of the contents of this publication and reser ves the right to make changes to s [...]