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Xilinx SP605 manuale d’uso - BKManuals
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Xilinx SP605 manuale d’uso

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Un buon manuale d’uso

Le regole impongono al rivenditore l'obbligo di fornire all'acquirente, insieme alle merci, il manuale d’uso Xilinx SP605. La mancanza del manuale d’uso o le informazioni errate fornite al consumatore sono la base di una denuncia in caso di inosservanza del dispositivo con il contratto. Secondo la legge, l’inclusione del manuale d’uso in una forma diversa da quella cartacea è permessa, che viene spesso utilizzato recentemente, includendo una forma grafica o elettronica Xilinx SP605 o video didattici per gli utenti. La condizione è il suo carattere leggibile e comprensibile.

Che cosa è il manuale d’uso?

La parola deriva dal latino "instructio", cioè organizzare. Così, il manuale d’uso Xilinx SP605 descrive le fasi del procedimento. Lo scopo del manuale d’uso è istruire, facilitare lo avviamento, l'uso di attrezzature o l’esecuzione di determinate azioni. Il manuale è una raccolta di informazioni sull'oggetto/servizio, un suggerimento.

Purtroppo, pochi utenti prendono il tempo di leggere il manuale d’uso, e un buono manuale non solo permette di conoscere una serie di funzionalità aggiuntive del dispositivo acquistato, ma anche evitare la maggioranza dei guasti.

Quindi cosa dovrebbe contenere il manuale perfetto?

Innanzitutto, il manuale d’uso Xilinx SP605 dovrebbe contenere:
- informazioni sui dati tecnici del dispositivo Xilinx SP605
- nome del fabbricante e anno di fabbricazione Xilinx SP605
- istruzioni per l'uso, la regolazione e la manutenzione delle attrezzature Xilinx SP605
- segnaletica di sicurezza e certificati che confermano la conformità con le norme pertinenti

Perché non leggiamo i manuali d’uso?

Generalmente questo è dovuto alla mancanza di tempo e certezza per quanto riguarda la funzionalità specifica delle attrezzature acquistate. Purtroppo, la connessione e l’avvio Xilinx SP605 non sono sufficienti. Questo manuale contiene una serie di linee guida per funzionalità specifiche, la sicurezza, metodi di manutenzione (anche i mezzi che dovrebbero essere usati), eventuali difetti Xilinx SP605 e modi per risolvere i problemi più comuni durante l'uso. Infine, il manuale contiene le coordinate del servizio Xilinx in assenza dell'efficacia delle soluzioni proposte. Attualmente, i manuali d’uso sotto forma di animazioni interessanti e video didattici che sono migliori che la brochure suscitano un interesse considerevole. Questo tipo di manuale permette all'utente di visualizzare tutto il video didattico senza saltare le specifiche e complicate descrizioni tecniche Xilinx SP605, come nel caso della versione cartacea.

Perché leggere il manuale d’uso?

Prima di tutto, contiene la risposta sulla struttura, le possibilità del dispositivo Xilinx SP605, l'uso di vari accessori ed una serie di informazioni per sfruttare totalmente tutte le caratteristiche e servizi.

Dopo l'acquisto di successo di attrezzature/dispositivo, prendere un momento per familiarizzare con tutte le parti del manuale d'uso Xilinx SP605. Attualmente, sono preparati con cura e tradotti per essere comprensibili non solo per gli utenti, ma per svolgere la loro funzione di base di informazioni e di aiuto.

Sommario del manuale d’uso

  • Pagina 1

    [Guide Subtitle] [optional] UG526 (v1.1.1 ) February 1, 2010 [ optional] SP605 Har d ware User Guide UG526 (v1.1.1 ) February 1, 2010[...]

  • Pagina 2

    SP605 Hard ware User Guide www .xilinx.com UG526 (v1.1.1) Februar y 1, 2010 Xilinx is disclosing this user gui de, manual, rel ease note, and/or sp ecification (the "Documentation") to y ou solely f or use in the dev elopment of designs to operate with Xilinx hardw are de vices. Y ou may not re produce, distrib ute, repub lish, downl oad,[...]

  • Pagina 3

    SP605 Hard ware User Guide www .xilinx.com 3 UG526 (v1.1.1) F ebrua ry 1, 2010 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

  • Pagina 4

    4 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 System ACE CF CompactFla sh Image Select DIP Switch S1 (Ac tive-High) . . . . . . . . . . 48 Mode DIP Switch SW1 (Acti ve-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 18. VITA 57.1 FMC LPC Connector . . . . . . . . . . . . . . . [...]

  • Pagina 5

    SP605 Hard ware User Guide www .xilinx.com 5 UG526 (v1.1.1) F ebrua ry 1, 2010 Pr eface About This Guide This manual accompan ies the Spar tan®-6 FP GA SP605 Evaluation Board and contains information about the SP605 hardwar e and software tools. Guide Contents This manual contains the following chapters: • Chapter 1, “SP605 Evaluation Board,?[...]

  • Pagina 6

    6 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Pref ace: About This Guide This guide describes the clocking r esources available in all Spartan-6 devices, including the DCMs and PLLs. • Spartan-6 FPGA Block RAM Res ourc es User Guide This guide describes the Spa rtan-6 device block RAM capa bilities. • Spartan-6 [...]

  • Pagina 7

    SP605 Hard ware User Guide www .xilinx.com 7 UG526 (v1.1.1) F ebrua ry 1, 2010 Chapter 1 SP605 Evaluation Board Overview The SP605 board enables har dware and software developers to cr eate or evaluate designs targeting the Spartan®-6 XC6SLX45T -3FGG484 FPGA. The SP605 provides boar d features common to many embedded pr ocessing systems. Some comm[...]

  • Pagina 8

    8 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board F eatures The SP605 board pr ovides the following features: • 1. Spartan-6 XC6SLX45T -3FGG48 4 FPGA • 2. 128 MB DDR3 Component Memory • 3. SPI x4 Flash • 4. Linear BPI Flash • 5. System ACE CF and CompactFlash Connector • 6. [...]

  • Pagina 9

    SP605 Hard ware User Guide www .xilinx.com 9 UG526 (v1.1.1) F ebrua ry 1, 2010 Overvie w • 17. Switches ♦ Power On/Of f slide switch ♦ System ACE CF Reset pushbutton ♦ System ACE CF bitstream image select DIP switch ♦ Mode DIP switch • 18. VIT A 57.1 FMC LPC C onnector • Configuration Options ♦ 3. SPI x4 Flash (both onboard and of f[...]

  • Pagina 10

    10 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board Related Xilinx Documents Prior to using the SP605 Evaluation Board, user s sh ou ld b e fa mil iar wit h Xi li nx res ource s. See the following locations for additional documentation on Xilinx tools and solutions: • ISE: www .xilinx.[...]

  • Pagina 11

    SP605 Hard ware User Guide www .xilinx.com 11 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription 4 Linear BPI Flash x16 Numonyx JS28F256P30T95 19 5 SystemACE CompactFlash Socket XCCACE-TQ144I Controller 20 6 USB JT AG Conn. (USB Mini-B) USB JT AG Download Circ uit 32 7 Clock Generation 200 MHz OSC, oscillator socket, SMA connectors 13, 14 a. 2[...]

  • Pagina 12

    12 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board 1. Spar tan-6 XC6SLX45T - 3 FGG4 8 4 FPGA A Xilinx Spartan-6 XC6SLX45T -3FGG484 FPGA is installed on the E mbedded Development Board . Ref erences See the Spartan-6 FPGA Dat a Sheet. [Ref 1] Configuration The SP605 supports configuratio[...]

  • Pagina 13

    SP605 Hard ware User Guide www .xilinx.com 13 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription I/O V oltage Rails There ar e four available banks on the XC6S LX45T -3FGG484 device. Banks 0, 1, and 2 are connected for 2.5V I/O. Bank 3 is used for the 1.5V DDR3 component memory interface of Spartan-6 FPGA ’s hard memory contr oller . The vol[...]

  • Pagina 14

    14 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board Ta b l e 1 - 5 shows the connections and pin numbers for the DDR3 Component Memory . T able 1- 4: FPGA On-Chip (OCT) T ermination Ex ternal Resistor Requirements U1 FPGA Pin FPGA Pin Number Board Connection f or OCT ZIO P3 No Connect RZ[...]

  • Pagina 15

    SP605 Hard ware User Guide www .xilinx.com 15 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription Ref erences See the Micron T e chnology , Inc. DDR3 SDRAM Specificat ion for mor e information. [Ref 12] Also, see the Sparta n-6 FPGA Memory Contr oller User Guide . [Ref 3] T1 MEM1_DQ9 C3 DQ9 U3 MEM1_DQ10 A2 DQ13 U1 MEM1_DQ1 1 D7 DQ8 W3 MEM1_DQ12[...]

  • Pagina 16

    16 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board 3 . SPI x4 Flash The Xilinx Spartan-6 FPGA hosts a SPI interfa ce which is visible to the Xilinx iMP ACT configuration tool. The SPI memory device oper ates at 3.0V ; t he Spartan-6 FPGA I/Os are 3.3V tolerant and provide electrically c[...]

  • Pagina 17

    SP605 Hard ware User Guide www .xilinx.com 17 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription Ref erences See the W inbond Serial Flash Memory Data Sheet for more information. [Ref 13] See the XPS Serial Peripheral Interface Data Sheet for more information. [Ref 4] T able 1- 6: SPI x4 Memory Connections U1 FPGA Pin Schematic Net Name SPI ME[...]

  • Pagina 18

    18 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board 4. Linear BPI Flash A Numonyx JS28F256P30 Linear Flas h memory (U25) on the SP605 ( Figur e 1-5 ) pr ovides 32 MB of non-volatile storage that can be us ed for configuration as well as softwar e storage. The Linear Flash is op erated in[...]

  • Pagina 19

    SP605 Hard ware User Guide www .xilinx.com 19 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription E22 FLASH_A16 55 A17 E20 FLASH_A17 18 A18 F22 F LASH_A18 17 A19 F21 F LASH_A19 16 A20 H19 FLASH_A20 1 1 A21 H18 FLASH_A21 10 A22 F20 F LASH_A22 9 A23 G19 FLASH_A23 26 A24 AA20 FPGA_D0_DIN_MISO_MISO1 34 D Q0 R13 FPGA_D1_MISO2 36 DQ1 T14 FPGA_D2_MISO[...]

  • Pagina 20

    20 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board FPGA Design Considerations f or the Configuration Flash The SP605 has the P30 BPI flash connected to th e FPGA dual use configuration pins and is not shared. It can be used to configur e the FPGA, and then controlled po st-configuration[...]

  • Pagina 21

    SP605 Hard ware User Guide www .xilinx.com 21 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription System ACE CF error and status LEDs indicate the operational state of the System ACE CF controller: • A blinking red err or LED indicates that no CompactFlash car d is pr esent • A solid red error LED indicate s an er ror condition during confi[...]

  • Pagina 22

    22 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board Ref erences See the System ACE CF pr oduct page for mor e information at http://www .xilinx.com/support/docum entation/sys tem_ace_solutions.htm . In addition, see the System ACE CompactFlash Solution Data Sheet . [Ref 5] 6. USB JT A G [...]

  • Pagina 23

    SP605 Hard ware User Guide www .xilinx.com 23 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription FMC bypass jumper J19 must be connected be tween pins 1-2 (bypass) to enable JT AG access to the FPGA on the basic SP605 boar d (w ithout FMC expansion modules installed), as shown in Figure 1-7 . When the VIT A 57.1 FMC LPC expansion connector is [...]

  • Pagina 24

    24 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board Oscillator Sock et (Single-Ended, 2.5V or 3 . 3 V) One populated single-ended clock socket (X2) is provided for user applications. The option of 2.5V or 3.3V power may be selected via a 0 ohm r esistor selection. The SP605 boar d is shi[...]

  • Pagina 25

    SP605 Hard ware User Guide www .xilinx.com 25 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription SMA Connectors (Diff erential) A high-pr ecision clock sign al can be pr ovided to the FPGA using dif fer ential clock signals through the onboar d 50-ohm SMA connectors J38 (N) and J4 1 (P). 8 . Multi-Gigabit T ransceiv ers (GTP MGTs) The SP605 pr[...]

  • Pagina 26

    26 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board X-Ref Target - Figure 1-10 Figure 1-10: GTP SMA Clock GND1 GND2 GND3 GND4 GND5 GND6 GND7 S IG GND1 GND2 GND3 GND4 GND5 GND6 GND7 S IG GND1 GND2 GND3 GND4 GND5 GND6 GND7 S IG GND1 GND2 GND3 GND4 GND5 GND6 GND7 S IG GND1 GND2 GND3 GND4 GN[...]

  • Pagina 27

    SP605 Hard ware User Guide www .xilinx.com 27 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription T able 1- 10: GTP SMA Clock Connections U1 FPGA Pin Schematic Net Name SMA Pin C9 SMA_RX_N J3 5.1 D9 SMA_RX_P J34.1 A8 SMA_TX_N J33.1 B8 SMA_TX_P J32.1 D1 1 SMA_REFCLK_N J36.1 C1 1 SMA_REFCLK_P J37.1[...]

  • Pagina 28

    28 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board 9. PCI Express Endpoint Connectivity The 1-lane PCIe edge connector pe rforms data transfe rs at the rate of 2.5 GT/s for a Gen1 application. The Spartan-6 F PGA GTP MGT is used for the multi-gigabit per second serial interface. The SP6[...]

  • Pagina 29

    SP605 Hard ware User Guide www .xilinx.com 29 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription Ref erences See the Spartan-6 FPGA GTP T ransceivers User Guide for mor e information. [Ref 6] Also, see the following websites for more information about the Spartan-6 FPGA Inte grated Endpoint Block for PCI Expr ess : • Product information, h t[...]

  • Pagina 30

    30 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board 10. SFP Module Connector The board contains a small form-fact or plugga ble (SFP) co nnector and cage assembly that accepts SFP modules. The SFP interface is co nnected to MGT Bank 123 on the FPGA. The SFP module se rial ID interface is[...]

  • Pagina 31

    SP605 Hard ware User Guide www .xilinx.com 31 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription 11. 10/100/1000 T ri-Speed Ether net PHY The SP605 uses the onboar d Marvell Alaska P H Y d e v i c e ( 8 8 E 1111 ) f o r E t h e r n e t communications at 10, 100, or 1000 Mb/s. The board supports a GMII interface from the FPGA to the PH Y . The [...]

  • Pagina 32

    32 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board Ref erences See the Marvell Alaska Gigabit Ethernet T ransceivers product page for more information. [Ref 17] Also, see the LogiCORE™ IP T ri-Mode Et hernet MAC User Guide . [Ref 7] U22 PHY_RXD7 120 RXD7 AB7 PHY_TXC_GTPCLK 14 GTXCLK L[...]

  • Pagina 33

    SP605 Hard ware User Guide www .xilinx.com 33 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription 12. USB-to-U AR T Bridge The SP605 contains a Silicon Labs CP2103G M USB-to-UAR T bridge device (U4) which allows connection to a host computer with a US B cable. The USB cable is supplied in this evaluation kit (T ype A end to host computer , T yp[...]

  • Pagina 34

    34 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board 1 3 . D VI CODEC A DVI connector (P3) is pre sent on the boar d to support an external video monitor . The DVI circuitry utilizes a Chr ontel CH7301C (U31) capable of 1600 X 1200 resolution with 24- bit color . The video interface chip [...]

  • Pagina 35

    SP605 Hard ware User Guide www .xilinx.com 35 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription 14. IIC Bus The SP605 implements thr ee IIC bus interfaces at the FPGA. The MAIN IIC bus hosts four items: • FPGA U1 Bank 1 "M AIN" IIC inte rface • 8-Kb NV Memory U4 • FMC LPC connector J2 • 2-Pin External Access Header J45 The D[...]

  • Pagina 36

    36 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board 8 -Kb NV Memor y The SP605 hosts a 8-Kb ST Microelectroni cs M24C08-WDW6TP IIC parameter storage memory device (U4) . The IIC addr ess of U4 is 0b1010 100 , and U4 is not write prote cted (WP pin 7 is tied to GND). The IIC memory is sho[...]

  • Pagina 37

    SP605 Hard ware User Guide www .xilinx.com 37 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription Ref erences See the ST Micro M24C08 Data Sheet for more information. [Ref 18] In addition, see the Xilinx XPS IIC Bus Interface Data Sheet . [Ref 8] T able 1- 20: IIC Memory Conne ctions U1 FPGA Pin Schematic Netname IIC Memory U4 Pin Number Pin Na[...]

  • Pagina 38

    38 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board 15. Status LEDs Ta b l e 1 - 2 1 defines the status LEDs. T able 1-21: Status LEDs Reference Designator Signal Name Color Label Description DS1 FMC_PWR_GOOD_FLASH_RST_B Green FMC PWR GD FMC Power Good DS2 FPGA_DONE Green DONE FPGA DONE [...]

  • Pagina 39

    SP605 Hard ware User Guide www .xilinx.com 39 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription Ether net PHY Status LEDs The Ethernet PHY status LEDs (DS1 1-DS13) are mounted in right-angle plastic housings to make them visible on the connector end of the board whe n the SP605 board is installed into a PC motherboard. This cluster of six LED[...]

  • Pagina 40

    40 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board FPGA INIT and DONE LEDs The typical Xilinx FPGA power up and conf iguration status LEDs are pr esent on the SP605. The red INIT LED DS17 comes on momentarily after the FPGA powers up and during its internal power-on pr ocess. The DONE L[...]

  • Pagina 41

    SP605 Hard ware User Guide www .xilinx.com 41 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription 16. User I/O The SP605 provides the following user and general purpose I/O capabilities: • User LEDs • User Pushbutton Switches • User DIP Switch • User SIP Header • User SMA GPIO User LEDs The SP605 provides four active-H igh green LEDs [...]

  • Pagina 42

    42 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board User Pushb utton Switches The SP605 provides five active-High pushbutton switches: SW4, SW5, SW6, SW7 and SW8. The five pushbuttons all have the same topology as the sample shown in Figure 1- 16 . Four pushbuttons are assigned as GPIO, [...]

  • Pagina 43

    SP605 Hard ware User Guide www .xilinx.com 43 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription User DIP Switch The SP605 includes an active-High fo ur-pole DIP switch, as described in Figur e 1- 17 and Ta b l e 1 - 2 5 . Three poles (switches 1-3) ar e pulled up to 2.5V , and one pole (switch 4) is pulled up to 1.5V , when closed. X-Ref Targ[...]

  • Pagina 44

    44 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board User SIP Header The SP605 includes a 6-pin sing le-inline (SIP) male pin header (J55) for FPGA GPIO access. Four pins of J55 ar e wir ed to the FPGA thr oug h 200 ohm series r esistors and a level shift er , and the remaining two J55 pi[...]

  • Pagina 45

    SP605 Hard ware User Guide www .xilinx.com 45 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription User SMA GPIO The SP605 inclu des an pair of SMA connectors for GPIO as described in Figure 1- 19 and Ta b l e 1 - 2 7 . X-Ref Target - Figure 1-19 Figure 1-19: User SMA GPIO T able 1- 27: User SMA Connections U1 FPGA Pin Schematic Net Name GPIO SM[...]

  • Pagina 46

    46 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board 17. Switches The SP605 Evaluation board incl udes the follow ing switches: • Power On/Off Slide Switch SW2 • FPGA_PROG_B Pushbutton SW3 (Active-Low) • SYSACE_RESET_B Pushbu tton SW9 (Active-Low) • System ACE CF CompactFlash Imag[...]

  • Pagina 47

    SP605 Hard ware User Guide www .xilinx.com 47 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription FPGA_PROG_B Pushb utton SW 3 (Act iv e-Lo w) The SW3 switch ( Figure 1-21 ) grounds the FPGA PROG_B pin when pr essed. This action clears the FPGA. See the Sparta n-6 FPGA data sheet for mor e information on clearing the contents of the FPGA. SYSA [...]

  • Pagina 48

    48 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board System A CE CF CompactFlash Image Se lect DIP Switch S1 (Activ e-High) System ACE CF CompactF lash (CF) image select DIP switch S1, switches 1–3 ( Figure 1-23 ) select which CF resi dent bitstream image is downloaded to the FPGA. S1 s[...]

  • Pagina 49

    SP605 Hard ware User Guide www .xilinx.com 49 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription Mode DIP Switch SW1 (Activ e-High) DIP switch SW1 sets the FPGA mode as shown in Figure 1- 24 and T able 1-30, pa ge 55 . Ref erences For more information, r efer to the Spartan-6 FPGA Configuration User Guide [Ref 2] . See T able 1-30, page 55 for[...]

  • Pagina 50

    50 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board 1 8 . VIT A 57.1 FMC LPC Connector The SP605 implements the Low Pin Count (LPC, J2) connector option of the VIT A 57.1.1 FMC specification. The FMC standar d calls for two connector densities: a High Pin Count (HPC) and a Low Pin Count [...]

  • Pagina 51

    SP605 Hard ware User Guide www .xilinx.com 51 UG526 (v1.1.1) F ebrua ry 1, 2010 Detailed Des cription Ta b l e 1 - 2 8 shows the VIT A 57.1 FMC LPC connections. The connector pinout is in Appendix B, “VIT A 57.1 FMC LPC Connector Pinout.” T able 1-28: VIT A 57.1 FMC LPC Connections J63 FMC LPC Pin Schematic Net Name U1 FPGA Pin J63 FMC LPC Pin [...]

  • Pagina 52

    52 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board P ower Mana gement A C Adapter and 12V Input P o wer J a c k/Switch The SP605 is powe red fr om a 12V sour ce that is connect ed throu gh a 6-pin (2X3) right angle Mini-Fit type connector J18. The AC-to-DC power supply included in the k[...]

  • Pagina 53

    SP605 Hard ware User Guide www .xilinx.com 53 UG526 (v1.1.1) F ebrua ry 1, 2010 P o wer Management Onboard P ow er Regulation Figure 1- 25 shows the SP605 onboar d power supply architecture. The SP605 uses T exas Instruments power contr ollers for primary core power control and monitoring. X-Ref Target - Figure 1-25 Figure 1-25: Onboar d P ower Reg[...]

  • Pagina 54

    54 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board V oltage and current monitoring and contr ol ar e available for selected power rails through T exas Instruments' Fusion Digital Power™ graphical u ser interface (GUI) . Both onboard TI power contr ollers ar e wire d to the same P[...]

  • Pagina 55

    SP605 Hard ware User Guide www .xilinx.com 55 UG526 (v1.1.1) F ebrua ry 1, 2010 Configuration Options Configuration Options The FPGA on the SP605 Evaluation Boar d can be configured by the following methods: • “3. SPI x4 Flash,” page 16 • “4. Linear BPI Flash,” page 18 • “5. System ACE CF and CompactFlash Connector ,” page 20 • [...]

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    56 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Chapter 1: SP605 Evaluation Board[...]

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    SP605 Hard ware User Guide www .xilinx.com 57 UG526 (v1.1.1) F ebrua ry 1, 2010 Appendix A Default Jumper and Switch Settings Ta b l e A - 1 shows the default switch settings and Ta b l e A - 2 , p a g e 5 8 shows the default jumper settings for the SP605. Ta b l e A - 1 : Def ault Switch Sett ings REFDES Function/T ype Default SW2 Board power slid[...]

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    58 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Appendix A: Default Jumper and Switch Settings Ta b l e A - 2 : Def ault Jumper Settin gs Jum pe r REFDES Function Default FMC JT AG Bypass J19 exclude FMC LPC connector J2 Jump 1-2 SFP Module J22 SFP Full BW Jump 1-2 J44 SFP Enabled Jump 1-2 SPI Memo ry Select J46 SPI [...]

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    SP605 Hard ware User Guide www .xilinx.com 59 UG526 (v1.1.1) F ebrua ry 1, 2010 Appendix B VIT A 57.1 FMC LPC Connector Pinout Figure B-1 shows the pinout of the FMC LPC co nnector . Pins marked NC are not connected. X-Ref Target - Figure B-1 Figure B-1: FMC LPC Connector Pinout KJ H G F E D C B A 1 N C N C V R E F _ A_ M2 C G ND NC NC P G _C 2M G [...]

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    60 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Appendix B: VIT A 57.1 FMC LPC Connector Pinout[...]

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    SP605 Hard ware User Guide www .xilinx.com 61 UG526 (v1.1.1) F ebrua ry 1, 2010 Appendix C SP605 Master UCF The UCF template is pr ovided for designs that tar get the SP605. Net names pr ovided in the constraints below corr elate with net names on the SP605 r ev . C schematic. On identi fying the appropriate pins , the net names below should be r e[...]

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    62 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Appendix C: SP605 Mast er UCF NET "FLASH_WE_B" LOC = "R20"; ## 14 on U25 NET "FLASH_OE_B" LOC = "P22"; ## 32 on U25 NET "FLASH_CE_B" LOC = "P21"; ## 30 on U25 NET "FLASH_ADV_B" LOC = "T19"; [...]

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    SP605 Hard ware User Guide www .xilinx.com 63 UG526 (v1.1.1) F ebrua ry 1, 2010 NET "FPGA_CMP_CS_B" LOC = "V18"; ## 4 on J3 NET "FPGA_CMP_MOSI" LOC = "W18"; ## 2 on J3 ## NET "FPGA_D0_DIN_MISO_MISO1" LOC = "AA20"; ## this pin is part of the FLASH_nn group ## NET "FPGA_D1_MISO2" L[...]

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    64 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Appendix C: SP605 Mast er UCF NET "MEM1_LDQS_N" LOC = "N1"; ## G3 on U42 NET "MEM1_LDQS_P" LOC = "N3"; ## F3 on U42 NET "MEM1_ODT" LOC = "L6"; ## K1 on U42 NET "MEM1_RAS_B" LOC = "M5"; ## J3[...]

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    SP605 Hard ware User Guide www .xilinx.com 65 UG526 (v1.1.1) F ebrua ry 1, 2010 ## NET "SYSCLK_N" LOC = "K22"; ## NET "SYSCLK_P" LOC = "K21"; ## ## NET "USB_1_CTS" LOC = "F18"; ## NET "USB_1_RTS" LOC = "F19"; ## NET "USB_1_RX" LOC = "B21"; ## NET &qu[...]

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    66 www .xilinx.com SP6 05 Hard ware User Guide UG526 (v1.1.1) Februar y 1, 2010 Appendix C: SP605 Mast er UCF[...]

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    SP605 Hard ware User Guide www .xilinx.com 67 UG526 (v1.1.1) F ebrua ry 1, 2010 Appendix D Refer ences This appendix provides r eferences to docume ntation supporting Spartan-6 FPGAs, tools, and IP . For additional information, see www .xilinx. com/support/documentation/index.htm . Xilinx documents supporting the SP605 Evaluati on Boar d: 1. DS162 [...]