Quatech MPAP-100 manuale d’uso

MPAP-100 RS-232 PCMCIA SYNCHRONOUS ADAPTER for PCMCIA Card Standard compatible machines User's Manual QUATECH, INC. TEL: (330) 655-9000 5675 Hudson Industrial Parkway FAX: (330) 655-9010 Hudson, Ohio 44236 www.quatech.com Quatech MPAP-100 User's Manual 1[...]

WARRANTY INFORMATION Quatech Inc. warrants the MPAP-100 to be free of defects for one (1) year from the date of purchase. Quatech Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from impro[...]

Copyright 2001 Quatech, Inc. NOTICE The information contained in this document is protected by copyright, and cannot be reproduced in any form without the written consent of Quatech, Inc. Likewise, any software programs that might accompany this document are protected by copyright and can be used only in accordance with any license agreement(s) bet[...]

38 10.2.2 Receive FIFO ............................................. 37 10.2.1 Transmit FIFO ........................................... 37 10.2 Accessin g the FIFOs .......................................... 37 10.1 Enablin g and disablin g the FIFOs ............................. 37 10 FIFO O p eration .............................................[...]

64 22.3.3 Bad Parameters ........................................... 63 22.3.2 Insufficient Number Of Command Line Ar g uments ........ 63 22.3.1 Resources Not Available .................................. 63 22.3 OS/2 Client Driver ........................................... 63 22.2.3 Memor y ran g e exclusion .................................. 63 [...]

1 Introduction The Quatech MPAP-100 is a PCMCIA Type II (5 mm) card and is PCMCIA PC Card Standard Specification 2.1 compliant. It provides a single-channel RS-232 synchronous communication port. The base address and IRQ are configured through the PCMCIA hardware and software using utility programs provided by Quatech. There are no switches or jump[...]

2 Hardware Installation Hardware installation for the MPAP-100 is a very simple process: 1. Insert the MPAP-100 into a vacant PCMCIA Type II adapter socket. 2. If PCMCIA Card and Socket Services and a Quatech MPAP-100 Client Driver are installed, the MPAP-100 will be configured for use automatically. Under DOS, it is also possible to use the Quatec[...]

3 DOS / Windows 3.x Software Installation Two DOS configuration software programs are provided with the MPAP-100: a client driver and a card enabler. These programs are executed from DOS (before entering Windows) and allow operation of the MPAP-100 in both the DOS and Windows 3.x environments. Table 1 highlights the differences between these progra[...]

3.1 MPAP-100 Client Driver for DOS In order to use the MPAP-100 client driver, the system must be configured with Card and Socket Services software. Card and Socket Services software is not provided with the MPAP-100 but is available from Quatech. 3.1.1 DOS client driver installation The MPAP-100 client driver accepts between zero and eight sets of[...]

S# The PCMCIA socket into which the MPAP-100 must be inserted for this configuration to be used. This value is a decimal number ranging from 0 to 15. If this parameter is not used, the configuration can apply to any socket. B# The base I/O address of the MPAP-100. This number must be a three-digit hexadecimal value ending in 0. If this parameter is[...]

is helpful if the user allows Card Services to select resources instead of specifying them on the command line.[...]

3.2 DOS Client Driver examples Example: Attempt to configure an MPAP-100 inserted into any socket with a base address and IRQ automatically assigned by Card Services. DEVICE= C:MPAP-100MPAP1CL.SYS Example: Attempt to configure an MPAP-100 inserted into any socket with a base address of 300 hex and an IRQ assigned by Card Services. Software contro[...]

3.3 MPAP-100 Enabler for DOS For systems that are not using PCMCIA Card and Socket Services software, the MPAP-100 DOS enabler may be used to enable and configure the card. The enabler will operate on any DOS system using an Intel 82365SL (PCIC) or PCIC-compatible PCMCIA socket adapter including the Cirrus Logic CL-PD6710/6720, the VLSI VL82C146, a[...]

The enabler requires a single desired configuration to be provided on the command line. The card will not be configured if the desired configuration is not provided. The desired configuration must be enclosed in parentheses and it contains parameters separated using commas (no spaces). In the descriptions below, replace the '#' symbols wi[...]

If configuration is successful, the enabler will display a message showing the configuration on the screen. If the MPAP-100 is not successfully configured, then the information in this section along with the Troubleshooting chapter of this manual should be consulted to determine the cause of the problem. 3.3.4 Releasing a card's configuration [...]

3.4 DOS Enabler Examples Example: Configure the MPAP-100 in socket 0 with a base address of 300H and IRQ 5. Software control of SYNCA will be enabled . MPAP1EN.EXE (s0,b300,i5,c) Example: Configure the MPAP-100 in socket 1 with a base address of 300H and IRQ 3 using a configuration memory window at segment D800. MPAP1EN.EXE (s1,b300,i3,wd8) Example[...]

4 Windows 95/98 Installation Windows 95/98 maintains a registry of all known hardware installed in your computer. Inside this hardware registry Windows keeps track of all of your system resources, such as I/O locations, IRQ levels, and DMA channels. The "Add New Hardware Wizard" utility was designed to add new hardware and update this reg[...]

2. Click the "Next" button. Select the radio button for "Search for the best driver for your device." Click the "Next" button to continue. 3. On the next dialog, select the " CD-ROM drive" checkbox. Insert the Quatech COM CD (shipped with the card) into the CD-ROM drive. Click the "Next" button. 4. [...]

5. Windows will copy the INF file from the CD and display a final dialog indicating that the process is complete. Click the "Finish" button.[...]

4.2 Viewing Resources with Device Manager The following instructions provide step-by-step instructions on viewing resources used by the MPAP-100 in Windows 95/98 using the "Device Manager" utility. 1. Double click the "System" icon inside the Control Panel folder. This opens up the System Properties box. 2. Click the "Devic[...]

6. If changes to the automatic configuration are necessary for compatibility with existing programs, uncheck the "Use Automatic Settings" box and doubleclick on the Resource Type that needs to be changed. Caution should be used to avoid creating device conflicts with other hardware in the system. 4.3 Configuration Options If the "Use[...]

5 OS/2 Software Installation An OS/2 client driver is provided with the MPAP-100. This client driver works with OS/2's Card and Socket Services to allow operation of the MPAP-100 under OS/2. 5.1 System Requirements  OS/2 2.1 or later.  OS/2 PCMCIA Card and Socket Services support must be installed. See "Installing OS/2 PCMCIA suppor[...]

addr (required) The base I/O address of the MPAP-100. This number must be a three-digit hexadecimal value ending in 0. irq (required) The interrupt level (IRQ) of the MPAP-100. This decimal number must be one of the following values: 3, 4, 5, 7, 9, 10, 11, 12, 14, 15, or 0 if no IRQ is desired. C (optional) Drive SYNC input of SCC channel A with th[...]

5.3 OS/2 Client Driver Configuration Examples Example: Configure the MPAP-100 at base address 300 hex and IRQ 5. Configuration will fail if any of these resources are already in use. Only one MPAP-100 can be used. DEVICE=C:MPAP-100MPAP100.SYS (300,5) Example: Configure the MPAP-100 at base address 300 hex and IRQ 5. Configuration will fail if any[...]

If PCMCIA support was not selected when OS/2 was installed, add it by using the Selective Install facility in the System Setup folder. Full PCMCIA support is built into OS/2 Warp 3.0 and later. On OS/2 2.1 and 2.11, PCMCIA Card Services is built in, but you must add Socket Services separately.[...]

6 Using the MPAP-100 with Syncdrive Syncdrive is a synchronous communications software driver package designed to aid users of Quatech synchronous communication hardware in the development of their application software. Syncdrive is included free of charge with all Quatech MPA-series synchronous communication products. The MPAP-100 is backward-comp[...]

7 Addressing The MPAP-100 occupies a continuous 16-byte block of I/O addresses. For example, if the base address is set to 300 hex, then the MPAP-100 will occupy address locations 300 hex to 30F hex. If the computer in which the MPAP-100 is installed is running PCMCIA Card and Socket Services, the base address is set by the client driver. If PCMCIA[...]

8 Interrupts The MPAP-100 will operate using the interrupt level (IRQ) assigned by the PCMCIA system. Interrupts can come from the SCC, the external FIFOs or RS-232 test mode. The interrupt source is selected by bits 4 and 5 of the Configuration Register (see page 41). When using interrupts with the MPAP-100, the application must have an interrupt [...]

9 SCC General Information The Serial Communications Controller (SCC) is a dual channel, multi-protocol data communications peripheral. The MPAP-100 provides a single channel for communications, however, portions of the second channel can be utilized to support some special circumstances. The SCC can be configured to satisfy a wide variety of serial[...]

9.1 Accessing the registers The mode of communication desired is established and monitored through the bit values of the internal read and write registers. The register set of the SCC includes 16 write registers and 9 read registers. These registers only occupy four address locations, which start at the MPAP-100's physical base address that is[...]

Example 3: Write data into the transmit buffer of channel A. mov dx, base ; load base address out dx, al ; write data in ax to buffer Example 4: Read data from the receive buffer of channel A. mov dx, base ; load base address in al, dx ; write data in ax to buffer External/Status interrupt information RR15 Upper byte of baud rate time constant RR13[...]

External/Status interrupt control WR15 Miscellaneous control bits: baud rate generator, DPLL control, auto echo WR14 Lower byte of baud rate time constant WR13 Lower byte of baud rate time constant WR12 Clock mode and source control WR11 Miscellaneous transmitter/receiver control bits, NRZI, NRZ, FM coding, CRC reset WR10 Master interrupt control a[...]

9.2 Baud Rate Generator Programming The baud rate generator (hereafter referred to as the BRG) of the SCC consists of a 16-bit down counter, two 8-bit time constant registers, and an output divide-by-two. The time constant for the BRG is programmed into WR12 (least significant byte) and WR13 (most significant byte). The equation relating the baud r[...]

The MPAP-100 is a single-channel device. Portions of SCC channel B are used to augment channel A. Channel B cannot be used for transmit, but may be used for receive, subject to certain limitations. 9.4.1 Receive data and clock signals The receive data signals RXDA and RXDB are tied together. The receive clock input signals RTxCA and RTxCB are also [...]

9.5 SCC Incompatibility Warnings Due to the SCC implementation used by the MPAP-100, there are two minor incompatibilities that the software programmer must avoid. 9.5.1 Register Pointer Bits In a Zilog 85230, the control port register pointer bits can be set in either channel. With the implementation on the MPAP-100, however, both parts of an SCC [...]

10 FIFO Operation The MPAP-100 is equipped with 1024-byte external FIFOs in the transmit and receive data paths. These FIFOs are implemented as extensions of the SCC's small internal FIFOs. They have been designed to be as transparent as possible to the software operating the MPAP-100. By using these FIFOs, it is possible to achieve high data [...]

10.2.2 Receive FIFO The receive FIFO can service the receiver of either channel A or channel B of the SCC. If RXSRC (bit 1) of the Configuration Register (see page 41) is logic 1, the receive FIFO will service SCC channel B. If RXSRC is logic 0, the receive FIFO will service SCC channel A. If the FIFOs are enabled, an I/O read from either SCC Data [...]

10.3.1 Using channel A for both transmit and receive This is the mode in which most applications will run. Set RXSRC (bit 1) in the Configuration Register to logic 0. This will configure the MPAP-100 to use W/REQA for receive DMA and DTR/REQA for transmit DMA. In addition to any other desired SCC configuration, ensure that the following bits are se[...]

10.3.2 Using channel B for receive The MPAP-100 supplies only limited support for SCC channel B. This mode, therefore, is not recommended for most applications. Set RXSRC (bit 1) in the Configuration Register to logic 1. This will configure the MPAP-100 to use W/REQA for transmit DMA and W/REQB for receive DMA. In addition to any other desired SCC [...]

10.4 FIFO status and control Several registers are used to control the FIFOs and monitor their status. These registers are detailed in other chapters of this manual. 10.4.1 Interrupt status Three interrupt statuses, listed in Table 8, can be generated by four events related to FIFO activity. In each case, a latched bit in the Interrupt Status Regis[...]

10.4.2 Resetting the FIFOs The FIFOs are automatically disabled and reset at powerup or when the MPAP-100 is inserted into a PCMCIA socket. The transmit and receive FIFOs can also be independently reset by setting and clearing the appropriate bits in the FIFO Control Register. Resetting a FIFO sets the appropriate FIFO empty status bit and resets t[...]

To make the external FIFOs more useful in byte-synchronous modes, the MPAP-100 can watch for a given character to be transferred consecutively a specific number of times from the SCC into the receive FIFO. When this occurs, the RX_PAT bit in the Interrupt Status Register (see page 43) is set. For instance, the MPAP-100 can watch for the end-of-text[...]

10.7 Receive FIFO timeout With asynchronous operational modes, the same problem exists. Namely, how is one to determine when a reception is complete? While the receive pattern detection may be useful here, the MPAP-100 also offers a timeout feature on the external receive FIFO. If the external FIFO is not empty and a time interval equal to a specif[...]

11 Communications Register The Communications Register is used to set options pertaining to the clocks. The source and type of clock to be transmitted or received can be specified. External synchronization and RS-232 DTE test modes and can also be controlled with this register. The address of the Communications Register is Base+4. Table 9 details i[...]

receive unformatted serial data, as it allows the SCC receiver to be manually placed into sync under program control. This bit is ignored if bit 6 is set (logic 1). Bit 3: RCKEN --- Receive Clock Source: When set (logic 1), this bit allows the receive clock (RCLK) signal to be generated by the TRxC pin on channel B of the SCC. When cleared (logic 0[...]

12 Configuration Register The Configuration Register is used to set the interrupt source and enable the interface between the SCC and the external FIFOs. The address of this register is Base+5. Table 10 details the bit definitions of the register. 0 RXSRC FIFOEN 0 INTS0 INTS1 0 1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Table 10 --- Configur[...]

Bit 1: RXSRC --- Receive FIFO DMA Source: This bit determines which SCC pins are used to control transmit and receive DMA transactions between the SCC and the external FIFOs (when enabled). The transmit data FIFO is always used with SCC channel A. The receive data FIFO may be used with SCC channel A by setting RXSRC to logic 0, or with SCC channel [...]

13 Interrupt Status Register The Interrupt Status Register is used to determine the cause of an interrupt generated by the MPAP-100. The address of this register is Base+8. Table 11 details the bit definitions of the register. The interrupt source in the Configuration Register (see page 41) must be set to INTSCC for any of the statuses indicated by[...]

14 FIFO Status Register The FIFO Status Register is used to return current status information about the external FIFOs. The address of this read-only register is Base+9. Table 12 details the bit definitions of the register. This register can be ignored if the external FIFOs are not being used. TXE TXH TXF 0 RXE RXH RXF 0 Bit 0 Bit 1 Bit 2 Bit 3 Bit[...]

15 FIFO Control Register The FIFO Control Register is used to control the external data FIFOs. The address of this register is Base+A (hex). Table 13 details the bit definitions of the register. This register can be ignored if the external FIFOs are not being used. TX_RESET 0 0 0 RX_RESET EN_TO EN_PAT 0 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit[...]

16 Receive Pattern Character Register The Receive Pattern Character Register is used to set the character value to be used in receive pattern detection. The address of this register is Base+B (hex). This register can be ignored if the external FIFOs are not being used. character value (0-255) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Table 14[...]

17 Receive Pattern Count Register The Receive Pattern Count Register is used to set the counter value to be used in receive pattern detection. The address of this register is Base+C (hex). This register can be ignored if the external FIFOs are not being used. counter value (0-255) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Table 15 --- Receive[...]

18 Receive FIFO Timeout Register The Receive FIFO Timeout Register is used to control the operation of the external receive FIFO timeout feature. The address of this register is Base+D (hex). This register can be ignored if the external FIFOs are not being used. See page 38 for details on the receive FIFO timeout feature. timeout interval (0-63) 0 [...]

19 External Connections The MPAP-100 is configured as a Data Terminal Equipment (DTE) device, meeting the RS-232-D standard using a DB-25 male connector. There is no DCE version available. The control signals the DTE can generate are Request To Send (RTS) and Data Terminal Ready (DTR). It can receive the signals Carrier Detect (DCD), Clear to Send [...]

N/C N/C RxCLK (DTE) SYNCA N/C CD DGND DSR CTS RTS RxD TxD CGND 13 12 11 10 9 8 7 6 5 4 3 2 1 25 24 23 22 21 20 19 18 17 16 15 14 TM (OUTPUT) TxCLK (DTE) N/C N/C RLBK (OUTPUT) DTR N/C LLBK (OUTPUT) RxCLK (DCE) N/C TxCLK (DCE) RING Figure 2 --- MPAP-100 Output Connector The testing signals the DTE can generate are Local Loopback (LL) and Remote Loopb[...]

* Not included in the official RS-232-D specification Comm. Reg. bit 7 TM TEST MODE X 25 TRxCA pin DA TXCLK (DTE) X 24 N/C 23 PCMCIA STSCHG signal CE RING X 22 Comm. Reg. bit 4 RL RLBK X 21 DTR/REQA pin CD DTR X 20 N/C 19 Comm. Reg. bit 5 LL LLBK X 18 RTxCA pin DD RXCLK (DCE) X 17 N/C 16 TRxCA pin DB TXCLK (DCE) X 15 N/C 14 N/C 13 N/C 12 RTxCA or T[...]

20 DTE Interface Signals CIRCUIT AB - SIGNAL GROUND  CONNECTOR NOTATION: DGND  DIRECTION: Not applicable This conductor directly connects the DTE circuit ground to the DCE circuit ground. CIRCUIT BA - TRANSMITTED DATA  CONNECTOR NOTATION: TXD  DIRECTION: To DCE This signal transfers the data generated by the DTE through the communicatio[...]

CIRCUIT CC - DCE READY (DATA SET READY)  CONNECTOR NOTATION: DSR  DIRECTION: From DCE This signal indicates the status of the local DCE by reporting to the DTE device that a communication channel has been established. CIRCUIT CD - DTE READY (DATA TERMINAL READY )  CONNECTOR NOTATION: DTR  DIRECTION: To DCE This signal controls the switc[...]

CIRCUIT DB - TRANSMIT SIGNAL ELEMENT TIMING (DCE SOURCE)  CONNECTOR NOTATION:TXCLK (DCE)  DIRECTION: From DCE This signal, generated by the DCE, provides the DTE with element timing information pertaining to the data transmitted to the DCE. The DCE can use this information for its received data. CIRCUIT DD - RECEIVER SIGNAL ELEMENT TIMING (DC[...]

21 Specifications Bus interface: PCMCIA PC Card Standard 2.1 Physical Dimensions: Type II (5 mm) PCMCIA card Controller: 85230-compatible 16-MHz Serial Communications Controller (SCC) DTE Interface: Male D-25 connector Transmit drivers: RS-232 compatible, 600 kbps typical maximum data rate Receive buffers: RS-232 compatible, 600 kbps typical maximu[...]

22 Software Troubleshooting This appendix discusses how to resolve some common problems sometimes encountered when using the MPAP-100 configuration software. 22.1 DOS Client Driver 22.1.1 Generic "SuperClient" Drivers Many Card and Socket Services packages include a generic client driver (or SuperClient) which configures standard I/O devi[...]

22.2.1 With Card and Socket Services The enabler should NOT be used if any Card and Socket Services are present on the system. If Card and Socket Services is installed, the enabler may interfere with its operation and with the device(s) it controls. The client driver should be used to configure the MPAP-100 if Card and Socket Services are installed[...]

The base address or IRQ value may be out of range. Make sure that the base address is a hexadecimal number between 100 hex and 3F0 hex ending in 0. Make sure that the IRQ is a decimal number between 2 and 15.[...]

MPAP-100 User's Manual Revision 2.22 March 2004 P/N 940-0090-222 Quatech MPAP-100 User's Manual i[...]