Intel IXP12xx manuale d’uso

IXP12xx ATM OC12/Ethernet IP Router Example Design Performance and Headroom Analysis April, 2002 Document Number: 301144-001[...]

Version 1.0 , 4/10/02 Page 2 of 17 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no li ability whatsoev[...]

Version 1.0 , 4/10/02 Page 3 of 17 IXP12xx ATM OC12/Ethernet IP Router Example Design Performance and Headroom Anal ysis OVERVIEW This documents details the performance and h eadroom analysis done on the IXP12xx ATM OC12 / Ethernet IP Router Example Design. It covers the general performance aspects of the protocols; cycle and instruction budgets; t[...]

Version 1.0 , 4/10/02 Page 4 of 17 KEY WORKLOADS & APPROACHES TO TESTING THE EXAMPLE DESIGN Protocol Performance of IP over ATM vs. Ethernet Figure 1 details the protocol processing required to carry an IP packet over ATM and Ethernet. . Figure 1 – Protocol Processing Figures 2 and 3 show that as the size of the IP packet varies so do the eff[...]

Version 1.0 , 4/10/02 Page 5 of 17 The result is that ATM is significantly more effici ent that Ethernet in terms of Mbps for carrying very small PDUs. Every Mbps of single-cell- PDUs on the ATM link requires (84/55) Mbps on the matching Ethernet link(s). 0 16 32 48 64 80 96 112 12 8 14 4 16 0 17 6 02 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 I P P a c ke t [...]

Version 1.0 , 4/10/02 Page 6 of 17 As shown graphically in Figure 3, 622Mbps of single- cell-PDU input requires 622*(84/55) = 949 Mbps of Ethernet output. This example design supplies 800Mbps of Ethern et bandwidth (IXP1240 configurations), so under a single cell/PDU workload the design can be e xpected to transmit Ethernet at line rate, and to dis[...]

Version 1.0 , 4/10/02 Page 7 of 17 bytes/minimum frame}. 84 bytes/frame * 8 bits/byte / 100Mb/sec = 6.72 usec/frame. 232MHz * 6.72 usec/frame = 1559 cycles/frame These cycle budgets specify how frequently a cell or frame goes over the wire. If multiple threads handle multiple frames on the same wire, then the budgets are multiplied accordingly. For[...]

Version 1.0 , 4/10/02 Page 8 of 17 One issue with running simulations unbounded to wi re-rate is that it can hide errors because there is no concept of device overflows or underflows. Further the design can become un-balanced, say for example if an efficient receiver races ahead of the rest of the design, hogging shared system resources and potenti[...]

Version 1.0 , 4/10/02 Page 9 of 17 Both the OC-12 and 4xOC-3 configurations experi ence an ATM overflow after 1M cycles. This indicates that under this system workload, the r eceiver is not keeping up with the wire, but has dropped a cell in the first 6,000 cells. Simulated 40-byte and 1500-byte packet perform ance 2 The OC-12 and 4xOC-3 configurat[...]

Version 1.0 , 4/10/02 Page 10 of 17 the number of times the PHY was not fed a cell in time to keep the wire busy, and thus had to manufacture an idle cell. The number reported here is from the 2 nd counters query when 2 “_VolgaGetChanCounters” are issued on the same line at the VxWorks prompt (this is because “_VolgaGetChanCounters” prints [...]

Version 1.0 , 4/10/02 Page 11 of 17 degrade in these scenarios, a nd the design becomes subject to ATM overflows from running “_VolgaGetChanCounters”. Ethernet Input Ports ATM Transmit Rate [%] IXF6012 Transmit Idle ATM Receive Ports IXF6012 Overflows Ethernet Transmit KFrame/s Ethernet Transmit [MB/s] 8 84 N/A 1 0 138 - 147 8.8 – 9.4 7 73 N/[...]

Version 1.0 , 4/10/02 Page 12 of 17 Ethernet Input Ports ATM Transmit Rate [%] IXF6012 Transmit Idle ATM Receive Ports IXF6012 Overflows Ethernet Transmit KFrame/s Ethernet Transmit [MB/s] 8 100 0 1 0 88,300 5.6 Figure 8 – Two-cell/PDU Perfor mance on 143MHZ DRAM Using 143 MHz DRAM, the 40-byte (2-cell/PDU) wo rkload perform ed perfectly, even wi[...]

Version 1.0 , 4/10/02 Page 13 of 17 Queue to Core Measurement Technique The performance of the queue-to-core path can be measured by modifying a nominal input data stream such that the entire stream is forwarded to core. For example, changing the IP version in the IP header from 4 to 5 will cause the packets to be forwarded to the core. The lab equ[...]

Version 1.0 , 4/10/02 Page 14 of 17 RESOURCE UTILIZATION AND HEADROOM ANALYSIS This section details system resource utilization, including per-microengine resources such as registers and microstore instructions; as well as shared resources such as Scratchpad RAM, SRAM, and DRAM. The memory utilization is shown using the default system memory map as[...]

Version 1.0 , 4/10/02 Page 15 of 17 Microstore utilization can be observed by openi ng a microengine list window with line num bers enabled, and recording the last line number plus 1. A vailable instructions = 2048 – used instructions. Figure 12 shows the results for each of the three configurations. The CRC Check and CRC Generate microengines ap[...]

Version 1.0 , 4/10/02 Page 16 of 17 SDRAM Capacity The IXM1240 Network Processor Base Card comes with 128MB of SDRAM. The project is configured to use less than 64MB: 32MB of Packet Data Buffers, 16MB for VxWorks, and the balance for IP Route Table Entries. This leaves over 50% available. The IP Route Table Entries live at 0x8100, simp ly because t[...]

Version 1.0 , 4/10/02 Page 17 of 17 APPENDIX Buffer Allocation in DRAM The microengines in this example design uses two DRAM command queues. The ordered queue is used by all sdram_crc[] commands to transfer packet data between DRAM and the receive and transmit FIFOs. The priority queue is used for all other microengine DRAM accesses, including acce[...]