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Cypress CY7C68320C manuale d’uso - BKManuals
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Cypress CY7C68320C manuale d’uso

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Sommario del manuale d’uso

  • Pagina 1

    EZ-USB A T2LP™ USB 2.0 to A T A/A T API Bridge CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document 001-05809 Rev . *A Revised November 30, 2006 Features • Fixed-function mass storage devi ce—requires no firmware • T wo powe r modes: S[...]

  • Pagina 2

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 2 of 42 Applications The CY7C68300C/30 1C and CY7C68320C/321A impleme nt a USB 2.0 bridge for all A T A/A T API-6 compliant mass storage devices, such as the following: • Hard drives • CD-RO M, CD-R/W • DVD-ROM, DVD-RAM, DVD±R/W • MP3 players • Personal media pl[...]

  • Pagina 3

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 3 of 42 Pin Diagrams The A T2LP is available in different package types to meet a va riety of design needs. The C Y7C68320C/321C is availab le in 56-pin QFN and 100-pin TQFP packages to provide the greatest flexibi lity for new designs. The CY7C 68300C/301C is availa ble i[...]

  • Pagina 4

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 4 of 42 Figure 3. 56-pin QFN Pinout (CY7C68300C/CY7C683 01C) RESET# GND ARESET# DA2 ( VBUS_PWR_VAL ID ) CS1# CS0# DRVPW RVLD ( DA2 ) DA1 DA0 INTRQ VCC DMAC K# DIOR# DIOW # IORDY DMARQ AVCC XTA L OU T XTA L I N AGND VCC DPLUS DMINUS GND VCC GND (PU10K) PW R500# GND 15 16 17[...]

  • Pagina 5

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 5 of 42 Figure 4. 56-pin SSOP Pinout (CY7C68320C/CY7C683 21C) 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 GPIO2 VCC GND IORDY DMARQ AVCC XTALOUT XTALIN AGND V[...]

  • Pagina 6

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 6 of 42 Figure 5. 56-pin QFN Pinout (CY7C68320C/CY7C683 21C) GND VCC GPIO2 GND DD15 DD14 DD13 DD12 DD11 DD10 DD9 DD8 VBUS_ATA_ENABLE VCC RESET# GND ARESET# DA2 CS1# CS0# GPIO0 DA1 DA0 INTRQ VCC DMACK# DIOR# DIOW# IORDY DMARQ AVCC XTALOUT XTALIN AGND VCC DPLUS DMINUS GND VC[...]

  • Pagina 7

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 7 of 42 Figure 6. 100-pin T QFP Pinout (CY7C68320C/CY7C68321 C only) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DD8 VBUS_ATA_EN ABLE VCC RESET # NC GND ARESET # DA2 CS1# CS0#[...]

  • Pagina 8

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 8 of 42 Pin Descriptions The following table lists the pinouts for the 56-pin SSOP , 56-pin QFN and 100-pin T QFP package options for th e A T2LP . Refer to the “Pin Diagrams” on page 3 for differences between the 68300C/01C and 68320C /321C pinouts for the 56-pin pack[...]

  • Pagina 9

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 9 of 42 30 16 23 SDA IO Data signal for I 2 C interface. (See “SCL, SDA” on page 1 1 ). Apply a 2.2k pull up resistor . 31 32 N/A N/A NC No connect. 33 17 24 V CC PWR V CC . Connect to 3.3V power source . 34 18 25 DD0 IO [1] Hi-Z ATA d a t a b i t 0 . 35 19 26 DD1 IO [[...]

  • Pagina 10

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 10 of 42 68 34 41 DA0 O/Z [1] Driven HIGH after 2 ms delay A T A ad dress . 69 35 42 DA1 O/Z [1] Driven HIGH after 2 ms delay A T A ad dress . 70 [3] 36 [3] 43 DRVPWR VLD ( DA2 ) I Input Device presence dete ct. (See “DRVPWRVLD” on page 13 ). Configurable logical p ola[...]

  • Pagina 11

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 1 1 of 42 Additional Pi n Descriptions The following se ctions provide additional pin information. DPLUS, DMINUS DPLUS and DMINUS are the USB signali ng pins; they must be tied to the D+ and D– pins of the USB con nector . Because they operate at h igh frequencies, the U[...]

  • Pagina 12

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 12 of 42 SYSIRQ The SYSIRQ pin provides a way for systems to request service from host software by using the USB Interrupt pipe o n endpoint 1 (EP1). If the A T2LP has no pe ndi ng interrupt data to return, USB interrupt pipe data requests are NAKed. If pending data is ava[...]

  • Pagina 13

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 13 of 42 Figure 8. SYSIRQ Latching Algorithm DRVPWRVLD When this pin is e nabled with bit 0 of configuration address 0x08 (DRVPWR VLD Enable), the A T2LP informs the host that a removable device, su ch as a CF ca rd, is present. The A T2LP uses DRVPWRVLD to detect that the[...]

  • Pagina 14

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 14 of 42 interface and the attached mass storage d evice, especially if Ultra DMA Mode is used. VBUS_A T A_ENABLE VBUS_A T A_ENABLE is typically used to indicate to the A T2LP that power is p resent on VBUS. This pin is polled b y the A T2LP at st artup and then every 20 m[...]

  • Pagina 15

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 15 of 42 HID Functions for Button Controls Cypress’s CY7C68320C/CY7C68321C has the capability of supporting Human Interface Device (HID ) signaling to the host. If there is a HID descriptor in the configurati on data, the GPIO pins that are set as inputs are polled by th[...]

  • Pagina 16

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 16 of 42 T able 6. A T ACB Field Descriptions Byte Field Name Field Descripti on 0 bVSCBSignature This field indicates to the CY7C68300C/CY7C6 8301C that the A T ACB contains a vendor-specific command blo ck. This value of this field must match the value in EEPROM address [...]

  • Pagina 17

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 17 of 42 3 bmA T ACBRe gisterSele ct This field controls which of the taskfile register read or write accesses occur . T askfile read data is always 8 bytes in leng th, and unselected register data are returned as 0x00. Register accesses occur in sequential order as outlin[...]

  • Pagina 18

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 18 of 42 Operating Modes The different modes of oper ation and EEPROM information are presented in the following se ctions. Operational Mode Select ion Flow During the power-up sequence, the A T2LP queries the I 2 C bus for an EEPROM. The A T2LP th en selects a pinout conf[...]

  • Pagina 19

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 19 of 42 Fused Memory Data When no EEPROM is detected at startup, the A T2LP enumerates with the VI D/PID/DID values that are stored in the fused memory space. These values can b e programmed into the A T 2LP during ch ip manufacturing for high volume applica - tions to av[...]

  • Pagina 20

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 20 of 42 MfgCB The mfg_load and mfg _read vendor-specific commands are passed down through th e bulk pipe in the CBWCB p ortion of the CBW . The format of thi s MfgCB is shown as foll ows. Byte 0 is a vendor-specific command designator wh ose value is configurable and set [...]

  • Pagina 21

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 21 of 42 EEPROM Organization The contents of the recommended 256-byte (2048-bit) I 2 C EEPROM are arranged as follows. In T able 1 1 , the column labeled ‘Required Conten ts’ contains the values that must be used for proper operation of the A T2LP . The column labeled [...]

  • Pagina 22

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 22 of 42 T able 1 1.Configuration Dat a Organization Byte Address Configuration Item Name Configuration Item Description Required Contents Var i a b l e Contents Note Devices running in Backward Compatibility (CY7C68300A) Mode must use the CY7C6830 0A EEPROM organization, [...]

  • Pagina 23

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 23 of 42 SRST Enable Bit 1 Determines if th e A T2LP is to do an SR ST reset during drive initialization. At le ast one reset must be enabled. Do not set SRST to 0 and Skip Pin Rese t to 1 at the same time. 0 = Do not perform SRST during initi aliza tion. 1 = Perform SRST [...]

  • Pagina 24

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 24 of 42 0x08 BUTTON_MODE Bit 7 Button mode (100-pin package only). Sets A T APUEN, PWR500# and DRVPWRVLD to become button inputs returned on bits 2, 1, and 0 of EP1IN. This bit must be set to ‘0’ if the 56-pin packages are used. 0 = Disable button mode. 1 = Enable but[...]

  • Pagina 25

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 25 of 42 0x0A Reserved GPIO Output Pin S tate Bits 7:6 Reserved. Must be set to zero. Bits 5:0 These bits select the value driv en on the GPIO pins that are configured as outputs in configuration address 0x09. 0 = Drive the GPIO pin LOW 1 = Drive the GPIO pin HIGH 0x00 0x0[...]

  • Pagina 26

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 26 of 42 0x12 bcdUSB (LSB) USB S pecification release number in BCD 0x00 0x13 bcdUSB (MSB) 0x02 0x14 bDeviceClass Device class 0x00 0x15 bDeviceSubClass Device subclass 0x00 0x16 bDeviceProtocol Device protocol 0x00 0x17 bMaxPacketSize0 USB packet size supported for defaul[...]

  • Pagina 27

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 27 of 42 0x32 iConfiguration Index to the configu rati on string. This entry must eq ual half of the address value where the string starts, or 0x00 if the string does not e xist. 0x00 0x33 bmAttributes Device attrib utes for this configu rat ion Bit 7 Reserved. Must be set[...]

  • Pagina 28

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 28 of 42 0x4F bAlternateSetting Alternate setting 0x00 0x50 bNumEndpoints Number of endpoints used by this interface 0x01 0x51 bInterfaceClass Class code 0x03 0x52 bInterfaceSubClass Sub class 0x00 0x53 bInterfaceSubSubClass Sub Sub class 0x00 0x54 iInterface Index of stri[...]

  • Pagina 29

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 29 of 42 0x75 Report_Size 8 bits 0x75 0x76 0x08 0x77 Report_Count 2 fields 0x95 0x78 0x02 0x79 Input Input (Data, V ariable, Absolute) 0x81 0x7A 0x02 Output Report 0x7B Usage Usage - vendor defined 0x09 0x7C 0xA9 0x7D Logical_Minimum Logical Minimum (–128) 0x15 0x7E 0x80[...]

  • Pagina 30

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 30 of 42 0x95 bRecipient Identifier of the target recipient If Recipient type field of bmAttributes = 1 then bRecipient field is the bInterfaceNumber If Recipient type field of bmAttributes = 2 then bRecipient field is an endpoint address, where: D7: Direction (0 = Out, 1 [...]

  • Pagina 31

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 31 of 42 0xB5 bS tring Unicode character LSB ’ ’ 0x20 0xB6 bS tring Unicode character MSB 0x00 0xB7 bS tring Unicode character LSB ’S’ 0x53 0xB8 bS tring Unicode character MSB 0x00 0xB9 bS tring Unicode character LSB ’e’ 0x65 0xBA bS tring Unicode characte r MS[...]

  • Pagina 32

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 32 of 42 0xDF bS tring Unicode characte r LSB ’ ’ 0x20 0xE0 bS tring Unicode character MSB 0x00 0xE1 bS tring Unicode character LSB ’D’ 0x53 0xE2 bS tring Unicode character MSB 0x00 0xE3 bS tring Unicode character LSB ’i’ 0x74 0xE4 bS tring Unicode character MS[...]

  • Pagina 33

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 33 of 42 Note : More than 0X100 bytes of co nfiguration are shown for ex ample only . The A T2LP only supports addresses up to 0xFF . Programming the EEPROM There are three methods of programming the EEPROM: • S tand-alone EEPROM programmer • V endor-specific USB comma[...]

  • Pagina 34

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 34 of 42 Legal values for wV alue are as follows: • 0x0000 Internal Config bytes, address range 0x2 – 0xF • 0x0002 External I 2 C memory device Internal Config byte writes must be con strai ned to ad dresses 0x2 through 0xF , as shown in Ta b l e 1 2 . Attempts to wr[...]

  • Pagina 35

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 35 of 42 Absolute Maximum Ratings S torage T emperature .............. ... ......................... .......................... ......................... ... ............ .. ......................... ..... –65 ° C to +150 ° C Ambient T e mperature with Power Supplied .[...]

  • Pagina 36

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 36 of 42 AC Electrical Characteristics A T A Timing C haracter istics The A T A interface supports A T A PIO modes 0, 3, and 4, Ultra DMA modes 2, 3, and 4, and mu lti-word DMA mode 2, per the A T A/A T API 6 S pecificatio n. The highest enabled transfe r rate common to bo[...]

  • Pagina 37

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 37 of 42 Package Diagrams Figure 12. 100-Pin Thin Plastic Qu ad Flatp ack (14 x 20 x 1.4 mm) A101 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DI[...]

  • Pagina 38

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 38 of 42 Figure 13. 56-lead Shrunk Sm all Outline Package 05 6 Package Diagrams (continued) 0.095 0.025 0.008 SEATING PLANE 0.420 0.088 .020 0.292 0.299 0.395 0.092 BSC 0.110 0.016 0.720 0.008 0.0135 0.730 DIMENSIONS IN INCHES MIN. MAX. 0.040 0.024 0° -8° GAUGE PLANE .01[...]

  • Pagina 39

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 39 of 42 General PCB Layout Recommendations For USB Ma ss Storage Designs The following recommendation s must be followed to ensure reliable high-performance operation: • Use at least a four-layer , impedance controll ed board to maintain signal quality . • S pecify sp[...]

  • Pagina 40

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 40 of 42 Quad Flat Package No Leads (QFN) Package Design Note s Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the botto m surface of the package to the PCB. Hence, special attention is required to the heat transfer area[...]

  • Pagina 41

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 41 of 42 © Cypress Semi con duct or Cor po rati on , 20 06 . The information contained he re i n is su bj ect to ch an ge wi t hou t n otice. Cypress Semic onductor Corporation assu mes no resp onsib ility for th e u se of any circuitry o ther than circuitry embodied i n [...]

  • Pagina 42

    CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Document 001-05809 Rev . *A Page 42 of 42 Document History Paged Description Title: CY7C68300C/CY7C68301C/CY7 C683 20C/C Y7C68321C EZ-USB A T2LP™ USB 2.0 to A T A/A T API Bridge Document Numb er: 001-05809 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 409321 See ECN GIR New data shee[...]