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Cypress Semiconductor CY7C1360C manuale d’uso - BKManuals
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Cypress Semiconductor CY7C1360C manuale d’uso

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Le regole impongono al rivenditore l'obbligo di fornire all'acquirente, insieme alle merci, il manuale d’uso Cypress Semiconductor CY7C1360C. La mancanza del manuale d’uso o le informazioni errate fornite al consumatore sono la base di una denuncia in caso di inosservanza del dispositivo con il contratto. Secondo la legge, l’inclusione del manuale d’uso in una forma diversa da quella cartacea è permessa, che viene spesso utilizzato recentemente, includendo una forma grafica o elettronica Cypress Semiconductor CY7C1360C o video didattici per gli utenti. La condizione è il suo carattere leggibile e comprensibile.

Che cosa è il manuale d’uso?

La parola deriva dal latino "instructio", cioè organizzare. Così, il manuale d’uso Cypress Semiconductor CY7C1360C descrive le fasi del procedimento. Lo scopo del manuale d’uso è istruire, facilitare lo avviamento, l'uso di attrezzature o l’esecuzione di determinate azioni. Il manuale è una raccolta di informazioni sull'oggetto/servizio, un suggerimento.

Purtroppo, pochi utenti prendono il tempo di leggere il manuale d’uso, e un buono manuale non solo permette di conoscere una serie di funzionalità aggiuntive del dispositivo acquistato, ma anche evitare la maggioranza dei guasti.

Quindi cosa dovrebbe contenere il manuale perfetto?

Innanzitutto, il manuale d’uso Cypress Semiconductor CY7C1360C dovrebbe contenere:
- informazioni sui dati tecnici del dispositivo Cypress Semiconductor CY7C1360C
- nome del fabbricante e anno di fabbricazione Cypress Semiconductor CY7C1360C
- istruzioni per l'uso, la regolazione e la manutenzione delle attrezzature Cypress Semiconductor CY7C1360C
- segnaletica di sicurezza e certificati che confermano la conformità con le norme pertinenti

Perché non leggiamo i manuali d’uso?

Generalmente questo è dovuto alla mancanza di tempo e certezza per quanto riguarda la funzionalità specifica delle attrezzature acquistate. Purtroppo, la connessione e l’avvio Cypress Semiconductor CY7C1360C non sono sufficienti. Questo manuale contiene una serie di linee guida per funzionalità specifiche, la sicurezza, metodi di manutenzione (anche i mezzi che dovrebbero essere usati), eventuali difetti Cypress Semiconductor CY7C1360C e modi per risolvere i problemi più comuni durante l'uso. Infine, il manuale contiene le coordinate del servizio Cypress Semiconductor in assenza dell'efficacia delle soluzioni proposte. Attualmente, i manuali d’uso sotto forma di animazioni interessanti e video didattici che sono migliori che la brochure suscitano un interesse considerevole. Questo tipo di manuale permette all'utente di visualizzare tutto il video didattico senza saltare le specifiche e complicate descrizioni tecniche Cypress Semiconductor CY7C1360C, come nel caso della versione cartacea.

Perché leggere il manuale d’uso?

Prima di tutto, contiene la risposta sulla struttura, le possibilità del dispositivo Cypress Semiconductor CY7C1360C, l'uso di vari accessori ed una serie di informazioni per sfruttare totalmente tutte le caratteristiche e servizi.

Dopo l'acquisto di successo di attrezzature/dispositivo, prendere un momento per familiarizzare con tutte le parti del manuale d'uso Cypress Semiconductor CY7C1360C. Attualmente, sono preparati con cura e tradotti per essere comprensibili non solo per gli utenti, ma per svolgere la loro funzione di base di informazioni e di aiuto.

Sommario del manuale d’uso

  • Pagina 1

    9-Mbit (256K x 36/512K x 18) Pipelined SRAM CY7C1360C CY7C1362C Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05540 Rev . *H Revised September 14, 2006 Features • Supports bus operation up to 250 MHz • A vailable speed grades are 250, 20 0, and 166 MHz • Registered in[...]

  • Pagina 2

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 2 of 31 . Selection Guide 250 MHz 200 MHz 166 MHz Unit Maximum Access T ime 2.8 3.0 3.5 ns Maximum Operating Curren t 250 220 180 mA Maximum CMOS S tandby Current 40 40 40 mA ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSP ADSC MODE BWE GW CE 1 CE 2 CE 3 OE ENABLE REGISTER OUTPU[...]

  • Pagina 3

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 3 of 31 Pin Configurations A A A A A 1 A 0 NC/72M NC/36M V SS V DD NC/18M A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQc V DDQ V SSQ DQ C DQ C DQ C DQ C V [...]

  • Pagina 4

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 4 of 31 Pin Configurations (continued) A A A A A 1 A 0 NC/72M NC/36M V SS V DD NC/18M NC A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQ C V DDQ V SSQ DQ C DQ [...]

  • Pagina 5

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 5 of 31 Pin Configurations (continued) 234 5 67 1 A B C D E F G H J K L M N P R T U V DDQ NC/288M NC/144M DQP C DQ C DQ D DQ C DQ D AA A A ADSP V DDQ CE 2 A DQ C V DDQ DQ C V DDQ V DDQ V DDQ DQ D DQ D NC NC V DDQ V DD CLK V DD V SS V SS V SS V SS V SS V SS V SS V SS NC/576M NC/1G NC NC TDO TCK [...]

  • Pagina 6

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 6 of 31 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable with JT AG) CY7C1360C (256 K x 36) 234 56 7 1 A B C D E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ D DQ D NC/36M NC/72M V DDQ B[...]

  • Pagina 7

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 7 of 31 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address In puts used to select one of the add ress locations . Sample d at the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 [2] are sampled active. A 1 , A 0 are fed to the two-bit[...]

  • Pagina 8

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 8 of 31 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO ) is 2.8 ns (250-MHz device). The[...]

  • Pagina 9

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 9 of 31 conducted, the data presented to the DQs is written into the corresponding address location i n the memory core. If a Byte Write is conducted, only the se lected byte s are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronou s self-timed Write m[...]

  • Pagina 10

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 10 of 31 READ Cycle, Begin Burst External L H L L H L X H L L-H Q READ Cycle, Begin Burst External L H L L H L X H H L-H T ri-St a te READ Cycle, Continue Burst Next X X X L H H L H L L-H Q READ Cycle, Continue Burst Next X X X L H H L H H L-H T ri-St a te READ Cycle, Continue Burst Next H X X [...]

  • Pagina 11

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 1 1 of 31 IEEE 1 149.1 Serial Boundary Sc an (JT AG) The CY7C1360C/CY7C1362C incorpora tes a serial boundary scan test access port (T AP) in the BGA package only . The TQFP package does not offer this functionality . This part operates in accordance with IEEE S t andard 1 149.1-1900, but doesn?[...]

  • Pagina 12

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 12 of 31 T AP Controller Block Diagram Performing a T AP Reset A RESET is performed by forcing TMS HIGH (V DD ) for five rising edges of TCK. This RESE T does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the T AP is reset in ternally to ens[...]

  • Pagina 13

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 13 of 31 IDCODE The IDCODE instruction causes a ven dor-specific, 32-bit code to be loaded into the instruction re gister . It also places the instruction register betwee n the TDI and TDO balls and allows the IDCODE to be shifted out of the device when th e T AP controller enters the Shift-DR [...]

  • Pagina 14

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 14 of 31 3.3V T AP AC T est Conditions Input pulse levels ............... .............. .............. ..... V SS to 3.3V Input rise and fall times ......... .............. ...................... ... ... 1 ns Input timing referenc e levels ...... .............. ........... ............1.5V Out[...]

  • Pagina 15

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 15 of 31 V OL2 Output LOW V oltage I OL = 100 µA V DDQ = 3.3V 0.2 V V DDQ = 2.5V 0.2 V V IH Input HIGH V oltage V DDQ = 3.3V 2.0 V DD + 0.3 V V DDQ = 2.5V 1.7 V DD + 0.3 V V IL Input LOW V oltage V DD Q = 3.3V –0.5 0.7 V V DDQ = 2.5V –0.3 0.7 V I X Input Load Current GND < V IN < V D[...]

  • Pagina 16

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 16 of 31 165-ball FBGA Boundary Scan Order CY7C1360C (256K x 36) CY7C1362C (512K x 18) Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball ID Signal Name 1 B6 CLK 37 R 6 A0 1 B6 CLK 37 R6 A0 2B 7 G W 38 P6 A1 2 B7 GW 38 P6 A1 3A 7 B W E 39 R4 A 3 A7 BWE 39 R4 A [...]

  • Pagina 17

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 17 of 31 1 19-ball BGA Boundary Scan Ord er CY7C1360C (256K x 36) CY7C1362C (512K x 18) Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball ID Signal Name 1 K4 CLK 37 P4 A0 1 K4 CLK 37 P4 A0 2H 4 G W 38 N4 A1 2 H4 GW 38 N4 A1 3M 4 B W E 39 R6 A 3 M4 BWE 39 R6 A [...]

  • Pagina 18

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 18 of 31 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emp erature ............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied ........... ............................ ...... –55°C to + 125°C [...]

  • Pagina 19

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 19 of 31 Cap acit ance [16] Parameter Description T est Conditions 100 TQFP Max. 1 19 BGA Max. 165 FBGA Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 55 5 p F C CLK Clock Input Capacitance 5 5 5 pF C I/O Input/Output Capacitance 5 7 7 pF Thermal Resist ance [[...]

  • Pagina 20

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 20 of 31 Switching Characteristics Over the Operating Range [17, 18] Parameter Description –250 –200 –166 Unit Min. Max. Min. Max. Min. Max. t POWER V DD (T ypical) to the First Access [19] 11 1 m s Clock t CYC Clock Cycle Time 4.0 5.0 6.0 ns t CH Clock HIGH 1.8 2.0 2.4 ns t CL Clock LOW [...]

  • Pagina 21

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 21 of 31 Switching W aveforms Read Cycle Timing [23] Note: 23. On this diagram, when CE is LOW: CE 1 is LOW, C E 2 is HIGH and CE 3 is LOW. When CE is HIGH: CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES GW, BWE, BWx[...]

  • Pagina 22

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 22 of 31 Write Cycle T iming [23, 24] Note: 24. Full width Write can be initiate d by either GW LOW; or by GW HIGH, BWE LOW and BW X LOW. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES BWE, BW X D ata Out (Q) High-Z ADV BURST RE[...]

  • Pagina 23

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 23 of 31 Read/Write Cycle Timing [23, 25, 26 ] Notes: 25. The data bus (Q) remains in high-Z following a W rite cycle, unless a new Read access is initiated by ADSP or ADSC . 26. GW is HIGH. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A2 t [...]

  • Pagina 24

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 24 of 31 ZZ Mode T iming [27, 28] Notes: 27. Device must be desele ct ed when entering ZZ mode. See Cycle Descr iptions t able for all possible signal conditions to deselect the device. 28. DQs are in High-Z when exiting ZZ sleep mode. Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZR[...]

  • Pagina 25

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 25 of 31 Ordering Information Not all of the spe ed, package and temperature ran ges are available. Please contact your local sales r epresentative or visit www . cypress.com for actual pro duct s offered. Speed (MHz) Ordering Code Pa ckage Diagram Part and Packa ge T ype Operating Range 166 CY[...]

  • Pagina 26

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 26 of 31 200 CY7C1360C-200AXC 51-8 5050 100-pin Thin Quad F lat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip Enable) Comm ercial CY7C1362C-200AXC CY7C1360C-200AJXC 51-8 5050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip Enable) CY7C1362C-200AJXC CY7C1360C-200BGC 51-851 15 1 19-b[...]

  • Pagina 27

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 27 of 31 250 CY7C1360C-250AXC 51-8 5050 100-pin Thin Quad F lat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip Enable) Comm ercial CY7C1362C-250AXC CY7C1360C-250AJXC 51-8 5050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip Enable) CY7C1362C-250AJXC CY7C1360C-250BGC 51-851 15 1 19-b[...]

  • Pagina 28

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 28 of 31 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMAT[...]

  • Pagina 29

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 29 of 31 Package Diagrams (continued) 1.27 20.32 2 16 5 4 37 L E A B D C H G F K J U P N M T R 12.00 19.50 30° TYP. 2.40 MAX. A1 CORNER 0.70 REF. U T R P N M L K J H G F E D C A B 21 43 65 7 Ø1.00(3X) REF. 7.62 22.00±0.20 14.00±0.20 1.27 0.60±0.10 C 0.15 C B A 0.15(4X) Ø0.05 M C Ø0.75±0[...]

  • Pagina 30

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 30 of 31 © Cypress Semi con duct or Cor po rati on , 20 06 . The information contained he re i n is su bj ect to ch ange without notice. Cypress S em ic on duct or Corpo ration assu mes no resp onsib ility for th e u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. N[...]

  • Pagina 31

    CY7C1360C CY7C1362C Document #: 38-05540 Rev . *H Page 31 of 31 Document History Page Document Title: CY7C1360C/CY7C1362C 9-Mbit (256K x 36/512K x 18 ) Pipelined SRAM Document Number: 38-05540 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 2416 90 See ECN RKF New data sheet *A 278130 See ECN RKF Changed Boundary Scan order to mat[...]