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Cypress 37000 CPLD manuel d'utilisation

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- nom du fabricant et année de fabrication Cypress 37000 CPLD
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Table des matières du manuel d’utilisation

  • Page 1

    5V , 3.3V , ISR™ High-Performance CPLDs Ultra37000 CPLD Family Cypress Semiconductor Corpora tion • 3901 North First S treet • San Jose , CA 95134 • 408-943-26 00 Document #: 38-03007 Rev . *E Revised March 7, 2004 Features • In-System Reprogram mab le™ (ISR ™) CMOS CPL Ds — JT AG interface for reconfigurabil ity — Design cha nges[...]

  • Page 2

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 2 of 64 Selection Guide 5.0V Selec tion Guide General Informa tion Device Macrocells Dedicated Input s I/O Pins Speed (t PD )S p e e d ( f MAX ) CY37032 32 5 32 6 200 CY37064 64 5 32/64 6 200 CY37128 128 5 64/128 6.5 167 CY37192 192 5 120 7.5 154 CY37256 256 5 128/160/192 7.5 154 CY37384 384[...]

  • Page 3

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 3 of 64 Architecture Overview of Ultra37000 Family Programmable Interc onnect Matrix The PIM consists of a completely global routing matrix for signals from I/O pins and feedbacks from th e logic blocks. The PIM provides extremely robust interco nnection to avoid fitting and density limitati[...]

  • Page 4

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 4 of 64 Low-Power Option Each logic block can operate in high-speed mode for critical path performance, or in low-power mode for power con ser- vation. The logic block mode is set by the user on a logic blo ck by logic block basis. Product T e rm Allocator Through the product te rm allocator[...]

  • Page 5

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 5 of 64 The buried macrocell also suppor ts input register capability . The buried macrocell can b e configured to act as an inp ut register (D-type or latch) whos e input comes from the I/O pin associated with the neighboring macr ocel l. The output of all buried macrocells is sent di rectl[...]

  • Page 6

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 6 of 64 Clocking Each I/O and buried macrocell has access to four synch ronous clocks (CLK0, CLK1, CLK2 and CLK3) as wel l as an asynchronous product term clock PTCLK. Each inp ut macrocell has access to all four synchronous clocks. Dedicated Inputs/Clocks Five pins on each me mber of the Ul[...]

  • Page 7

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 7 of 64 JT AG and PCI St andards PCI Compliance 5V operation of the Ultra37000 is full y compliant with the PCI Local Bus S pe cification published by the PCI S pecial Interest Group. The 3.3V products meet all PC I requirements except for the output 3.3V clamp, which is in direct conflict w[...]

  • Page 8

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 8 of 64 The third programming option for Ultra37000 devices is to utilize the embedded controll er or processor that already exists in the system. The Ultra37000 ISR software assists in this method by converting the device JEDEC maps into the ISR serial stream that contains the ISR instructi[...]

  • Page 9

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 9 of 64 Logic Block Diagrams CY37032/CY37032V LOGIC BLOCK B LOGIC BLOCK A 36 16 36 16 Input Clock/ Input 16 I/Os 16 I/Os I/O 0 − I/O 15 I/O 16 − I/O 31 4 4 4 16 16 TDI TCK TMS TDO JT AG T ap Controller 1 PIM JT AG EN LOGIC BLOCK D LOGIC BLOCK C LOGIC BLOCK A LOGIC BLOCK B 36 16 36 16 36 [...]

  • Page 10

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 10 of 64 Logic Block Diagrams (continued) TDI TCK TMS TDO JT AG T ap Controller CY37128/CY37128V PIM INPUT MACROCELL CLOCK INPUTS 4 4 36 16 16 36 LOGIC BLOCK 36 16 16 36 16 I/Os 36 36 36 16 16 36 16 16 64 64 4 1 INPUT/CLOCK MACROCELLS I/O 0 –I/O 15 A INPUT S LOGIC BLOCK C LOGIC BLOCK B LOG[...]

  • Page 11

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 1 1 of 64 Logic Block Diagrams (continued) CY37256/CY37256V LOGIC BLOCK G LOGIC BLOCK H LOGIC BLOCK I LOGIC BLOCK J LOGIC BLOCK L LOGIC BLOCK P LOGIC BLOCK M LOGIC BLOCK N LOGIC BLOCK O LOGIC BLOCK A LOGIC BLOCK B LOGIC BLOCK C LOGIC BLOCK D LOGIC BLOCK E LOGIC BLOCK K LOGIC BLOCK F 36 16 36[...]

  • Page 12

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 12 of 64 Logic Block Diagrams (continued) CY37384/CY37384V LOGIC BLOCK AH LOGIC BLOCK AI LOGIC BLOCK BD LOGIC BLOCK BE LOGIC BLOCK BG LOGIC BLOCK BL LOGIC BLOCK BI LOGIC BLOCK BJ LOGIC BLOCK BK LOGIC BLOCK AA LOGIC BLOCK AB LOGIC BLOCK AC LOGIC BLOCK AD LOGIC BLOCK AF LOGIC BLOCK BF LOGIC BL[...]

  • Page 13

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 13 of 64 Logic Block Diagrams (continued) CY37512/CY37512V LOGIC BLOCK AG LOGIC BLOCK AH LOGIC BLOCK BI LOGIC BLOCK BJ LOGIC BLOCK BL LOGIC BLOCK BP LOGIC BLOCK BM LOGIC BLOCK BN LOGIC BLOCK BO LOGIC BLOCK AA LOGIC BLOCK AB LOGIC BLOCK AC LOGIC BLOCK AD LOGIC BLOCK AE LOGIC BLOCK BK LOGIC BL[...]

  • Page 14

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 14 of 64 5.0V Device Characteristics Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emp erature ............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied ........... ..........................[...]

  • Page 15

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 15 of 64 3.3V Device Characteristics Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature .. ................. .............. –65 ° C to +150 ° C Ambient T emperature with Power Applied ... .............. .............. .[...]

  • Page 16

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 16 of 64 Induct ance [5] Parameter Description T est Con ditions 44- Lead TQFP 44- Lead PLCC 44- Lead CLCC 84- Lead PLCC 84- Lead CLCC 100- Lead TQFP 160- Lead TQFP 208- Lead PQFP Unit L Max imum Pin Induct ance V IN = 3.3V at f = 1 MHz 2528589 1 1 n H Cap acit ance [5] Parameter Descr iptio[...]

  • Page 17

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 17 of 64 Parameter [1 1] V X Ou tput W aveform—Measurement L evel t ER(–) 1.5V t ER(+) 2.6V t EA(+) 1.5V t EA(–) V the (d) T est Waveforms V OH V X 0.5V V OL V X 0.5V V X V OH 0.5V V X V OL 0.5V Switching Characteristics Over the Operating Range [12] Parameter Description Unit Combinat[...]

  • Page 18

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 18 of 64 Product T erm Clocki ng Parameters t COPT [13, 14, 15] Product T erm Clock or Latch Enable (PTCLK) to Output ns t SPT Set-Up T ime from Input to Product T erm Cl ock or Latch Enable (PTCLK) ns t HPT Register or Latch Dat a Hold T ime ns t ISP T [13] Set-Up T ime for Buried Register [...]

  • Page 19

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 19 of 64 Switching Characteristics Over the Operating Range [12] Parameter 200 MHz 16 7 MHz 154 MHz 143 MHz 125 MHz 100 MHz 83 MHz 66 MHz Unit Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Combinatorial Mode Parameters t PD [13, 14, 15] 6 6.5 7.5 8.5 10 12 1[...]

  • Page 20

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 20 of 64 t RO [13, 14, 15] 12 13 13 14 15 18 21 26 ns t PW 8 8 8 8 10 12 15 20 ns t PR [13] 10 10 10 10 12 14 17 22 ns t PO [13, 14, 15] 12 13 13 14 15 18 21 26 ns User Option Parameters t LP 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t SLEW 33 3 3 3 3 3 3 n s t 3.3IO [19] 0.3 0.3 0.3 0.3 0.3 0.3 0.[...]

  • Page 21

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 21 of 64 Registered Output wi th Product Term Clocking In put Going Through the Ar ray Registered Outpu t with Product Te rm Clocking Input Coming From Adjacen t Buried Register Latched Output Switching W aveforms (continued) t SPT INPUT PRODUCT TERM t COPT REGISTERED OUTPUT t HPT CLOCK t IS[...]

  • Page 22

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 22 of 64 Registered Input Clock to Clock Latched Input Switching W aveforms (continued) t IS REGISTERED INPUT INPUT REGISTER CLOCK t ICO COMBINATORIAL OUTPUT t IH CLOCK t WL t WH INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK t SCS t ICS t IS LATCHED INPUT LATCH ENABLE t ICO COMBINATORIAL OUTPUT[...]

  • Page 23

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 23 of 64 Latched Inpu t and Output Asynchronous Rese t Asynchronous Prese t Output Enable/Disabl e Switching W aveforms (continued) t ICS LATCHED INPUT OUTPUT LATCH ENABL E LATCHED OUTPUT t PDLL LATCH ENABLE t WL t WH t ICOL INPUT LATCH ENABL E t SL t HL INPUT t RO REGISTERED OUTPUT CLOCK t [...]

  • Page 24

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 24 of 64 Power Consumption T ypical 5.0V Power Consumption CY37032 CY37064 0 10 20 30 40 50 60 0 50 100 150 200 250 Fr equency ( M Hz) Icc (mA) Hi gh S peed Low P ower The typical pattern is a 16-bit up counter , per logic block, with outputs disabl ed. V CC = 5.0V , T A = Room T emperature [...]

  • Page 25

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 25 of 64 CY37128 CY37192 T ypical 5.0V Power Consumption (continu ed) 0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160 180 Fr equency ( M H z) Icc (mA) Low P ower Hi gh Speed The typical pattern is a 16-bit up counter , per logic block, with outputs disabled. V CC = 5.0V , T A = R[...]

  • Page 26

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 26 of 64 CY37256 CY37384 T ypical 5.0V Power Consumption (continu ed) 0 50 100 150 200 250 300 0 20 40 60 80 100 120 140 160 180 Fr equency ( M H z) Icc (mA) Low P ower Hi gh Speed The typical pattern is a 16-bit up counter , per logic block, with outputs disabled. V CC = 5.0V , T A = Room T[...]

  • Page 27

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 27 of 64 CY37512 T ypical 5.0V Power Consumption (continu ed) 0 100 200 300 400 500 600 0 20 40 60 80 100 120 140 160 Fr equency ( M H z) Icc (mA) Low P ower Hi gh S pe ed The typical pattern is a 16-bit up co unter , per logic block, with output s disabled. V CC = 5.0V , T A = Room T empera[...]

  • Page 28

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 28 of 64 CY37064V CY37128V T ypical 3.3V Power Consumption (continu ed) 0 5 10 15 20 25 30 35 40 45 0 20 40 60 80 100 120 140 Fr equency ( MH z) Icc (mA) Low Pow er Hi gh Speed The typical patter n is a 16-bit up counter , per logic block, with outputs disabled. V CC = 3.3V , T A = Room T em[...]

  • Page 29

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 29 of 64 CY37192V CY37256V T ypical 3.3V Power Consumption (continu ed) 0 20 40 60 80 100 120 0 20 40 60 80 100 120 Fr equency ( M H z) Icc (mA) Low P ow er Hi g h Sp e e d The typical pattern is a 16-bit up counter , per logic block, with outputs disabled. V CC = 3.3V , T A = Room T emperat[...]

  • Page 30

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 30 of 64 CY37384V CY37512V T ypical 3.3V Power Consumption (continu ed) 0 20 40 60 80 100 120 140 160 180 200 0 1 02 03 04 05 06 07 08 09 0 Fr equency (MH z) Icc (mA) Low P ow er Hi gh Speed The typical pattern is a 16-bit up counter , per logic block, with outputs disabled. V CC = 3.3V , T [...]

  • Page 31

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 31 of 64 Pin Configurations [20] 44-pin TQFP (A44) Top View I/O 2 GND V CCO I/O 3 I/O 4 I/O 1 I/O 0 I/O 29 I/O 30 I/O 31 I/O 28 I/O 27 /TDI I/O 26 I/O 25 I/O 24 CLK 1 /I 4 GND I 3 CLK 3 /I 2 I/O 23 I/O 22 I/O 21 GND I/O 20 V CC I/O 18 I/O 17 I/O 16 I/O 15 I/O 14 I/O 12 I/O 5 /TCK I/O 6 I/O 7[...]

  • Page 32

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 32 of 64 Note: 20. For 3.3V versions (Ultra37000V), V CCO = V CC . Note: 21. This pin is a N/C, but Cypress recommends that you connect it to V CC to ensure future compatibility . Pin Configurations [20] (continued) 48-ball Fine-Pitch BGA (BA50) T op View 12345678 A I/O 5 TCK V CC I/O 3 I/O [...]

  • Page 33

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 33 of 64 Pin Configurations [20] (continued) Top View 100-lead TQFP (A100) 100 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 30 29 31 32 35 34 36 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 TDI NC V CCO I/O 55 I/O 54 I/O 53[...]

  • Page 34

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 34 of 64 Pin Configurations [20] (continued) 100-ball Fine-Pitch BGA (B B100) for CY37064V To p V i e w 100-ball Fine-Pitch BGA (B B100) for CY37128V To p V i e w 123456789 1 0 A N C NC I/O 7 I/O 5 I/O 2 I/O 62 I/O 60 I/O 58 I/O 57 I/O 56 BI / O 9 I/O 8 I/O 6 I/O 4 I/O 1 I/O 63 V CC I/O 59 I[...]

  • Page 35

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 35 of 64 Pin Configurations [20] (continued) I/O 77 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 43 44 160 45 159 46 158 47 157 48 156 49 155 50 154 51 153 52 152 53 151 54 150 55 149 56 148 5[...]

  • Page 36

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 36 of 64 Pin Configurations [20] (continued) I/O 72 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 43 44 160 45 159 46 158 47 157 48 156 49 155 50 154 51 153 52 152 53 151 54 150 55 149 56 148 5[...]

  • Page 37

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 37 of 64 Pin Configurations [20] (continued) I/O 152 I/O 154 I/O 153 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 41 42 43 44 45 46 47 48 49 50 51 52 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 [...]

  • Page 38

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 38 of 64 Pin Configurations [20] (continued) 292-Ball PBGA (BG292) T op View 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 9 2 0 AG N D I / O 21 NC I/O 16 I/O 12 I/O 9 I/O 7 I/O 4 I/O 0 I/O 190 I/O 189 I/O 186 I/O 182 NC I/O 178 I/O 175 NC NC I/O 169 I/O 168 A B I/O 23 I/O 20 I/O 19 I/O 18 [...]

  • Page 39

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 39 of 64 Pin Configurations [20] (continued) 256-Ball Fine-Pitch BGA (BB256) T op View 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 A GND GND I/O 26 I/O 24 I/O 20 V CC I/O 11 GND GND I/O 186 V CC I/O 177 I/O 17 2 I/O 167 GND GND B GND I/O 27 I/O 25 I/O 23 I/O 19 I/O 15 I/O 10 GND GND I/O 185 I/O 18[...]

  • Page 40

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 40 of 64 Pin Configurations [20] (continued) 388-Lead PBGA (BG388) To p V i e w 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 AG N D G N D I / O 19 I/O 15 I/O 13 I/ O 34 I/O 31 I/O 28 I/O 25 I/O 10 I/ O 7 I/O 4 I/O 1 I/O 263 I/O 260 I/O 257 I/O 254 I/O 239 I/O[...]

  • Page 41

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 41 of 64 Pin Configurations [20] (continued) 400-Ball Fine-Pitch BGA (BB400) T op View A GND GND NC I/O 17 I/O 16 I/O 14 I/O 29 V CC I/O 11 GND GND I/O 257 V CC I/O 239 I/O 233 I/O 232 I/O 230 NC GND GND B GND GND GND NC I/O 15 I/O 13 I/O 28 V CC I/O 10 GND GND I/ O 256 V CC I/O 238 I/O 231 [...]

  • Page 42

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 42 of 64 Ordering Information 5.0V Ordering Information Macrocells Spee d (MHz) Ordering Code Package Name Package T ype Operating Range 32 200 CY37032P44-200AC A44 44-Lead Thin Quad Flat Pack Commercial CY37032P44-200AXC A4 4 44-Lead Lead Free T hin Quad Flat Pack CY37032P44-200JC J67 44-Le[...]

  • Page 43

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 43 of 64 64 154 CY37064P44-154AC A44 44-Lead Thin Quad Flat Pack Commercial CY37064P44-154JC J67 44-Lead Plastic Lea ded Chip Carrier CY37064P84-154JC J83 84-Lead Plastic Lea ded Chip Carrier CY37064P100-154AC A100 100-Lead Thin Quad Flat Pack CY37064P44-154AI A4 4 44-Lead Thin Quad Flat Pac[...]

  • Page 44

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 44 of 64 128 167 CY37128P84 -167JC J83 84-Lead Plastic Leaded Chip Carrier Commercial CY37128P84-167JXC J83 84-L ead Lead Free Plastic Leaded Chip Carri er CY37128P100-167AC A100 100-Lead Thin Quad Flat Pack CY37128P100-167AXC A100 100-Lead Lead Free Thin Quad Flat Pack CY37128P160-167AC A16[...]

  • Page 45

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 45 of 64 256 154 CY372 56P160-154AC A160 160-Lead Thin Quad Flat Pack Commercial CY37256P160-154AXC A160 160-Lead Lead Free Thin Quad Flat Pack CY37256P208-154NC N208 208-Lead Plastic Quad F lat Pack CY37256P256-154BGC BG292 292-Ball Plastic Ball Gri d Array 125 CY37256P160-125AC A160 160-Le[...]

  • Page 46

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 46 of 64 512 125 CY37512P20 8-125NC N208 208-Lead Pl asti c Quad Flat Pack Commercial CY37512P256-125BGC BG292 292-Ball Plastic Ball Gri d Array CY37512P352-125BGC B G388 388-Ball Plastic Ball Gri d Array 100 CY37512P208-100NC N208 208-Lead Plas tic Quad Flat Pack Commercial CY37512P256-100B[...]

  • Page 47

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 47 of 64 64 143 CY37064VP44-143AC A44 44-Lea d Thin Quad Flatpack Commercial CY37064VP44-143AXC A44 4 4-Lead Lead Free Thin Quad Flatpack CY37064VP48-143BAC BA50 48-Ball Fine-Pitch Ball Grid Array CY37064VP100-143AC A1 00 100-Lead Thin Quad Flatpack CY37064VP100-143AXC A1 00 100-Lead Lead Fr[...]

  • Page 48

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 48 of 64 256 100 CY37256VP160-100AC A1 60 160-Lead Thin Quad Flat Pack Commercial CY37256VP160-100AXC A1 60 160-Lead Lead Free Thin Quad Flat Pack CY37256VP208-100NC N 208 208-Lead Plastic Quad Flat Pack CY37256VP256-100BGC BG292 292-Ball Pl astic Ball Grid Array CY37256VP256-100BBC BB 256 2[...]

  • Page 49

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 49 of 64 Package Diagrams 51-85064- * B 44-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack A44 51-85003- * A 44-Lead Lead (Pb)-Free Plastic Lead ed Chip Carrier J67 [+] Feedback[...]

  • Page 50

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 50 of 64 Package Diagrams (continued) 44-Lead Ceramic Leaded Chip Car rier Y67 51-80014 -** [+] Feedback[...]

  • Page 51

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 51 of 64 Package Diagrams (continued) 48-Ball (7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch) Thin BGA BA48D 51-85109-*C 51-85006- * A 84-Lead Lead (Pb)-Free Plastic Lead ed Chip Carrier J83 [+] Feedback[...]

  • Page 52

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 52 of 64 Package Diagrams (continued) 84-Lead Ceramic Leaded Chip C arrier Y84 51-80095- * A [+] Feedback[...]

  • Page 53

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 53 of 64 Package Diagrams (continued) 51-85048- * B 100-Lead Lead (Pb)-Free Thin Plastic Quad F lat Pack (TQFP) A100 [+] Feedback[...]

  • Page 54

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 54 of 64 Package Diagrams (continued) 100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100 51-85107-*B [+] Feedback[...]

  • Page 55

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 55 of 64 Package Diagrams (continued) 51-85049-* B 160-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack (24 x 24 x 1.4 mm) (TQFP) A160 [+] Feedback[...]

  • Page 56

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 56 of 64 Package Diagrams (continued) SEATING PLANE DIMENSION IN MM (INCH) 2.79(.110) 2.03(.080) 0.500(.020) 0.050(.002) (.020 ±.008) 0.51 ±0.20 (.006 ±.001) 0.15 ±0.02 TYP. 0.300(.012) TYP. 0.650(.0256) (1.228 ±.010) 31.20 ±0.25 (1.102 ±.004) 28.00 ±0.10 SQ. SQ. PIN 1 25.35±0.10 (.[...]

  • Page 57

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 57 of 64 Package Diagrams (continued) 208-Lead Plastic Qu ad Flatpack N208 51-85069-*B [+] Feedback[...]

  • Page 58

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 58 of 64 Package Diagrams (continued) SEATING PLANE DIMENSIONS IN MM (INCH) 0.500(.020) 0.050(.002) 3.94(.155) 3.43(.135) (.006 ±.001) 0.15 ±0.02 (.020 ±.008) 0.51 ±0.20 (1.229 ±.010) 31.22 ±0.25 (1.102 ±.008) 28.00 ±0.10 TYP. 0.50(.0197) TYP. 0.20(.008) SQ. SQ. PIN 1 SEE DETAIL A (.[...]

  • Page 59

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 59 of 64 Package Diagrams (continued) BOTTOM VIEW TOP VIEW 1 0 987654 32 1 A B C D E F G H J K PIN 1 CORNER PIN 1 CORNER 0.20(4X) Ø 0 . 2 5MCAB Ø0.05 M C Ø0.45±0.05(256X)-CPLD DEVICES (37K & 39K) 0.25 C 0.70±0.05 C SEATING PLANE 0.15 C 16 15 14 13 12 11 T R P M N L N T R P M L K J F[...]

  • Page 60

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 60 of 64 Package Diagrams (continued) 292-Ball Plastic Ball Grid Array PBGA (27 x 27 x 2.33 mm) BG292 51-85097-*B [+] Feedback[...]

  • Page 61

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 61 of 64 Package Diagrams (continued) 51-85103-*C 388-Ball Plastic Ball Grid Array PBGA (35 x 35 x 2.33 mm) BG388 [+] Feedback[...]

  • Page 62

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 62 of 64 © Cypress Semi conductor Corpora tion, 2005. The i nformation cont ained here in is subject to ch ange withou t notice. Cypress S emic onductor Corporation assu mes no responsibility for the use of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor does it co[...]

  • Page 63

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 63 of 64 Addendum 3.3V Operating Range (CY37064VP100-143AC, CY37064 VP100-143BBC , CY37064VP44-1 43AC, CY37064VP48-143B AC) Range Ambient T emperature [2] Jun ction T emp erature V CC Commercial 0°C to +70°C 0°C to +90°C 3.3V ± 0.16V [+] Feedback[...]

  • Page 64

    Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 64 of 64 Document History Page Document Title: Ultra37000 CPLD Family 5V , 3.3V , ISR™ High-Performanc e CPLDs Document Number: 38-03007 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 106272 04/18/01 SZV Change from S p ec n umber: 38-00475 to 38-03007 *A 124942 03/21/03[...]